Abstract: Semiconductor device (100) performance is improved via a gate structure (120) having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment of the present invention, the design threshold voltage of a semiconductor device (100) is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device (100) at a selected voltage. The gate is formed having two different conductive materials (130, 135) with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive material is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device (100). In addition, by selecting the order of the layers, carrier depletion in the gate electrode can be avoided.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.

Abstract: This invention relates to a process of forming a transistor with three vertical gate electrodes and the resulting transistor. By forming such a transistor it is possible to maintain an acceptable aspect ratio as MOSFET structures are scaled down to sub-micron sizes. The transistor gate electrodes can be formed of different materials so that the workfunctions of the three electrodes can be tailored. The three electrodes are positioned over a single channel and operate as a single gate having outer and inner gate regions.

Abstract: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.

Abstract: The present invention provides an alloy system as metal gate material of MOSFET devices that can solve the issue of work function incompatibility of metal gate and then can achieve low threshold voltage of surface channel MOSFETs effectively to satisfy the requirement of low voltage and high performance operation. To achieve this purpose, a chemically inert and thermally stable element, platinum (Pt), with high work function is selected as the basic component, which is doped with low work function element, such as tantalum (Ta), or titanium (Ti) to various atomic ratios. The work function can be adjusted to arbitrary value depends on the atomic ratio of element.

Abstract: A complementary integrated circuit comprises: an n-channel element having a gate electrode in which at least a portion contacting a gate insulating film is made of a first metal material having a work function close to the work function of n-type polysilicon; and a p-channel element having a gate electrode in which at least a portion contacting a gate insulating film is made of a second metal material having a work function close to the work function of p-type polysilicon. Preferably, the first metal material consists of a material selected from a group consisting of zirconium and hafnium, and the second metal material consists of a material selected from a group consisting of platinum silicide, iridium silicide, cobalt, nickel, rhodium, palladium, rhenium and gold. Alternatively, the first metal material may consist of a material selected from a group consisting of zirconium and hafnium, and the second metal material may consist of rhenium.

Abstract: A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.

Abstract: A new multilayer dielectric film for improving dielectric constant and thermal stability of gate dielectrics is provided. The multilayer dielectric film comprises a first layer formed of a metal oxide material having a high dielectric constant, and a second layer formed on the first layer. The second layer is formed of a metal silicate material having a dielectric constant lower than the dielectric constant of the first layer. A semiconductor transistor incorporating the multilayer dielectric film is also provided.

Abstract: The present invention provides a semiconductor device and a method of manufacturing the same improved in reliability of a gate insulating film by increasing a total charge amount Qbd by suppressing a film stress of a gate electrode formed of a polysilicon film, to a low value. Since the film stress is closely related to a film formation temperature, it is possible to reduce the film stress lower than the conventional case by forming a film at as a high temperature as 640° C. or more. At this time, when the film stress decreases, the total charge amount Qbd regulating dielectric breakdown of the film increases, improving reliability of the gate insulating film. It is therefore possible to set the film stress of the gate electrode at 200 MPA or less in terms of absolute value by forming the gate electrode at 640° C. or more.

Abstract: An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substantially near mid-gap work function or greater. The DRAM also includes a peripheral area including a plurality of logic transistors. In a preferred embodiment the pass gate transistors are silicon-on-insulator transistors.

Abstract: A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integrated circuit gives the device the electrical performance and doping qualities of a polysilicon gate and also gives the device the smoothness of an amorphous silicon gate which improves line definition during gate patterning.

Abstract: Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate includes a ternary metallic conductor formed by atomic layer deposition.

Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer. The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers.

Abstract: An integrated circuit can include gate structures designed to effect a work function of a transistor. A first set of gate structures can have a first work function and a second set of gate structures can have a second work function. The gate structures include metal layers to affect changes in the work function. The work function can affect the threshold voltage associated with the transistors. The transistor can be built on a silicon-on-insulator substrate.

Abstract: An MIS transistor that permits freely controlling in a continuous manner a work function in relation to a gate insulation film of a gate electrode to values that differ from a characteristic value of the material that constitutes the gate electrode and, as a result, permits continuously controlling a Vth. For MIS transistors (100A) and (100B), the gate electrode (10) has a multi layer structure of metal layers (11), (12), (13) of metals having distinct work functions and, moreover, the first metal layer (11) that is in contact with the gate insulation film (2) is formed at film thickness of 5 debye length of less, by atomic layer CVD.

Abstract: The field-effect transistor has an insulated gate, a source electrode, a drain electrode, and an inversion channel between the source and drain electrodes and underneath the gate electrode. The gate electrode is fabricated from a material which does not have a permitted energy state in the energy interval which is used to control the charge carrier density in the inversion channel between the source electrode and the drain electrode.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure.

Abstract: A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.

Abstract: A method for fabricating metal gates in deep sub-micron CMOS devices. The method blanket deposits a transition metal nitride layer on top of a gate dielectric layer for forming gate electrodes for both a PMOS and an NMOS device. After a cap layer is deposited on top of the gate electrode for PMOS, a rapid thermal annealing process is carried out to drive out nitrogen from the transition metal nitride on top of the NMOS. Gate electrodes having different work functions on top of the PMOS and NMOS are thus achieved simultaneously by the same fabrication process.

Abstract: A metal gate structure and method of forming the same introduces metal impurities into a first metal layer, made of TiN, for example. The impurities create a surface region of greater etch selectivity that prevents overetching of the TiN during the etching of an overlying tungsten gate during the formation of the metal gate structure. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum as the metal impurities provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.

Abstract: Integrated power devices include a plurality of field effect transistor unit cells and a Faraday shield layer that reduces parasitic gate-to-drain capacitance (Cgd) and concomitantly improves high frequency switching performance. These power devices may include a field effect transistor in an active portion of a semiconductor substrate and a gate electrode that is electrically connected to a gate of the field effect transistor. A Faraday shield layer is provided between at least a first portion of the gate electrode and a drain of the field effect transistor in order to capacitively decouple the first portion of the gate electrode from the drain. The gate electrode and drain typically extend adjacent opposing faces of the semiconductor substrate. The Faraday shield layer is preferably electrically connected to a source of the field effect transistor and provides edge termination.

Abstract: A dual work function CMOS metal gate device provides a composite metal gate electrode structure. The composite metal gate structure includes a bulk metal and a thin metal layer having an appropriate work function for the transistor type and desired threshold voltage, VT. Both N-channel and P-channel transistors are formed to have distinct threshold voltages by incorporating the metal material having the appropriate work function for the desired VT into the composite metal gate electrode. The two different electrodes of the N-channel and P-channel transistors are electrically connected by means of the bulk metal.

Abstract: A semiconductor device including: a gate electrode made from silicon-germanium or germanium; a first semiconductor region formed under the gate electrode with a first gate insulating film between the first semiconductor region and the gate electrode; and a second semiconductor region formed over the gate electrode with a second gate insulating film between the second semiconductor region and the gate electrode, wherein a first conductivity type MOS transistor includes the first semiconductor region, the first gate insulating film, and the gate electrode, and a second conductivity type MOS transistor includes the second semiconductor region, the second gate insulating film, and the gate electrode.

Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.

Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

Abstract: In one embodiment, a method of making a gate stack semiconductor device is disclosed. The method comprises the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer and subjecting the n-type polysilicon layer to nitridation, and then forming a p-type polysilicon layer over the nitridated n-type polysilicon layer; and forming a high-K insulating layer over the p-type polysilicon layer.

Abstract: An asymmetric semiconductor device and a method of making a pair of the asymmetric devices. The semiconductor device includes a layer of semiconductor material having a source and a drain, and a dual work function gate disposed on the layer of semiconductor material to define a channel interposed between the source and the drain.

Abstract: A gate structure for a MOSFET device comprises a gate insulation layer, a first layer of a first metal abutting the gate insulation layer, and a second layer overlying the first layer and comprising a mixture of the metal of the first layer and a second metal, the metal layers formed by the diffusion of the first metal into and through the second metal. The second metal can be used as the gate for a n-MOS transistor, and the mixture of first metal and second metal overlying a layer of the first metal can be used as a gate for a p-MOS transistor where the first metal has a work function of about 5.2 eV and the second metal has a work function of about 4.1 eV.

Abstract: An asymmetric semiconductor device and a method of making a pair of the asymmetric devices. The semiconductor device includes a layer of semiconductor material having a source and a drain, and a dual work function gate disposed on the layer of semiconductor material to define a channel interposed between the source and the drain.

Abstract: On a semiconductor substrate of P-type silicon, an active area including a channel forming region with a smaller dimension along the gate width and a source region and a drain region extending along the gate length is formed so as to be surrounded with an isolation area of an insulating oxide film. On the isolation area on the semiconductor substrate and the channel forming region of the active area, a gate electrode is formed with a gate insulating oxide film sandwiched therebetween. A channel lower insulating layer is formed, out of the same insulating oxide film for the isolation area, merely in an area below the channel forming region below the gate electrode in the active area of the semiconductor substrate.

Abstract: A buried channel device structure for an electrostatic discharge protection circuit capable of minimizing the effect on the electrostatic discharge protection circuit due to current flowing close to gate oxide layer. A p+ ion-doped region is formed above a p-type substrate. The p+ ion-doped region serves as a gate terminal. A first and a second n+ ion-doped region are also formed in the p-type substrate on each side of the p+ gate terminal. In addition, an n-doped region is formed in the p-type substrate under the p+ gate terminal between the first and the second n+ ion-doped region. A similar buried channel device structure can also be formed on an n-type structure.

Abstract: A parallel connection-type nonvolatile memory semiconductor device comprises a plurality of memory cells disposed on a semiconductor substrate in matrix form, each including a gate insulating film, a floating gate electrode, an interlayer film and a control gate electrode successively formed so as to cover a channel region on a main surface of the semiconductor substrate, of a first conductivity type; a second conductivity type source and drain regions formed on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing a second conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially lower than the drain region in impurity concentration; and a punch-th

Abstract: A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure.

Abstract: The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions.

Abstract: A method of forming a diffusion barrier layer in a semiconductor device is disclosed. A high-k gate dielectric layer is formed over a substrate. A silicon nitride barrier layer is subsequently formed over the high-k gate dielectric layer by reacting tetrachlorosilane with ammonia through a chemical vapor deposition process. The silicon nitride barrier layer substantially blocks diffusion of impurities from an ensuing overlying gate layer. A semiconductor device comprising the silicon nitride barrier layer, and a method of fabricating such a semiconductor device are also disclosed.

Abstract: A semiconductor device has a semiconductor substrate, a first transistor having a first gate electrode formed of a polycrystalline silicon germanium film as formed above said semiconductor substrate, and a second transistor having a second gate electrode which is formed of a polycrystalline silicon germanium film as formed above the semiconductor substrate and which is different in concentration of germanium from the first gate electrode.

Abstract: A semiconductor integrated circuit device wherein plural field effect transistors having different threshold values are integrated on one chip by forming plural gate electrodes of silicon-germanium mixed crystals having different germanium contents. By varying the germanium content of the gate electrode material, a work function with respect to the channel region can be varied, so a semiconductor integrated circuit device wherein plural field effect transistors having different threshold voltage values are integrated on one chip can be manufactured.

Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function.

Abstract: A stratum or discontinuous monolayer of dielectric-coated semiconductor particles includes a high density of semiconductor nanoparticles with a tightly controlled range of particle sizes in the nanometer range. In an exemplary embodiment, the nanoparticles of the stratum are substantially the same size and include cores which are crystalline, preferably single crystalline, and include a density which is approximately the same as the bulk density of the semiconductor material of which the particle cores are formed. In an exemplary embodiment, the cores and particles are preferably spherical in shape. The stratum is characterized by a uniform particle density on the order of 1012 to 1013 particles/cm2. A plurality of adjacent particles contact each other, but the dielectric shells provide electrical isolation and prevent lateral conduction between the particles of the stratum. The stratum includes a density of foreign atom contamination of less than 1011 atoms/cm2.

Abstract: The present invention relates to a silicon-on-insulator (SOI) substrate, a method for fabricating the SOI substrate and a SOI MOSFET using the SOI substrate to easily migrate the design applied to a conventional bulk silicon substrate to the SOI design and to remove a floating body effect. The SOI substrate includes a mono-silicon substrate, a buried oxide layer formed over the surface of the mono-silicon substrate, and a thin mono-silicon layer formed over the surface of the buried oxide layer. Conductive layers are formed at through holes of the buried oxide layer positioned between the predetermined regions of the thin layer and the substrate for body contacts. Therefore, additional layout spaces are not needed for body contacts and the constant body contact resistance can allow the conventional circuit design applied to die bulk silicon substrate to be migrated to the circuit design applied to the SOI substrate without any modifications.

Abstract: A MOSFET and methods of fabrication. The MOSFET includes a gate having a center gate electrode portion being spaced from the layer of semiconductor material by a center gate dielectric. The gate also includes a lateral gate electrode portion adjacent each sidewall of the center gate electrode portion. The lateral gate electrode portions are each spaced from the layer of semiconductor material by a lateral gate dielectric portion.

Abstract: An aspect of the present invention includes a first conductive type semiconductor region formed in a semiconductor substrate, a gate electrode formed on the first conductive type semiconductor region, a channel region formed immediately below the gate electrode in the first conductive type semiconductor region, and a second conductive type first diffusion layers constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which the germanium concentration of at least one of the source side and the drain side is higher than that of the central portion.

Abstract: The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions.

Abstract: This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure provides for increased density and enables ultra low power to be utilized. The methods also provide for simultaneously making both four-terminal and dynamic threshold MOSFET devices.

Abstract: In a semiconductor device including a plurality of n-channel transistors having different threshold voltages and each having a gate electrode including an n-type polysilicon film, the impurity concentration of the n-type polysilicon film included in the gate electrode of an n-channel transistor having a relatively high threshold, is lower than the impurity concentration of the n-type polysilicon film included in the gate electrode of an n-channel transistor having a relatively low threshold. Thus, the n-channel transistor having a relatively high threshold can be realized in the semiconductor device, without various problems such as an increased leak current caused by increasing the impurity concentration of the channel region, the lowered subthreshold factor caused by using the p+ polysilicon film in the gate electrode, the deteriorated insulating performance of the gate oxide film, the increased number of fabricating steps, or the dropped reliability of the transistor.

Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function.

Abstract: A MOSFET and method of fabrication. The MOSFET includes a metal containing source and a metal containing drain; a semiconductor body having a thickness of less than about 15 nm disposed between the source and the drain and on top of an insulating layer, the insulating layer formed on a substrate; a gate electrode disposed over the body and defining a channel interposed between the source and the drain; and a gate dielectric made from a high-K material and separating the gate electrode and the body.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.