Including Lightly Doped Drain Portion Adjacent Channel (e.g., Lightly Doped Drain, Ldd Device) Patents (Class 257/408)
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Publication number: 20120098072Abstract: Semiconductor devices are provided including a gate across an active region of a substrate; a source region and a drain region in the active region on either side of the gate and spaced apart from each other; a main channel impurity region in the active region between the source and drain regions and having a first channel impurity concentration; and a lightly doped channel impurity region in the active region adjacent to the drain region. The lightly doped channel impurity region has the same conductivity type as the main channel impurity region and a second channel impurity concentration, lower than the first channel impurity concentration. The lightly doped channel impurity region and the main channel impurity region contain a first element. The lightly doped channel impurity region also contains a second element, which is a different Group element from the first element.Type: ApplicationFiled: October 20, 2011Publication date: April 26, 2012Inventors: Seung-Uk Han, Min-Chul Park, Young-Jin Choi, Nam-Ho Jeon
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Patent number: 8163619Abstract: An asymmetric insulated-gate field effect transistor (100U or 102U) is provided along an upper surface of a semiconductor body so as to have first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima at respective locations (PH-1-PH-3-NH-3) spaced apart from one another. This typically enables the transistor to have reduced current leakage.Type: GrantFiled: March 27, 2009Date of Patent: April 24, 2012Assignee: National Semiconductor CorporationInventors: Jeng-Jiun Yang, Constantin Bulucea, Sandeep R. Bahl
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Patent number: 8159036Abstract: A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of the second conduction type is formed in the surface of the semiconductor layer at a position sandwiching the gate electrode with the LDD layer. A drain layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the resurf layer. The resurf layer is formed in depth to have peaks of a first and a second impurity concentration in turn from the surface of the semiconductor layer. The peak of the first impurity concentration is smaller than the peak of the second impurity concentration.Type: GrantFiled: June 18, 2008Date of Patent: April 17, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tomoko Matsudai, Norio Yasuhara, Manji Obatake
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Patent number: 8158482Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.Type: GrantFiled: September 2, 2009Date of Patent: April 17, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
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Patent number: 8159033Abstract: A junction forming region is formed between a drain region of a MOS structure and a device isolation region which surrounds the MOS structure and is in contact with the drain region, to form a PN junction together with the drain region. As a consequence, it is possible to adjust a breakdown voltage of an ESD protection device which is fabricated in the same process as that for an internal device without varying basic performance of the internal device even at a final stage of an LSI manufacturing process.Type: GrantFiled: March 4, 2009Date of Patent: April 17, 2012Assignee: Lapis Semiconductor Co., Ltd.Inventor: Hirokazu Hayashi
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Patent number: 8159051Abstract: In one aspect of the present invention, a semiconductor device may include a first semiconductor layer of a first conductivity type and having a main surface that has a first plane orientation, a second semiconductor layer of the first conductivity type and having a main surface that has a second plane orientation different from the first plane orientation, the second semiconductor layer being directly provided on the first semiconductor layer, a third semiconductor layer having a main surface that has the first plane orientation, and being formed on the first semiconductor layer and on a side face of the second semiconductor layer, a gate electrode formed on the second semiconductor layer via a gate insulating film, first impurity diffusion regions of a second conductivity type, and being formed in the second semiconductor layer so that the gate electrode is located on a region sandwiched in a gate length direction between the first impurity diffusion regions, the first impurity diffusion regions extending tType: GrantFiled: September 14, 2009Date of Patent: April 17, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Nobuaki Yasutake
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Patent number: 8148777Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 500, 510, or 530; or 220, 220W, or 540) is provided with a hypoabrupt vertical dopant profile below one (104; or 264 or 564) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108; or 268 or 568). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone.Type: GrantFiled: September 15, 2010Date of Patent: April 3, 2012Assignee: National Semiconductor CorporationInventor: Constantin Bulucea
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Patent number: 8143139Abstract: A method of fabricating an extended drain MOS transistor which reduces a design rule and prevents the generation of leakage current. The method includes sequentially forming a diffusion film, a first conductive epitaxial layer, a gate oxide layer and a hard mask layer over a semiconductor substrate, forming a first hard mask pattern having a first thickness by performing a first etching process on the hard mask layer, forming a second hard mask pattern having a second thickness by performing a second etching process on the first hard mask layer, and then forming a thin gate oxide layer by performing a third etching process on the gate oxide layer using the second hard mask pattern as a mask.Type: GrantFiled: August 25, 2008Date of Patent: March 27, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Kyoung-Jin Lee
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Patent number: 8143131Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.Type: GrantFiled: March 31, 2009Date of Patent: March 27, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Pin Hsu, Kong-Beng Thei, Harry Chuang
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Patent number: 8143677Abstract: A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.Type: GrantFiled: February 25, 2010Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Myoung-Soo Kim
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Patent number: 8138559Abstract: A high-voltage metal-oxide-semiconductor (HVMOS) device having increased breakdown voltage and methods for forming the same are provided. The HVMOS device includes a semiconductor substrate; a gate dielectric on a surface of the semiconductor substrate; a gate electrode on the gate dielectric; a source/drain region adjacent and horizontally spaced apart from the gate electrode; and a recess in the semiconductor substrate and filled with a dielectric material. The recess is between the gate electrode and the source/drain region, and is horizontally spaced apart from the gate electrode.Type: GrantFiled: April 3, 2007Date of Patent: March 20, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: William Wei-Yuan Tien, Fu-Hsin Chen
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Patent number: 8138552Abstract: A semiconductor device according to an embodiment of the present invention includes a substrate, a gate insulation film formed on the substrate, a gate electrode formed on the gate insulation film, sidewall insulation films provided on side surfaces of the gate electrode, and stress application layers embedded in source and drain regions located, on a surface of the substrate, at a position which sandwiches the gate electrode, and applying stress to a channel region located under the gate insulation film in the substrate, a height of upper ends of interfaces between the substrate and the stress application layers being higher than a height of a lower end of an interface between the substrate and the gate insulation film.Type: GrantFiled: December 18, 2008Date of Patent: March 20, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Kouji Matsuo
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Publication number: 20120056276Abstract: The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.Type: ApplicationFiled: September 3, 2010Publication date: March 8, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Chun-Fai Cheng, Ka-Hing Fung, Shyh-Wei Wang, Chin-Te Su
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Publication number: 20120056277Abstract: The present invention provides a semiconductor device including a semiconductor substrate having a first conductive type, at least one high-side transistor device and at least one low-side transistor device. The high-side transistor device includes a doped high-side base region having a second conductive type, a doped high-side source region having the first conductive type and a doped drain region having the first conductive type. The doped high-side base region is disposed within the semiconductor substrate, and the doped high-side source region and the doped drain region are disposed within the doped high-side base region. The doped high-side source region is electrically connected to the semiconductor substrate, and the semiconductor substrate is regarded as a drain of the low-side transistor device.Type: ApplicationFiled: January 26, 2011Publication date: March 8, 2012Inventor: Wei-Chieh Lin
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Patent number: 8120074Abstract: A bipolar semiconductor device with a hole current redistributing structure and an n-channel IGBT are provided. The n-channel IGBT has a p-doped body region with a first hole mobility and a sub region which is completely embedded within the body region and has a second hole mobility which is lower than the first hole mobility. Further, a method for forming a bipolar semiconductor device is provided.Type: GrantFiled: October 29, 2009Date of Patent: February 21, 2012Assignee: Infineon Technologies Austria AGInventors: Hans-Joachim Schulze, Francisco Javier Santos Rodriguez
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Patent number: 8120109Abstract: A semiconductor device for reducing junction capacitance by an additional low dose super deep source/drain implant and a method for its fabrication are disclosed. In particular, the super deep implant is performed after spacer formation to significantly reduce junction capacitance in the channel region.Type: GrantFiled: July 22, 2004Date of Patent: February 21, 2012Assignee: Micron Technology, Inc.Inventors: Zhongze Wang, Inna V. Patrick
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Patent number: 8120092Abstract: First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.Type: GrantFiled: September 23, 2009Date of Patent: February 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Sato, Fumitaka Arai
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Publication number: 20120038008Abstract: In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, forming an ion doped drain extension portion in the substrate, forming a first spacer portion adjacent to the dummy gate stack, removing the dummy gate stack to expose a channel region of the substrate, a portion of the ion doped source extension portion, and a portion of the ion doped drain extension portion, forming a second spacer portion on the exposed portion of the ion doped source extension portion and on the exposed portion of the ion doped drain extension portion, and forming a gate stack on the exposed channel region of the substrate.Type: ApplicationFiled: August 16, 2010Publication date: February 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Pranita Kulkarni, Ramachandran Muralidhar, Chun-Chen Yeh
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Publication number: 20120038007Abstract: A method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, the source extension portion extending from the source region into the first portion of the substrate, forming an ion doped drain extension portion in the substrate, the drain extension portion extending from the drain region into the first portion of the substrate, removing a portion of the dummy gate stack to expose an interfacial layer of the dummy gate stack, implanting ions in the source extension portion and the drain extension portion to form a channel region in the first portion of the substrate, removing the interfacial layer, and forming a gate stack on the channel region of the substrate.Type: ApplicationFiled: August 16, 2010Publication date: February 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Pranita Kulkarni, Ramachandran Muralidhar, Chun-Chen Yeh
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Publication number: 20120032278Abstract: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.Type: ApplicationFiled: October 13, 2011Publication date: February 9, 2012Inventors: Thorsten Kammler, Andy Wei, Ina Ostermay
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Publication number: 20120032277Abstract: A semiconductor device includes a MOS transistor. The MOS transistor includes a pair of first, second, and third impurity diffusion regions. The second impurity diffusion regions have a first conductive type and are provided in a semiconductor substrate in opposite sides of the first impurity diffusion region. The impurities concentration of the first conductive type in the second impurity diffusion regions is higher than the impurities concentration of the first conductive type in the first impurity diffusion regions. The third impurity diffusion regions have a second conductive type and are provided in the semiconductor substrate such that it contacts not the second impurity diffusion regions, but the first impurity diffusion regions.Type: ApplicationFiled: August 1, 2011Publication date: February 9, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Kazutaka MANABE
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Patent number: 8110897Abstract: The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity.Type: GrantFiled: March 3, 2010Date of Patent: February 7, 2012Assignee: Panasonic CorporationInventor: Taiji Noda
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Patent number: 8106466Abstract: A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.Type: GrantFiled: August 10, 2008Date of Patent: January 31, 2012Assignee: United Microelectronics Corp.Inventors: Po-Lun Cheng, Pin-Chien Chu
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Publication number: 20120018815Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.Type: ApplicationFiled: July 22, 2010Publication date: January 26, 2012Inventors: Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Shiang Yang Ong, Elgin Quek
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Patent number: 8097924Abstract: A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.Type: GrantFiled: June 18, 2004Date of Patent: January 17, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Wang, Shang-Chih Chen, Yen-Ping Wang, Hsien-Kuang Chiu, Liang-Gi Yao, Chenming Hu
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Patent number: 8097518Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.Type: GrantFiled: October 6, 2010Date of Patent: January 17, 2012Assignee: Spansion LLCInventor: Masatomi Okanishi
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Patent number: 8093665Abstract: A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.Type: GrantFiled: May 18, 2009Date of Patent: January 10, 2012Assignee: MACRONIX International Co., Ltd.Inventors: I-Chen Yang, Guan-Wei Wu, Yao-Wen Chang, Tao-Cheng Lu
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Publication number: 20110316093Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Applicant: GLOBALFOUNDRIES Inc.Inventors: Bin Yang, Man Fai NG
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Publication number: 20110316094Abstract: a method comprises forming a hardmask over one or more gate structures. The method further comprises forming a photoresist over the hardmask. The method further comprises forming an opening in the photoresist over at least one of the gate structures. The method further comprises stripping the hardmask that is exposed in the opening and which is over the at least one of the gate structures. The method further comprises removing the photoresist. The method further comprises providing a halo implant on a side of the least one of the at least one of the gate structures.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Darshana N. BHAGAT, Thomas J. DUNBAR, Yen Li LIM, Jed H. RANKIN, Eva A. SHAH
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Patent number: 8084827Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.Type: GrantFiled: March 27, 2009Date of Patent: December 27, 2011Assignee: National Semiconductor CorporationInventors: Constantin Bulucea, William D. French, Donald M. Archer, Jeng-Jiun Yang, Sandeep R. Bahl, D. Courtney Parker
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Patent number: 8084831Abstract: A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first source/drain regions formed in the semiconductor substrate on both sides of the first channel region, the first gate electrode comprising a first metal layer and a first conductive layer thereon; and a p-type transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, and second source/drain regions formed in the semiconductor substrate on both sides of the second channel region, the second gate electrode comprising a second metal layer and a second conductive layer thereon, the second metal layer being thicker than the first metal layer and having the same constType: GrantFiled: August 13, 2009Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masakazu Goto, Shigeru Kawanaka
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Patent number: 8071437Abstract: A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.Type: GrantFiled: November 19, 2009Date of Patent: December 6, 2011Assignee: United Microelectronics Corp.Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong, Ching-Hsiang Tseng
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Publication number: 20110291202Abstract: A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.Type: ApplicationFiled: May 28, 2010Publication date: December 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
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Publication number: 20110281409Abstract: An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region.Type: ApplicationFiled: May 12, 2010Publication date: November 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Kirk D. PETERSON, Jed H. RANKIN
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Patent number: 8053843Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.Type: GrantFiled: June 11, 2009Date of Patent: November 8, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Chi Kang Liu, Ta Lee Yu, Quan Li
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Patent number: 8053847Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.Type: GrantFiled: November 28, 2008Date of Patent: November 8, 2011Assignee: United Microelectronics Corp.Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
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Publication number: 20110266635Abstract: A method for fabricating a native device is presented. The method includes forming a gate structure over a substrate starting at an outer edge of an inner marker region, where the gate structure extends in a longitudinal direction, and performing MDD implants, where each implant is performed using a different orientation with respect to the gate structure, performing pocket implants, where each implant is performed using a different orientation with respect to the gate structure, and concentrations of the pocket implants vary based upon the orientations. A transistor fabricated as a native device, is presented, which includes an inner marker region, an active outer region which surrounds the inner marker region, a gate structure coupled to the inner marker region, and first and second source/drain implants located within the active outer region and interposed between the first source/drain implant and the second source/drain implant.Type: ApplicationFiled: April 29, 2010Publication date: November 3, 2011Applicant: QUALCOMM INCORPORATEDInventors: Shashank S. Ekbote, Rongtian Zhang
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Publication number: 20110266621Abstract: A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.Type: ApplicationFiled: July 11, 2011Publication date: November 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III
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Publication number: 20110266636Abstract: A method for forming an offset spacer of a MOS device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a dielectric stack on the substrate and the gate structure, wherein the dielectric stack comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer; and performing an etching process on the dielectric stack to form an offset spacer around the gate structure.Type: ApplicationFiled: May 3, 2010Publication date: November 3, 2011Inventor: Chun Rong
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Patent number: 8048730Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes an isolation area formed on a semiconductor substrate to define NMOS and PMOS areas, a gate insulating layer and a gate formed on each of the NMOS and PMOS areas, a primary gate spacer formed at sides of the gate, LDD areas formed in the semiconductor substrate at sides of the gate, a secondary gate spacer formed at sides of the primary gate spacer, source and drain areas formed in the semiconductor substrate at sides of the gate of the PMOS area; and source and drain areas formed in the semiconductor substrate at sides of the gate of the NMOS area, wherein the source and drain areas of the NMOS area are deeper than the source and drain areas of the PMOS area.Type: GrantFiled: August 13, 2009Date of Patent: November 1, 2011Assignee: Dongbu Hitek Co., Ltd.Inventor: Eun Jong Shin
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Patent number: 8049275Abstract: There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n?-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n?-type impurity regions overlap with a gate electrode, and the other n?-type impurity regions do not overlap with the gate electrode. Since the two kinds of n?-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.Type: GrantFiled: October 31, 2005Date of Patent: November 1, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8048765Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.Type: GrantFiled: August 28, 2009Date of Patent: November 1, 2011Assignee: Broadcom CorporationInventors: Xiangdong Chen, Bruce Chih-Chieh Shen, Henry Kuo-Shun Chen
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Patent number: 8049281Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.Type: GrantFiled: December 3, 2010Date of Patent: November 1, 2011Assignee: HRL Laboratories, LLCInventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, Paul Ou Yang
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Patent number: 8043923Abstract: Methods of manufacturing a semiconductor device include forming a gate electrode on a semiconductor substrate, forming spacers on side walls of the gate electrode, and doping impurities into the semiconductor substrate on both sides of the spacers to form highly doped impurity regions. The spacers are selectively etched to expose portions of the semiconductor substrate, and more lightly doped impurity regions are formed in the semiconductor substrate between the highly doped impurity regions and the gate electrode.Type: GrantFiled: November 12, 2010Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hwan Kim, Yamada Satoru
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Publication number: 20110254105Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.Type: ApplicationFiled: April 16, 2010Publication date: October 20, 2011Applicant: Taiwan Semiconductor Manufacturing Company. Ltd.Inventors: Chun-Fai Cheng, Ka-Hing Fung, Han-Ting Tsai, Ming-Huan Tsai, Wei-Han Fan, Hsueh-Chang Sung, Haiting Wang, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Publication number: 20110254015Abstract: A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode.Type: ApplicationFiled: April 15, 2010Publication date: October 20, 2011Applicant: International Business Machines CorporationInventors: Bruce B. Doris, Johnathan E. Faltermeier, Lahir M. Shaik Adam, Balasubramanian S. Pranatharthi Haran
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Patent number: 8035141Abstract: A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon.Type: GrantFiled: October 28, 2009Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Jinghong Li, Viorel Ontalus, Zhengmao Zhu
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Publication number: 20110241128Abstract: A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Applicants: TOKYO ELECTRON LIMITED, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David L. O'Meara, Anthony Dip, Aelan Mosden, Pao-Hwa Chou, Richard A. Conti
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Publication number: 20110241129Abstract: The present invention provides a transistor, a semiconductor device and a transistor fabrication process that thoroughly ameliorate electric fields in a transistor element. Namely, the transistor includes a semiconductor substrate, incline portions, a gate electrode, side walls, and a source and a drain. The semiconductor substrate includes a protrusion portion at a surface thereof. The incline portions constitute side surface portions of the protrusion portion and are inclined from the bottom to the top of the protrusion portion. The gate electrode is formed on the top of the protrusion portion, with a gate insulation film interposed therebelow. The side walls are formed on the top of the protrusion portion at two side surfaces of the gate electrode and the gate insulation film. The source and the drain each include a low density region and a high-density region.Type: ApplicationFiled: March 28, 2011Publication date: October 6, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Michihiro Ebe
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Publication number: 20110233688Abstract: A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate.Type: ApplicationFiled: March 25, 2010Publication date: September 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhibin Ren, Kevin K. Chan, Chung-Hsun Lin, Xinhui Wang