Avalanche Junction Patents (Class 257/438)
  • Patent number: 7372495
    Abstract: An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel circuit from breaking down when the voltage in the pixel circuit reaches the operating voltage applied to the charge multiplying photoconversion layer in response to the image sensor being exposed to a strong light. The protection circuit causes additional voltage entering the pixel circuit from the charge multiplying photoconversion layer over a predetermined threshold voltage level to be dissipated from the storage node and any downstream components.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: May 13, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Isao Takayanagi, Junichi Nakamura
  • Patent number: 7348607
    Abstract: The present invention includes a planar avalanche photodiode having a first n-type semiconductor layer defining a planar contact area, and a second n-type semiconductor layer having a p-type diffusion region. Further features of the structure includes an n-type semiconductor multiplication layer, an n-type semiconductor absorption layer, and a p-type contact layer. Further embodiments include a planar avalanche photodiode having a first n-type semiconductor layer defining a planar contact area, an n-type semiconductor multiplication layer, an n-type semiconductor absorption layer and a p-type semiconductor layer electrically coupled to a p-type contact layer.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: March 25, 2008
    Assignee: Picometrix, LLC
    Inventors: Cheng C. Ko, Barry Levine
  • Patent number: 7348608
    Abstract: A planar avalanche photodiode includes a small localized contact layer on the top of the device produced by either a diffusion or etching process and a semiconductor layer defining a lower contact area. A semiconductor multiplication layer is positioned between the two contact areas and a semiconductor absorption layer is positioned between the multiplication layer and the upper contact layer. The photodiode has a low capacitance and a low field near the edges of the semiconductor multiplication and absorption layers.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: March 25, 2008
    Assignee: Picometrix, LLC
    Inventors: Cheng C. Ko, Barry Levine
  • Publication number: 20080067620
    Abstract: A photodiode designed to capture incident photons includes a stack of at least three superposed layers of semiconductor materials having a first conductivity type The stack includes: an interaction layer designed to interact with incident photons so as to generate photocarriers, a collection layer to collect the photocarriers; a confinement layer designed to confine the photocarriers in the collection layer. The collection layer has a band gap less than the band gaps of the interaction layer and confinement layer. The photodiode also includes a region which extends transversely relative to the planes of the layers. The region is in contact with the collection layer and confinement layer and has a conductivity type opposite to the first conductivity type so as to form a p-n junction with the stack.
    Type: Application
    Filed: September 12, 2007
    Publication date: March 20, 2008
    Applicant: Commissariat A L'Energie Atomique
    Inventor: Johan ROTHMAN
  • Patent number: 7332785
    Abstract: A dye-sensitized solar cell with high conversion efficiency is provided. The dye-sensitized solar cell according to the present invention has, between an electrode (2) formed on a surface of a transparent substrate (1) and a counter electrode (6), a light-absorbing layer (3) containing light-absorbing particles carrying dye and an electrolyte layer (5), characterized in that the light-absorbing layer (3) containing light-scattering particles (4) different in size from the light-absorbing particles. In such a dye-sensitized solar cell according to the present invention, the energy of light, which passes through a light-absorbing layer in a conventional cell structure, can be strongly absorbed by the dye in the light-absorbing layer of the present invention. This will increase the conversion efficiency and output current of the dye-sensitized solar cell.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: February 19, 2008
    Assignee: Sony Corporation
    Inventor: Takashi Tomita
  • Patent number: 7326970
    Abstract: A metamorphic avalanche photodetector includes a substrate, and an active structure supported on the substrate. The active structure has a metamorphic absorption structure that absorbs light and responsively produces primary charge carriers, and an avalanche multiplication structure that receives the primary charge carriers from the metamorphic absorption structure and responsively produces secondary charge carriers. An output electrical contact is in electrical communication with the active structure to collect at least some of the secondary charge carriers. A buffer layer lies between the substrate and the active structure, between the active structure and the output electrical contact, or between the metamorphic absorption structure and the avalanche multiplication structure. A lattice parameter of the buffer layer varies with position through a thickness of the buffer layer.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: February 5, 2008
    Assignee: The Boeing Company
    Inventors: Geoffrey S. Kinsey, Dmitri D. Krut, Joseph C. Boisvert, Christopher M. Fetzer, Richard R. King
  • Publication number: 20080017883
    Abstract: An avalanche photodetector is disclosed. An apparatus according to aspects of the present invention includes a mesa structure defined in a first type of semiconductor. The first type of semiconductor material includes an absorption region optically coupled to receive and absorb an optical beam. The apparatus also includes a planar region proximate to and separate from the mesa structure and defined in a second type of semiconductor material. The planar region includes a multiplication region including a p doped region adjoining an n doped region to create a high electric field in the multiplication region. The high electric field is to multiply charge carriers photo-generated in response to the absorption of the optical beam received in the mesa structure.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 24, 2008
    Inventors: Gadi Sarid, Yimin Kang, Alexandre Pauchard
  • Publication number: 20070290285
    Abstract: A semiconductor device that contains photodiodes whose sensitivity and storage capacity can be increased, and a solid-state image pickup device formed by arranging the photodiodes in an array and its manufacturing method. A first semiconductor region 11 of a second conductivity type is formed on the principal surface of a semiconductor substrate 10 of a first conductivity type. A pixel separating region 14 of the first conductivity type is formed to penetrate through the first semiconductor region 11 to separate the regions of the adjacent photodiodes PD. A second semiconductor region 15 of the second conductivity type used to drain excess charge is formed in semiconductor substrate 10 at a position away from the junction surface between semiconductor substrate 10 and the first semiconductor region 11 and below the junction surface.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 20, 2007
    Applicant: TEXAS INSTRUMENTS, INCORPORATED
    Inventors: Hidetoshi Shimada, Karuya Mori
  • Patent number: 7271376
    Abstract: A photodetector circuit incorporates an avalanche photodiode structure having a contact layer (14) forming an ohmic contact over an annular region (18) with the annular guard ring (8). In the fabrication process, the starting substrate can either be the handle wafer of a p? silicon-on-insulator wafer, or a p-Si substrate with an insulating SiO2 layer (4). A window (6) is produced in the insulating layer (4) by conventional photolithographic and etching. A n+ guard ring (8) is created by diffusing donor impurities into the substrate, and a thinner insulating SiO2 layer (22) is thermally grown so as to cover the exposed surface of the substrate within the window (6). P-type dopant is then implanted through the thin oxide layer to increase the doping level near the surface of the substrate. Subsequently a second window (24) is made in the insulating layer (22), and the layer (12) is then epitaxially grown selectively on the area of the substrate exposed by the window (24) in the insulating layer (22).
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: September 18, 2007
    Assignee: QinetiQ Limited
    Inventors: John L Glasper, David J Robbins, Weng Y Leong
  • Patent number: 7268339
    Abstract: A method is provided for forming a semiconductor-detection device that provides internal gain. The method includes forming a plurality of bottom trenches in a bottom surface of an n-doped semiconductor wafer; and forming a second plurality of top trenches in a top surface of the semiconductor wafer. The bottom surface and the top surface are opposed surfaces. Each of the bottom trenches is substantially parallel to and substantially juxtaposed to an associated one of the top trenches. The method further includes doping the semiconductor wafer with at least one p-type dopant to form a p-region that defines at least one n-well within the p-region, wherein a p-n junction is formed substantially at an interface of the n-well and the p-region; and removing a portion of the bottom surface to form a remaining-bottom surface, wherein a portion of the n-well forms a portion of the remaining-bottom surface.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: September 11, 2007
    Assignee: Radiation Monitoring Devices, Inc.
    Inventors: Richard Farrell, Kofi Vanderpuye
  • Patent number: 7259408
    Abstract: An objective is to provide an avalanche photodiode that is excellent in device characteristics such as reliability. An avalanche photodiode is provided, which includes a substrate 1 formed with a light receiving region 3 on a multiplication layer 119, and formed with layers of differing semiconductor type with the multiplication layer 119 intervening, a ring-shaped groove 7 formed on the end face of the substrate 1 on its light-receiving-region side, in such a way that the groove surrounds the light receiving region 3, and one or more steps 5 provided on a side wall of the ring-shaped groove 7, in a range of from ¼ to ¾ of the depth of the groove.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: August 21, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Eiji Yagyu, Nobuyuki Tomita, Eitaro Ishimura, Masaharu Nakaji
  • Patent number: 7233051
    Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: June 19, 2007
    Assignee: Intel Corporation
    Inventors: Michael T. Morse, Olufemi I. Dosunmu, Ansheng Liu, Mario J. Paniccia
  • Patent number: 7216423
    Abstract: The present invention relates to a method for forming an active area or flat panel in an X-ray detector device. The method comprises forming at least one flat form factor panel in a first size on a substrate of a second size and extending at least one contact of the at least one flat form factor panel. The method further comprises trimming the substrate to the first size forming the at least one flat panel.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: May 15, 2007
    Assignee: General Electric Company
    Inventors: Jeffrey A. Kautzer, Richard Aufrichtig, John French
  • Patent number: 7199437
    Abstract: A method for embedding optical band gap (OBG) devices in a ceramic substrate (100). The method includes the step (320) of pre-forming an OBG structure (105). The OBG structure can be a micro optical electromechanical systems (MOEMS) device. Further, the OBG structure can be preformed from indium phosphide and/or indium gallium arsenide. The method also includes the step (325) of coating the OBG structure with a surface binding material (230). The surface binding material can be comprised of calcium and hexane. The ratio of the calcium to hexane can be from about 1% to 2%. At a next step (330), the OBG structure can be inserted into the ceramic substrate. A pre-fire step (335) and a sintering step (340) then can be performed on the substrate.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: April 3, 2007
    Assignee: Harris Corporation
    Inventor: Randy T. Pike
  • Patent number: 7196390
    Abstract: A method for encoding information that is encoded in spatial variations of the intensity of light (24) of a first wave-length into light of a second wavelength, the method comprising: generating a first density distribution of electrons homologous with the spatial variations in intensity of the first wavelength light; generating a second additional electron density homologous with the first electron density distribution; trapping electrons from the first and second electron density distributions in a trapping region (34) to generate an electric field homologous with the density distributions in a material (36) that modulates a characteristic of light (22) that passes therethrough responsive to an electric field (46) therein; and transmitting the second wavelength light (22) through the modulating material (36) thereby modulating the second wavelength light in response to the electric field and encoding it with the information.
    Type: Grant
    Filed: June 26, 1999
    Date of Patent: March 27, 2007
    Assignee: 3DV Systems Ltd.
    Inventors: Amnon Manassen, Giora Yahav
  • Patent number: 7122453
    Abstract: The invention includes a method of patterning radiation. The radiation is simultaneously passed through a structure and through a subresolution assist feature that is transmissive of at least a portion of the radiation. The subresolution assist feature alters a pattern of radiation intensity defined by the structure relative to a pattern of radiation intensity that would be defined in the absence of the subresolution assist feature. The invention further includes methods of forming radiation-patterning tools, and the radiation-patterning tools themselves.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: October 17, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Bill Baggenstoss
  • Patent number: 7098519
    Abstract: The invention relates to an avalanche radiation detector comprising a semiconductor substrate (HK) with a front side (VS) and a back side (RS), an avalanche region (AB) which is arranged in the semiconductor substrate (HK) on the front side (VS) of the semiconductor substrate (HK) and a control electrode (R) for adjusting the electric field strength in the avalanche region (AB). It is proposed that the control electrode (R) is also arranged on the front side of the semiconductor substrate (HK).
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: August 29, 2006
    Assignee: Max-Planck-Gesellschaft zur Forderung der Wissenchafter E.V.
    Inventors: Gerhard Lutz, Rainer H. Richter, Lothar Struder
  • Patent number: 7075165
    Abstract: A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: July 11, 2006
    Assignee: Applied Material, Inc.
    Inventors: Francisco A. Leon, Lawrence C. West, Yuichi Wada, Gregory L. Wojcik, Stephen Moffatt
  • Patent number: 7061065
    Abstract: The present invention discloses an LED (light emitting diode), which primarily includes a transparent window, such as a glass substrate, an LED epitaxial layer including at least an active layer, and a transparent conductive film formed between the transparent window and the LED epitaxial layer. The transparent conductive film can be oxides, nitrides or fluorides of metals, for example, ITO, InO, SnO, ZnO, etc. By involving the transparent conductive film, current spreading is improved and resistance is reduced because of larger cross section areas provided, particularly compared with the conventional spin on glass or polymer adhesives. Additionally, light-emitting efficiency can be improved since the conventional opaque substrate, such as a GaAs substrate on which the active layer is grown can be etched away after the transparent window and the active layer are combined with the transparent conductive film.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: June 13, 2006
    Assignee: National Chung-Hsing University
    Inventors: Ray-Hua Horng, Tung-Hsing Wu, Shao-Hua Huang, Chi-Ying Chiu
  • Patent number: 7057253
    Abstract: A magnetic memory cell and method of manufacturing thereof, wherein the angle between the shape anisotropy axis and the intrinsic anisotropy axis of the magnetic material layer is optimized to minimize fluctuations in the switching field. The angle between shape anisotropy axis and intrinsic anisotropy axis is preferably between 45 and less than 90 degrees. Magnetic layers may be used having increased thickness, resulting in increased activation energy. Magnetic memory cells may be manufactured that are more stable for long term storage and have improved write margins.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: June 6, 2006
    Assignee: Infineon Technologies AG
    Inventor: Daniel Braun
  • Patent number: 7045761
    Abstract: The present application is directed to a self-pixelating focal plane array and includes a photodetection portion having a body defining a self-pixelating active detection region, and a readout device in electrical communication with the photodetection portion and configured to capture electrical charges from the photodetection portion. During use, the photodetection portion is configured to operate in Geiger mode. As such, the application of one or more electrical fields to the photodetection portion results in the photodetection portion operating in a self-pixelating manner. The readout device may be used to capture the electrical charges and signals generated by the photodetection portion due to the incidence of one or more photons on the photodetection portion.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: May 16, 2006
    Assignee: The Boeing Company
    Inventor: Jeffrey H. Hunt
  • Patent number: 7038251
    Abstract: A semiconductor device has a structure reducing resistances to a high frequency current. The semiconductor device includes a semi-insulating substrate, a first n-type layer made of a compound semiconductor, and a first p-type layer made of a compound semiconductor in which a signal current flows in a lateral direction, parallel to the semi-insulating substrate. The first p-type layer is sandwiched between the semi-insulating substrate and the first n-type layer. A second n type layer made of a compound semiconductor is between the semi-insulating substrate and the first p type layer. An alternating current component of the signal current flows through the second n type layer.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: May 2, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Eitaro Ishimura, Masaharu Nakaji, Eiji Yagyu, Nobuyuki Tomita
  • Patent number: 7005699
    Abstract: A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, intergate dielectric layer, tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. The second stacked gate structure has a select gate dielectric layer, a select gate and a second cap layer. The control gate is between each of the first stacked gate structures, and between each of the second stacked gate structures and adjacent first stacked gate structure. The floating gate is between the control gate and substrate. The inter-gate dielectric layer is between the control and floating gates. The tunnel oxide is between the floating gate and substrate. The doping regions are under the first stacked gate structure, and the source/drain regions are in the exposed substrate.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: February 28, 2006
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Shih-Chang Chen, Cheng-Yuan Hsu, Chih-Wei Hung
  • Patent number: 7002156
    Abstract: A detection system for detecting gamma rays including a scintillator crystal for receiving at least one gamma ray and generating at least one ultraviolet ray and an avalanche photodiode for detecting the ultraviolet ray. The avalanche photodiode includes: a substrate having a first dopant; a first layer having a second dopant, positioned on top of the substrate; a passivation layer for providing electrical passivation on a surface of the avalanche photodiode; a phosphorous silicate glass layer for limiting mobile ion transport, positioned above of the first layer; and a pair of metal electrodes for providing an ohmic contact wherein a first electrode is positioned below the substrate and a second electrode is positioned above the first layer. The avalanche photodiode comprises a first sidewall and a second sidewall forming a sloped mesa shape.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: February 21, 2006
    Assignee: General Electric Company
    Inventors: Peter M. Sandvik, Dale M. Brown, Stephen D. Arthur, Kevin S. Matocha, James W. Kretchmer
  • Patent number: 6995444
    Abstract: Photodetector device comprising a semiconductor substrate (1) of a first type of conductivity connected to a first electrode (2). Said substrate comprises an active area (4) made up of different semiconductor regions of a second type of conductivity (8, 9, 10) insulated from each other and connected to respective second electrodes (13, 14, 15) so that each of them can be connected separately from the others to an appropriate bias voltage. By regulating the bias voltages applied to these regions the function of optic diaphragm of the device can be controlled. The device works without needing any form of optical insulation between the different regions of the active area and always uses the same single output electrode for the signal in all the different situations of diaphragm adjustment.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: February 7, 2006
    Assignee: Carl Zeiss Jena GmbH
    Inventors: Sergio Cova, Franco Zappa, Massimo Ghioni, Robert Grub, Eberhard Derndinger, Thomas Hartmann
  • Patent number: 6963089
    Abstract: An avalanche photo-detector (APD) is disclosed, which can reduce device capacitance, operating voltage, carrier transport time and dark current as well as increasing response speed and output power. Thus, an avalanche photo-detector (APD) with high saturation power, high gain-bandwidth product, low noise, fast response, low dark current is achieved. The APD includes an absorption layer with graded doping for converting an incident light into carriers, an undoped multiplication layer for multiplying current by means of receiving carriers, a doped field buffer layer sandwiched between the absorption layer and the multiplication layer for concentrating an electric field in the multiplication layer when a bias voltage is applied, and an undoped drift layer sandwiched between the absorption layer and the field buffer layer for capacitance reduction.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: November 8, 2005
    Assignee: Industrial Technology Research Institute
    Inventors: Jin-Wei Shi, Chee-Wee Liu
  • Patent number: 6956251
    Abstract: A blue-ultraviolet on-p-GaAs substrate pin Zn1-xMgxSySe1-y photodiode with high quantum efficiency, small dark current, high reliability and a long lifetime. The ZnMgSSe photodiode has a metallic p-electrode, a p-GaAs single crystal substrate, a p-(ZnSe/ZnTe)m superlattice (m: integer number of sets of thin films), an optionally formed p-ZnSe buffer layer, a p-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, an n-Zn1-xMgxSySe1-y layer, an n-electrode and an optionally provided antireflection film. Incidence light arrives at the i-layer without passing ZnTe layers. Since the incidence light is not absorbed by ZnTe layers, high quantum efficiency and high sensitivity are obtained.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: October 18, 2005
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koshi Ando, Tomoki Abe, Takao Nakamura
  • Patent number: 6956273
    Abstract: In a photoelectric conversion element which is formed by alternately stacking a region of a first conductivity type and a region of a second conductivity type as a conductivity type opposite to the first conductivity type to form a multi-layered structure, in which junction surfaces between the neighboring regions of the first and second conductivity types are formed to have depths suited to photoelectrically convert light in a plurality of different wavelength ranges, and which outputs signals for respective wavelength ranges, a region of a conductivity type opposite to the conductivity type of a surface-side region of the junction surface closest to a surface is formed in the surface of the surface-side region. Thus, highly color-separable signals which suffer less color mixture upon reading out signals from a plurality of photodiode layers is read out.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: October 18, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toru Koizumi
  • Patent number: 6936868
    Abstract: A sequential mesa type avalanche photodiode (APD) includes a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: August 30, 2005
    Assignee: Anritsu Corporation
    Inventors: Jun Hiraoka, Kazuo Mizuno, Yuichi Sasaki
  • Patent number: 6936806
    Abstract: Disclosed is a photoelectric conversion device having a multiplying function and an image sensing device using the same. The photoelectric conversion device essentially comprises three layered structure: a carrier generation/multiplication layer composed of amorphous silicon to have both the function of absorbing light and generating carriers through optical excitation and the function of multiplying the generated carriers; an electron injection inhibiting layer composed of an amorphous silicon carbide of the p-type conductivity to inhibit injection of electrons into the carrier generation/multiplication layer; and a hole injection inhibiting layer composed of an amorphous silicon nitride of the n-type conductivity to inhibit injection of holes into the carrier generation/multiplication layer. The said carrier generation/multiplication layer is provided between said electron injection inhibiting layer and said hole injection inhibiting layer.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: August 30, 2005
    Assignee: Minolta Co., Ltd.
    Inventors: Ken Kitamura, Yoshinori Hatanaka
  • Patent number: 6919609
    Abstract: An opto-electronic device configured as a photodetector has a capacitor and/or resistor monolithically formed on a surface of the photodetector. The capacitor capacitively couples the AC ground of the photodetector to the bias terminal of the photodetector. The on chip capacitor design eliminates the inductance of external circuit traces between the power supply and an external capacitor. The resistor forces the AC return current of the photodetector through the AC ground in preference to the typical (DC bias terminal) path. Combinations of capacitors and resistors are particularly effective in reducing crosstalk among adjacent detectors in arrays.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: July 19, 2005
    Assignee: Optical Communication Products, Inc.
    Inventors: John Hart Lindemann, Michael Thomas Dudek, David Galt
  • Patent number: 6900512
    Abstract: This invention relates to a light-receiving module in which transmission impedance of lead terminals are matched by simple method. The module has a semiconductor light-receiving device, such as a photo diode, a plurality of lead terminals for transmitting an electrical signal converted by the semiconductor device, and a metal base with a plurality of through holes, the lead terminals passes therethrough. The diameter of the lead terminal for signal transmission is smaller as compared with that of other lead terminal and the diameter of the through holes is adjusted and filled by a sealant glass with a dielectric constant so as to match the impedance thereof.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: May 31, 2005
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kenichiro Kohmoto, Takeshi Sekiguchi, Motoyoshi Tanaka, Makoto Ito
  • Patent number: 6894324
    Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: May 17, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Dou Ker, Kei-Kang Hung, Tien-Hao Tang
  • Patent number: 6894322
    Abstract: A highly reflecting back illuminated diode structure allows light that has not been absorbed by a semiconductor absorbing region to be back reflected for at least a second pass into the absorbing region. The diode structure in a preferred embodiment provides a highly reflecting layer of gold to be supported in part by a conducting alloyed electrode ring contact and in part by a passivation layer of SixNy. Conveniently this structure provides a window within the contact which allows light to pass between the absorbing region and the reflecting layer of gold.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: May 17, 2005
    Assignee: JDS Uniphase Corporation
    Inventors: Steven Kwan, Rafael Ben-Michael, Mark Itzler
  • Patent number: 6885040
    Abstract: A wavelength-selective photo detector device includes a transparent upper electrode including a capacitor, a first semiconductor layer disposed under the upper electrode, an optical absorption layer disposed under the first semiconductor layer for absorbing light to form pairs of electrons and holes, an amplification layer disposed under the optical absorption layer for generating secondary electrons, a second semiconductor layer disposed under the amplification layer, and a lower electrode disposed under the second semiconductor layer and including an inductance coupled in parallel with an external resistance. The photo detector improves the S/N ratio and filters only light having a particular wavelength band.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: April 26, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-young Kim, Byoung-lyong Choi, Eun-kyung Lee
  • Patent number: 6885039
    Abstract: There is provided a semiconductor photodetector which comprises (i) an InP substrate(1), (ii) an optical waveguide(5) having an N-type semiconductor layer(32) formed on the InP substrate(1), an optical waveguide core layer(3) formed on a partial area of the N-type semiconductor layer(32), and an upper cladding layer(4) formed on the optical waveguide core layer(3), and (iii) an avalanche photodiode(17) constructed by forming a photo absorbing layer(33), a heterobarrier relaxing layer(34), an underlying layer(14a) of a N-type field dropping layer(35), an overlying layer(14b) of the N-type field dropping layer(35), a carrier multiplying layer(36), and a P-type semiconductor layer(37) in sequence on another area of the N-type semiconductor layer(32), and coupled to the optical waveguide(5), wherein a side surface of the underlying layer(14a) of the N-type field dropping layer(35) comes into contact with a side surface of the optical waveguide core layer(3), and a part of the overlying layer(14b) of the N-type fi
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: April 26, 2005
    Assignee: Fujitsu Limited
    Inventor: Haruhiko Kuwatsuka
  • Patent number: 6870239
    Abstract: An avalanche photodiode comprises, in various implementations, a p-doped absorption region fabricated from a first material and joined along a hetero-junction with one side of an intrinsic charge-carrier multiplication region fabricated from a second material. Situated on an opposite side of the multiplication region is an n-doped diode cathode. Under reverse bias, the p-doped and n-doped regions assume, respectively, a negative charge and a positive charge and an electric field is present in the multiplication region. The first and second materials are selected to one of (i) minimize and (ii) render non-existent any conduction-band-dependent potential barrier opposing the diffusion of electrons from the absorption region into the multiplication region.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: March 22, 2005
    Assignee: Solid State Scientific Corporation
    Inventor: William Clark
  • Patent number: 6861681
    Abstract: A blue-ultraviolet on-p-GaAs substrate pin Zn1-xMgxSySe1-y photodiode with high quantum efficiency, small dark current, high reliability and a long lifetime. The ZnMgSSe photodiode has a metallic p-electrode, a p-GaAs single crystal substrate, a p-(ZnSe/ZnTe)m superlattice (m: integer number of sets of thin films), an optionally formed p-ZnSe buffer layer, a p-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, an n-Zn1-xMgxSySe1-y layer, an n-electrode and an optionally provided antireflection film. Incidence light arrives at the i-layer without passing ZnTe layers. Since the incidence light is not absorbed by ZnTe layers, high quantum efficiency and high sensitivity are obtained.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: March 1, 2005
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koshi Ando, Tomoki Abe, Takao Nakamura
  • Patent number: 6858912
    Abstract: A photodetector circuit incorporates an avalanche photodiode (APD) 300 produced by epitaxy on a CMOS substrate 302 with implanted n-well 304 and p-well 306. The n-well 304 has an implanted p+ guard ring 310 delimiting the APD 300. Within the guard ring 310 is an implanted n+ APD layer 312 upon which is deposited an epitaxial p+ APD layer 314, these layers forming the APD 300. The APD may be incorporated in an amplifier circuit 50 providing feedback to maintain constant bias voltage, and may include an SiGe absorption region to provide extended long wavelength response or lower avalanche voltage. Non-avalanche photodiodes may also be used.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: February 22, 2005
    Assignee: QinetiQ Limited
    Inventors: Gillian F Marshall, David J Robbins, Wang Y Leong, Steven W Birch
  • Patent number: 6838741
    Abstract: An aspect of the present invention is directed to an avalanche photodiode (APD) device for use in oil well drilling applications in harsh, down-hole environments where shock levels are near 250 gravitational acceleration (G) and/or temperatures approach or exceed 150° C. Another aspect of the present invention is directed to an APD device fabricated using SiC materials. Another aspect of the present invention is directed to an APD device fabricated using GaN materials.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: January 4, 2005
    Assignee: General Electtric Company
    Inventors: Peter M. Sandvik, Dale M. Brown, Stephen D. Arthur, Kevin S. Matocha, James W. Kretchmer
  • Publication number: 20040256688
    Abstract: A magnetic memory cell and method of manufacturing thereof, wherein the angle between the shape anisotropy axis and the intrinsic anisotropy axis of the magnetic material layer is optimized to minimize fluctuations in the switching field. The angle between shape anisotropy axis and intrinsic anisotropy axis is preferably between 45 and less than 90 degrees. Magnetic layers may be used having increased thickness, resulting in increased activation energy. Magnetic memory cells may be manufactured that are more stable for long term storage and have improved write margins.
    Type: Application
    Filed: June 19, 2003
    Publication date: December 23, 2004
    Inventor: Daniel Braun
  • Publication number: 20040256689
    Abstract: A method of forming a MEMS device produces a device layer wafer having a pre-formed conductive pathway before coupling it with a handle wafer. To that end, the method produces the noted device layer wafer by 1) providing a material layer, 2) coupling a conductor to the material layer, and 3) forming at least two conductive paths through at least a portion of the material layer to the conductor. The method then provides the noted handle wafer, and couples the device layer wafer to the handle wafer. The wafers are coupled so that the conductor is contained between the material layer and the handle wafer.
    Type: Application
    Filed: June 23, 2003
    Publication date: December 23, 2004
    Inventors: Bruce K. Wachtmann, Michael W. Judy
  • Publication number: 20040245592
    Abstract: A solid state microchannel plate is disclosed comprising a multiplicity of photodetector elements, each using limited gain from a small Geiger mode avalanche and summing the contributions thereof. An array of such multiplicities operates as a pixelated linear or area photodetector. In the preferred embodiment, a multiplicity of passively quenched photodetector elements connect to a common anode, and each photodetector element is passively quenched by its own current-limiting resistor in series with its cathode.
    Type: Application
    Filed: May 1, 2004
    Publication date: December 9, 2004
    Applicant: Yale University
    Inventors: Eric S. Harmon, David B. Salzman
  • Patent number: 6826637
    Abstract: An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the Nth layer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding one of the buffering devices for the Nth layer, respectively. (b) A buffering device for the N+1th layer is implemented at a location close to the middle place between two buffering devices for the Nth layer, and each one of the buffering devices for the Nth layer is electrically connected to the corresponding one of the buffering devices for the N+1th layer, respectively. Then, the number of the buffering devices for the N+1th layer is judged whether or not to be 1.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: November 30, 2004
    Assignee: Via Technologies, Inc.
    Inventors: Yung-Chung Chang, You-Ming Chiu
  • Publication number: 20040217435
    Abstract: A mask capable of alignment by the TTR system and complementary division and having a high strength, a method of production of the same, and a method of production of a semiconductor device having a high pattern accuracy are provided. A stencil mask having stripe-shaped grid lines 4 formed by etching a silicon wafer in four sub-regions A to D on a membrane, having the stripes arranged point symmetrically about a center of the membrane, and having all of the grid lines connected to other grid lines or the silicon wafer around the membrane (support frame), a method of production of the same, and a method of production of a semiconductor device using the mask.
    Type: Application
    Filed: August 4, 2003
    Publication date: November 4, 2004
    Inventors: Shinki Omori, Shigeru Moriya
  • Patent number: 6812539
    Abstract: An improved imager pixel arrangement having a light shield over the pixel circuitry, but below the conductive interconnect layers of the pixel. The light shield can be a thin film of opaque (or nearly-opaque) material with openings for contacts to the underlying circuitry. An aperture in the light shield exposes the active region of the pixel's photoconversion device.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: November 2, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 6800914
    Abstract: Reducing a dark current in a semiconductor photodetector provided with a second mesa including an regrown layer around a first mesa. An n-type buffer layer, a n-type multiplication layer, a p-type field control layer, a p-type absorption layer, a cap layer made of p-type InAlAs crystal, and a p-type contact layer 107 are made to grow on a main surface of a n-type substrate. Thereafter the p-type contact layer, the p-type cap layer, the p-type absorption layer and the p-type field control layer are patterned to form a first mesa. Next, after making a p-type regrown layer selectively grow around the first mesa or by forming a groove in the regrow layer located in a vicinity of the p-type cap type during a step of the selective growth, the p-type cap layer containing Al and the regrow layer are separated owing to the groove such that no current path is formed between both layers.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: October 5, 2004
    Assignee: Opnext Japan, Inc.
    Inventors: Kazuhiro Ito, Shigehisa Tanaka, Sumiko Fujisaki, Yasunobu Matsuoka, Takashi Toyonaka
  • Patent number: 6791124
    Abstract: A sequential mesa type avalanche photodiode (APD) comprises a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: September 14, 2004
    Assignee: Anritsu Corporation
    Inventors: Jun Hiraoka, Kazuo Mizuno, Yuichi Sasaki
  • Publication number: 20040169246
    Abstract: A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.
    Type: Application
    Filed: June 24, 2002
    Publication date: September 2, 2004
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventor: Chia-Ta Hsieh
  • Patent number: 6774448
    Abstract: An opto-electronic device configured as a photodetector has a capacitor and/or resistor monolithically formed on a surface of the photodetector. The capacitor capacitively couples the AC ground of the photodetector to the bias terminal of the photodetector. The on chip capacitor design eliminates the inductance of external circuit traces between the power supply and an external capacitor. The resistor forces the AC return current of the photodetector through the AC ground in preference to the typical (DC bias terminal) path. Combinations of capacitors and resistors are particularly effective in reducing crosstalk among adjacent detectors in arrays.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: August 10, 2004
    Assignee: Optical Communication Products, Inc.
    Inventors: John Hart Lindemann, Michael Thomas Dudek, David Galt