Avalanche Junction Patents (Class 257/438)
  • Publication number: 20040119128
    Abstract: A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfOx and a ZrOx.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Inventors: Lawrence A. Clevenger, Louis L. Hsu, Carl J. Radens, Joseph F. Shepard
  • Patent number: 6747296
    Abstract: An avalanche photodiode charge-carrier multiplication region comprises a first region fabricated from a first material having a first impact ionization threshold and a second region joined to the first region at an interface and fabricated from a second material having a second impact ionization threshold lower than the first impact ionization threshold. The first region includes, in the presence of an applied reverse-bias, first and second oppositely charged layers to establish an elevated, localized electric field within a sub-region of the first region. The first and second charged layers are arranged such that preferred charge carriers are accelerated by the localized electric field just prior to being injected into the second material where they impact ionize at predetermined statistical rate.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: June 8, 2004
    Assignee: Solid State Scientific Corporation
    Inventor: William Clark
  • Publication number: 20040089876
    Abstract: There is provided a semiconductor photodetector which comprises (i)an InP substrate(1), (ii)an optical waveguide(5) having an N-type semiconductor layer(32) formed on the InP substrate(1), an optical waveguide core layer(3) formed on a partial area of the N-type semiconductor layer(32), and an upper cladding layer(4) formed on the optical waveguide core layer(3), and (iii)an avalanche photodiode(17) constructed by forming a photo absorbing layer(33), a heterobarrier relaxing layer(34), an underlying layer(14a) of a N-type field dropping layer(35), an overlying layer(14b) of the N-type field dropping layer(35), a carrier multiplying layer(36), and a P-type semiconductor layer(37) in sequence on another area of the N-type semiconductor layer(32), and coupled to the optical waveguide(5), wherein a side surface of the underlying layer(14a) of the N-type field dropping layer(35) comes into contact with a side surface of the optical waveguide core layer(3), and a part of the overlying layer(14b) of the N-type field
    Type: Application
    Filed: October 29, 2003
    Publication date: May 13, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Haruhiko Kuwatsuka
  • Patent number: 6730979
    Abstract: A recessed p-type region cap layer avalanche photodiode (12) is provided. The photodiode (12) includes a semiconductor substrate (30) and a semiconductor stack (32), which is electrically coupled to the substrate (30). A cap layer (34) is electrically coupled to the stack (32) and includes a recessed p-type region (36). The recessed p-type region (36) forms a p-n junction (38) with the stack (32). A method of forming the photodiode (12) is also provided. The method includes forming the substrate (30), the stack (32), and the cap layer (34). The cap layer (34) is selectively etched to expose the stack (32) and form a cap layer opening (42). Dopant is diffused through the cap layer opening (42) into the stack (32) to form the p-n junction (38).
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: May 4, 2004
    Assignee: The Boeing Company
    Inventor: Joseph C. Boisvert
  • Patent number: 6724018
    Abstract: A blue-violet-near-ultraviolet pin-photodiode with small dark current, high reliability and long lifetime. The pin-photodiode has a metallic n-electrode, a n-ZnSe single crystal substrate, an optionally added n-ZnSe buffer layer, an n-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, a p-Zn1-xMgxSySe1-y layer, a p-(ZnTe/ZnSe)m SLE, a p-ZnTe contact layer, an optionally provided antireflection film and a metallic p-electrode. A blue-violet-near-ultraviolet avalanche photodiode with small dark current, high reliability and long lifetime. The avalanche photodiode has a metallic n-electrode, a n-ZnSe single crystal substrate, an optionally added n-ZnSe buffer layer, an n-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, a p-Zn1-xMgxSySe1-y layer, a p-(ZnTe/ZnSe)m SLE, a p-ZnTe contact layer, an optionally provided antireflection film and a metallic p-electrode. Upper sides of the layered structure are etched into a mesa-shape and coated with insulating films.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: April 20, 2004
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koshi Ando, Takao Nakamura
  • Patent number: 6720588
    Abstract: An improved APD structure and an improved manner of operating APD's particularly beneficial for a single photon detection applications are provided. An APD is provided having an absorption region, a control region, and a multiplication region, wherein the multiplication region has a k value of approximately 1. In one example the multiplication region comprises a doped InP layer. The field control layer is designed so as to produce a reduction of electric field that is equal to the multiplication region's breakdown electric field, plus or minus 5V/&mgr;m. The method comprises applying a potential across the APD so as to induce an electric field across the multiplication region that exceeds the breakdown field; while having the control region shield the absorption region to prevent excessive noise.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: April 13, 2004
    Assignee: Optonics, Inc.
    Inventor: James S. Vickers
  • Patent number: 6713768
    Abstract: A junction-side illuminated detector array of pixelated detectors is constructed on a silicon wafer. A junction contact on the front-side may cover the whole detector array, and may be used as an entrance window for light, x-ray, gamma ray and/or other particles. The back-side has an array of individual ohmic contact pixels. Each of the ohmic contact pixels on the back-side may be surrounded by a grid or a ring of junction separation implants. Effective pixel size may be changed by separately biasing different sections of the grid. A scintillator may be coupled directly to the entrance window while readout electronics may be coupled directly to the ohmic contact pixels. The detector array may be used as a radiation hardened detector for high-energy physics research or as avalanche imaging arrays.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: March 30, 2004
    Assignee: Photon Imaging, Inc.
    Inventors: Jan S. Iwanczyk, Bradley E. Patt, Carolyn Tull
  • Patent number: 6707075
    Abstract: A method of forming an avalanche trench optical detector device on a semiconductor substrate, comprising forming a first set and a second set of trenches in the substrate, wherein trenches of the first set are alternately disposed with respect to trenches of the second set, filling the trenches with a doped sacrificial material, and annealing the device to form a multiplication region in the substrate. The method comprises etching the doped sacrificial material from the first set of trenches, filling the first set of trenches with a doped material of a first conductivity, etching the doped sacrificial material from a second set of trenches, and filling the second set of trenches with a doped material of a second conductivity. The method further comprises providing separate wiring connections to the first set of trenches and the second set of trenches.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: March 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Dennis L. Rogers, Min Yang
  • Publication number: 20040041393
    Abstract: A solder ball pad for mounting and connecting of electronic devices and, more particularly, apparatus and methods providing an improved solder ball pad structure on a substrate, such as a printed circuit board (“PCB”) or a semiconductor die, while enabling better use of the spaces between adjacent solder ball pads and at the same time providing increased surface area for bonding to a solder ball. Substrates, electronic device assemblies and systems incorporating the invention are also disclosed.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 4, 2004
    Inventor: Teck Kheng Lee
  • Patent number: 6635908
    Abstract: The object of disclosing the novel art consists in providing a highly reliable mesa-structured avalanche photo-diode using a novel structure capable of keeping the dark current low, and a fabrication method thereof. The avalanche photo-diode for achieving the object has an absorption layer for absorbing light to generate a carrier, a multiplication layer for multiplying the generated carrier, and a field control layer inserted between the absorption layer and the multiplication layer. Moreover, a first mesa including at least part of the multiplication layer and part of the field control layer is formed over a substrate, a second mesa including another part of the field control layer and the absorption layer is formed over the first mesa, the area of the top surface of the first mesa is greater than that of the bottom surface of the second mesa, and a semiconductor layer is formed over the part of the first mesa top surface not covered by the second mesa and the side surface of the second mesa.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: October 21, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Shigehisa Tanaka, Yasunobu Matsuoka, Kazuhiro Ito, Tomohiro Ohno, Sumiko Fujisaki, Akira Taike, Tsukuru Ohtoshi, Shinji Tsuji
  • Publication number: 20030178636
    Abstract: A highly reflecting back illuminated diode structure allows light that has not been absorbed by a semiconductor absorbing region to be back reflected for at least a second pass into the absorbing region. The diode structure in a preferred embodiment provides a highly reflecting layer of gold to be supported in part by a conducting alloyed electrode ring contact and in part by a passivation layer of SixNy. Conveniently this structure provides a window within the contact which allows light to pass between the absorbing region and the reflecting layer of gold.
    Type: Application
    Filed: February 10, 2003
    Publication date: September 25, 2003
    Applicant: JDS Uniphase Corporation
    Inventors: Steven Kwan, Rafael Ben-Michael, Mark Itzler
  • Patent number: 6614086
    Abstract: There is disclosed a photodetector having two or more avalanche-gain layered structures and multi-terminals. The avalanche photodetector includes an emitter light absorption layer structure located between a collector layer and an emitter layer (top contact layer) stacked on a substrate. The photodetector further comprises multiple avalanche-gain layered structures consisting of a charge layer, a multiplication layer and a contact layer between the light absorption layer and said collector layer.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: September 2, 2003
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Gyung Ock Kim, In Kyu Kim, Kwang Eui Pyun
  • Patent number: 6583482
    Abstract: An avalanche photodetector (APD) is made from composite semiconductor materials. The absorption region of the APD is formed in a n-type InGaAs layer. The multiplication region of the APD is formed in a p-type silicon layer. The two layers are bonded together. The p-type silicon layer may be supported on an n+ type silicon substrate. A p-n junction formed at the interface between the silicon layer and the substrate. Alternatively, the n-type InGaAs layer may be supported on an InP substrate. In this case, a p-n junction is formed by making n-doped surface regions in the p-type silicon superlayer. In either case, the p-n junction is reverse biased for avalanche multiplication of charge carriers. The maximum of the electric field distribution in the APD under reverse bias operating conditions is located at p-n junction. This maximum is at a distance equal to about the thickness of the p-type silicon layer away from the absorption region.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: June 24, 2003
    Inventors: Alexandre Pauchard, Yu-Hwa Lo
  • Publication number: 20030111702
    Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.
    Type: Application
    Filed: September 5, 2002
    Publication date: June 19, 2003
    Inventors: Daniel C. Guterman, Gheorghe Samachisa, Yupin Kawing Fong, Eliyahou Harari
  • Patent number: 6570083
    Abstract: A photovoltaic generator including at least one photovoltaic cell, and a transparent matrix placed with at least one optically active material with an absorption wavelength &lgr;a and a reemission wavelength &lgr;r, the optically active material selected such that &lgr;a corresponds to a range of the photovoltaic cell with a lower sensitivity than &lgr;r, the matrix having an input surface and an opposite surface and comprises a reflecting coating an a dichroic filter on the input surface that substantially reflects wavelengths longer than about 950 nm and is substantially transparent for wavelengths less than about 950 nm, and on the opposite surface the matrix has a reflecting coating that reflects wavelengths greater than about 400 nm, and wherein the photovoltaic cell is included in the matrix.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: May 27, 2003
    Assignee: Biocure S.A.R.L.
    Inventors: Philippe Gravisse, Gilles Destremau, Marc Schiffmann
  • Patent number: 6541836
    Abstract: An avalanche drift photodetector (ADP) incorporates extremely low capacitance of a silicon drift photodetector (SDP) and internal gain that mitigates the surface leakage current noise of an avalanche photodetector (APD). The ADP can be coupled with scintillators such as CsI(Tl), NaI(Tl), LSO or others to form large volume scintillation type gamma ray detectors for gamma ray spectroscopy, photon counting, gamma ray counting, etc. Arrays of the ADPs can be used to replace the photomultiplier tubes (PMTs) used in conjunction with scintillation crystals in conventional gamma cameras for nuclear medical imaging.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: April 1, 2003
    Assignee: Photon Imaging, Inc.
    Inventors: Jan Iwanczyk, Bradley E. Patt, Gintas Vilkelis
  • Publication number: 20030042564
    Abstract: A semiconductor device comprises: a semiconductor element; an external terminal used for an external connection; an interposer having the semiconductor element mounted on a first surface thereof and having the external terminal formed on a second surface thereof opposite to the first surface so as to electrically connect the semiconductor element and the external terminal; a resin sealing the semiconductor element on the first surface; and an interconnecting portion formed within the resin, the interconnecting portion having a first connecting part electrically connected to the external terminal and having a second connecting part exposed on an outer surface of the resin.
    Type: Application
    Filed: October 24, 2002
    Publication date: March 6, 2003
    Applicant: Fujitsu Limited
    Inventors: Fumihiko Taniguchi, Akira Takashima
  • Publication number: 20030042565
    Abstract: Field-Effect Transistor Based on Embedded Cluster Structures and Process for Its Production In field-effect transistors, semiconductor clusters, which can extend from the source region to the drain region and which can be implemented in two ways, are embedded in one or a plurality of layers. In a first embodiment, the semiconductor material of the adjacent channel region can be strained by the clusters and the effective mass can thus be reduced by altering the energy band structure and the charge carrier mobility can be increased. In a second embodiment, the clusters themselves can be used as a canal region. These two embodiments can also appear in mixed forms. The invention can be applied to the Si material system with SiGe clusters or to the GaAs material system with InGaAs clusters or to other material systems.
    Type: Application
    Filed: October 25, 2002
    Publication date: March 6, 2003
    Inventors: Oliver G. Schmidt, Karl Eberl
  • Patent number: 6525347
    Abstract: A filter layer and a buffer layer are sequentially laminated on a first principal face of a semiconductor substrate, and an island-shaped light absorption layer and a window layer are laminated on top of the buffer layer. A diffusion region in which p-type impurities have been diffused is formed in the window layer. An n-side electrode and a p-side electrode are formed on the buffer layer and the diffusion region, respectively. A light incidence portion is formed on the buffer layer where the light absorption layer has not been formed.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: February 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kenichi Matsuda
  • Publication number: 20020185702
    Abstract: A photodiode array device having an absorption layer and a cladding layer formed on one surface of a single substrate, anodes formed on the cladding layer, a cathode formed on the other surface of the substrate, and a plurality of light-receiving regions; a photodiode module including the photodiode array device; and a structure for connecting the photodiode module and an optical connector. The photodiode array device has trenches formed on the one surface of the substrate and having such a depth as to divide the absorption layer into subdivisions, for cutting off propagation of light between adjacent light-receiving regions.
    Type: Application
    Filed: February 4, 2002
    Publication date: December 12, 2002
    Inventors: Takehiro Shirai, Masayuki Iwase, Takeshi Higuchi, Naoki Tsukiji
  • Patent number: 6489659
    Abstract: A non-hermetic APD for operation in a moisture-containing ambient comprises an InP/InGaAsP-containing Group III-V compound semiconductor body and a p-n junction formed in the body. Typically the junction intersects a top surface of the body. A patterned dielectric layer is formed on the surface so as to cover at least those regions of the surface that are intersected by the junction. An electrode is formed in an opening in the dielectric layer so as to make electrical contact with one side of the junction. Importantly, the thickness of the dielectric layer is sufficient to reduce the leakage current through it to less than about 1 nA when the operating voltage is in the range of about 20-100 V. In accordance with a preferred embodiment, the thickness of the dielectric layer is greater than about 2 &mgr;m when the applied voltage is in excess of about 20 V. Moreover, the composition of dielectric layer may be either inorganic (e.g., a silicon nitride) or a combination of inorganic and organic materials.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: December 3, 2002
    Assignee: Agere Systems Inc.
    Inventors: Utpal Kumar Chakrabarti, Robert Benedict Comizzoli, John William Osenbach, Christopher Theis
  • Patent number: 6445020
    Abstract: A semiconductor light-receiving device 1a comprises a first InP layer 12 having a first conductive type region 20a, a second InP layer 16 having a second conductive type, and an InGaAs light-receiving layer 14 disposed between these layers 12, 16. The InP layer 16 of second conductive type has a maximum carrier concentration of 1×1017 cm−3 or higher. Because of this carrier concentration, the depletion layer caused by an applied reverse bias to extend into the InP layer 16 becomes sufficiently small. Therefore, this depletion layer spreads within the light-receiving layer 14 in which electron-hole pairs are generated. Hence, the applied voltage can fully be utilized for drifting generated carriers. Thus provided is a semiconductor light-receiving device in which the occurrence of wave tails is reduced.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: September 3, 2002
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yasushi Fujimura
  • Patent number: 6437233
    Abstract: A solar cell comprises a superstrate formed from a material that is transparent to light, a first layer formed of delta doped silicon, a plurality of layers formed from semiconductor materials, each characterized by multi-quantum wells and multiple band gaps, a first semiconductor layer having a band gap energy state that is the smallest, the last semiconductor layer having-a band gap that is the largest, and the intermediate semiconductor layers having band gaps transitioning from the smallest to the largest, a second layer overlying the semiconductor layers and formed of delta doped silicon, an n-cap layer formed on the second delta doped layer, and a metal layer formed on the n-cap layer and serving to reflect light into the semiconductor.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: August 20, 2002
    Assignee: TRW Inc.
    Inventors: Dean Tran, George J. Vendura, Jr., William L. Jones, Edward A. Rezek
  • Patent number: 6429499
    Abstract: Disclosed is a semiconductor structure and manufacturing process for making an integrated FET and photodetector optical receiver on a semiconductor substrate. A FET is formed by forming at least one p region in a p-well of the substrate and forming at least one n region in the p-well of the substrate. A p-i-n photodetector is formed in the substrate by forming at least one p region in an absorption region of the substrate when forming the at least one p region in the p well of the FET and forming at least one n region in the absorption region of the substrate when forming the at least one n region in the p-well of the FET.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventors: Randolph B. Heineke, William K. Hogan, Scott Allen Olson, Clint Lee Schow
  • Patent number: 6392282
    Abstract: An APD is provided, said APD having an N-type first buried region (cathode) formed on a P-type substrate, and P-type first, second layer, and fourth semiconductor region (anode) formed thereon. A vertical type PNP transistor is provided, said vertical type PNP transistor having the N-type first buried region formed on the substrate, a P-type first buried region and a P-type second semiconductor layer (collector) formed on the P-type first semiconductor layer, and an N-type second semiconductor region (base) in the P-type second semiconductor layer. A vertical type NPN transistor is provided, said vertical type NPN transistor having an N-type second buried region and an N-type first semiconductor region (collector) in the substrate, and a P-type third semiconductor region (base) in the N-type first semiconductor region. An NMOS is provided in the surface of the P-type second semiconductor layer. A PMOS is provided in the surface of the N-type second semiconductor region.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: May 21, 2002
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Masanori Sahara, Takashi Suzuki
  • Patent number: 6384462
    Abstract: A planar avalanche photodetector (APD) is fabricated by forming a, for example, InGaAs absorption layer on a p+-type semiconductor substrate, such as InP, and wafer-bonding to the absorption layer a second p-type semiconductor, such as Si, to form a multiplication layer. The layer thickness of the multiplication layer is substantially identical to that of the absorption layer. A region in a top surface of the p-type Si multiplication layer is doped n+-type to form a carrier separation region and a high electric field in the multiplication region. The APD can further include a guard-ring to reduce leakage currents as well as a resonant mirror structure to provide to wavelength selectivity. The planar geometry furthermore favors the integration of high-speed electronic circuits on the same substrate to fabricate monolithic optoelectronic transceivers.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: May 7, 2002
    Assignee: Nova Crystals, Inc.
    Inventors: Alexandre Pauchard, Yu-Hwa Lo
  • Patent number: 6365951
    Abstract: Methods of laying out avalanche light emitting diodes (LEDs) are described in which a heavily impurity doped region of one type of polarity, a second, lighter doped region of like polarity, and a heavy doped region of opposite type polarity are disposed in a silicon substrate. Electrodes are laid out such that light emitted by the avalanching PN junction is not blocked. Construction features include shallow implants to improve efficiency and implants which avoid the silicon-oxide interface for stability and implants which avoid junction corners to avoid concentrating injection. Construction of vertical and side emitting junctions are disclosed. Also disclosed are construction details of side emitting SOI junctions which are useful in SOI based opto couplers.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: April 2, 2002
    Inventor: Eugene Robert Worley
  • Patent number: 6359322
    Abstract: The present disclosure relates to an avalanche photodiode having edge breakdown suppression. The photodiode comprises a p contact and an n contact, as well as a plurality of device layers disposed between the p contact and the n contact. The device layers include, in order from the p contact to the n contact, a primary well, a decoupler layer, a multiplication layer, a charge sheet, an absorption layer, and a substrate. The layers are constructed so as to have particular volumes of charge which affects the order in which they deplete. With the preferred order of depletion, the multiplication layer will deplete before the decoupler layer and the decoupler layer will deplete before the charge sheet when a negative bias is applied to the avalanche photodiode. This results in a joint opening effect within the avalanche photodiode which effectively suppresses edge breakdown.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: March 19, 2002
    Assignee: Georgia Tech Research Corporation
    Inventors: Joe N. Haralson, Kevin F. Brennan
  • Patent number: 6353238
    Abstract: A novel use of a solid state light detector with a low impedance substrate is described. Light that enters the substrate after traversing the antireflective layer creates an electron-hole pair. The electrons are collected in a crystalline epitaxial layer that spans the space charge region, or depletion layer. A high electric field accelerates free electrons inside the depletion region. The electrons collide with the lattice to free more holes and electrons resulting from the presence of a n-p junction, or diode. The diode is formed by placing the crystalline layer which has positive doping in close proximity with the electrodes which have negative doping. The continual generation of charge carriers results in avalanche multiplication with a large multiplication coefficient. During the avalanche process, electrons can be collected enabling light detection. A resistive layer is used to quench, or stop, the avalanche process.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: March 5, 2002
    Assignee: Board of Regents, The University of Texas System
    Inventors: Peter P. Antich, Edward N. Tsyganov
  • Patent number: 6316715
    Abstract: A multijunction photovoltaic cell comprises a first subcell that initially receives incident light upon the photovoltaic cell, with the first subcell being made of a first material system, having a first thickness, and producing a first photogenerated current output. A second subcell receives the incident light after the first subcell receives the incident light, with the second subcell being disposed immediately adjacent the first subcell. The second subcell is made of the first material system or a similar semiconductor material, has a second thickness that is greater than the first thickness, and produces a second photogenerated current output that is substantially equal in amount to the first photogenerated current output. A tunnel junction is disposed between the first and second subcells. The multijunction cell provides a greater ability to current match to low-current-producing subcells, higher multijunction cell voltage, lower series resistance, and greater radiation resistance.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: November 13, 2001
    Assignee: The Boeing Company
    Inventors: Richard R. King, David E. Joslin, Nasser H. Karam
  • Publication number: 20010022368
    Abstract: A novel use of a solid state light detector with a low impedance substrate is described. Light that enters the substrate after traversing the antireflective layer creates an electron-hole pair. The electrons are collected in a crystalline epitaxial layer that spans the space charge region, or depletion layer. A high electric field accelerates free electrons inside the depletion region. The electrons collide with the lattice to free more holes and electrons resulting from the presence of a n-p junction, or diode. The diode is formed by placing the crystalline layer which has positive doping in close proximity with the electrodes which have negative doping. The continual generation of charge carriers results in avalanche multiplication with a large multiplication coefficient. During the avalanche process, electrons can be collected enabling light detection. A resistive layer is used to quench, or stop, the avalanche process.
    Type: Application
    Filed: April 23, 2001
    Publication date: September 20, 2001
    Applicant: Board of Regents, The University of Texas System
    Inventors: Peter P. Antich, Edward N. Tsyganov
  • Patent number: 6265727
    Abstract: A solar blind p-i-n photodiode where the active i-region has a bandgap larger than the bandgap of one or both of the n-type and p-type regions. The preferred embodiment photodiode is GaN based and Al is added to the regions to obtain the desired bandgap profiles. Al is added to the i-region to obtain a bandgap large enough to be responsive to light in the solar blind spectrum. By having a smaller bandgap p-type and n-type region, the problems associated with growing highly doped AlGaN are avoided. In most embodiments the light incident on the photodiode illuminates the p-type region first. The p-type region is grown thin compared to conventional photodiodes which allows the majority of light incident to pass through the p-type region to the i-region. Light with sufficient energy will be detected in the i-region. The inventive photodiode can also be used in the fabrication of backside illuminated solar blind photodiodes that are useful for photodiode arrays.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: July 24, 2001
    Assignee: Cree Lighting Company
    Inventors: Peter Kozodoy, Eric J. Tarsa
  • Patent number: 6222209
    Abstract: A novel use of a solid state light detector with a low impedance substrate is described. Light that enters the substrate after traversing the antireflective layer creates an electron-hole pair. The electrons are collected in a crystalline epitaxial layer that spans the space charge region, or depletion layer. A high electric field accelerates free electrons inside the depletion region. The electrons collide with the lattice to free more holes and electrons resulting from the presence of an n-p junction, or diode. The diode is formed by placing the crystalline layer which has positive doping in close proximity with the electrodes which have negative doping. The continual generation of charge carriers results in avalanche multiplication with a large multiplication coefficient. During the avalanche process, electrons can be collected enabling light detection. A resistive layer is used to quench, or stop, the avalanche process.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: April 24, 2001
    Assignee: Board of Regents, The University of Texas System
    Inventors: Peter P. Antich, Edward N. Tsyganov
  • Patent number: 6188083
    Abstract: A pin diode, having a p-layer, an n-layer, and an i-layer sandwiched by the p-layer and the n-layer, is constituted by a quantum-wave interference unit with a plurality of pairs of a first layer W and a second layer B. The second layer B has a wider band gap than the first layer W. Each thickness of the first layer W and the second layer b is determined by multiplying by odd number one fourth of quantum-wave wavelength of carriers in each of the first layer W and the second layer B. A &dgr; layer sharply varying in band gap energy from the first and second layers is formed at every interface between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. A plurality of quantum-wave interference units are formed sandwiching carrier accumulation layers in series. Then, the I-V characteristic of the diode indicates that, for values of an applied backward voltage, a backward electric current can flow rapidly.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: February 13, 2001
    Assignee: Canare Electric Co., Ltd.
    Inventor: Hiroyuki Kano
  • Patent number: 6166320
    Abstract: A solar cell that is capable of having a thickness optimum for the highest photoelectric conversion efficiency and achieves reduction of carrier recombination loss is provided. For this purpose, a solar cell (10) is formed by stacking a top cell (12) including an n.sup.+ layer, a p layer, and a p.sup.+ layer, and a bottom cell (14) including an n.sup.+ layer and a p.sup.+ layer arranged at the bottom of the p layer along the back surface. The top cell (12) has a band gap wider than that of the bottom cell (14). A top electrode (18) is formed at the n.sup.+ layer of the top cell (12), while a negative electrode (26) and a positive electrode (28) are individually connected to the n.sup.+ layer and the p.sup.+ layer of the bottom cell (14), respectively.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: December 26, 2000
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tomonori Nagashima, Takeshi Nishikawa
  • Patent number: 6111299
    Abstract: A large area avalanche photodiode device that has a plurality of contacts formed on a bottom side that are isolated from each other by various kinds of isolation structures. In one embodiment, a cavity is formed in one layer of the avalanche photodiode that extends to a depletion region that exists in the layer as a result of a voltage applied to the device. The plurality of contacts are formed in the cavity so that each of the contacts are positioned substantially adjacent the depletion region. In another embodiment, a plurality of contacts are formed in a cavity and an isolation structure comprised of a grid of semiconductor material is formed so as to be interposed between adjacent contacts. The isolation structure preferably forms a p-n junction with the surrounding semiconductor material and the p-n junction provides isolation between adjacent contacts.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: August 29, 2000
    Assignee: Advanced Photonix, Inc.
    Inventors: Andrzej J. Dabrowski, Vladimir K. Eremin, Anatoly I. Sidorov
  • Patent number: 6104047
    Abstract: The present invention relates to an avalanche photodiode having a simple structure, high reliability, and a high speed response on the order of Gbps. This photodiode is formed by depositing laminated layers on a semiconductor substrate in the order of an n-type buffer layer, a semiconductor multiplication layer, a p-type semiconductor field buffer layer, a p-type semiconductor light absorbing layer, a p-type semiconductor cap layer, and a p-type semiconductor contact layer, and said p-type semiconductor light absorbing layer is constructed by two layers consisted of a depleted region of a thickness in the range of 10 nm to 0.3 .mu.m disposed adjacent to the p-type semiconductor field buffer layer and a non-depleted layer region at a thickness of less than 2 .mu.m disposed adjacent to the depleted layer region.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: August 15, 2000
    Assignee: NEC Corporation
    Inventor: Isao Watanabe
  • Patent number: 6072201
    Abstract: An amorphous silicon based hole-injection type "Separate Absorption and Multiplication Avalanche Photodiode" ("SAMAPD") has been invented. The device was made by separating an absorption layer and an avalanche layer from a conventional APD (Avalanche Photodiode). This will make a majority of an voltage bias to go across on the avalanche layer (i.e., a high energy bandgap material) and to enlarge an avalanche multiplication effect (i.e., increasing optical gains). In addition, the voltage bias goes across on the absorption layer will be sufficiently small to reduce a dark current. Using an i-a-Si:H material as the avalanche layer material and an i-a-Si.sub.1-x :Ge.sub.x :H material as the absorption layer material, the hole-injection type SAMPAD yields a very high gain, i.e., 686, at a reverse bias of 16V under an incident light power of P.sub.in =1 .mu.w. The product of this invention is very suitable for use in a long distance optical communication.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: June 6, 2000
    Assignee: National Science Counsel
    Inventors: Yeau-Kuen Fang, Kuen-Hsien Lee, Gun-Yuan Lee
  • Patent number: 5977602
    Abstract: A semiconductor device having an oxygen-rich punchthrough region under the channel region, and a process for fabricating such a device are disclosed. In accordance with one embodiment, a semiconductor device is formed by forming an oxygen-rich punchthrough region in a substrate, and forming a channel region over the oxygen-rich punchthrough region. The use of an oxygen-rich punchthrough region may, for example, inhibit the diffusion of dopants used in forming the channel region.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: November 2, 1999
    Assignee: Advanced Micro Devices
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 5942788
    Abstract: A solid state image sensing device having a semiconductor substrate, a first diffusion region of a positive or negative conductive type provided on the semiconductor substrate, a plurality of second diffusion regions each of which is an opposite conductive type relative to the first diffusion region and is provided in the first diffusion region, and a semiconductor thin layer provided on at least the second diffusion regions.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: August 24, 1999
    Assignee: Minolta Co., Ltd.
    Inventors: Kenji Takada, Kouichi Ishida, Keiichi Nomura, Yoshihiro Hamakawa, Hiroaki Okamoto
  • Patent number: 5923071
    Abstract: A semiconductor substrate having a silicon-on-insulator structure may achieve superior performance by utilizing a low oxygen content monocrystalline silicon thin film layer for device formation. A supporting substrate, which may comprise a transparent material, such as quartz, or which may be silicon, has an insulating film disposed thereover. The insulating film preferably has a lower diffusion coefficient with respect to impurities than the monocrystalline silicon thin film, which is provided thereover. In accordance with this structure, oxygen particles are not introduced into the monocrystalline thin film and the thin film has a low oxygen concentration to maximize the minority carrier lifetime, enhance device performance characteristics, and prevent the occurrence of latch up.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: July 13, 1999
    Assignee: Seiko Instruments Inc.
    Inventor: Yutaka Saito
  • Patent number: 5912478
    Abstract: An avalanche photodiode having an absorption zone, a multiplication zone, and a transition zone disposed between the absorption zone and the multiplication zone, the transition zone being doped and being constituted at least in part by a material of composition that is graded such that the energy bands of the structure are substantially continuous when it is biased, wherein said doping is distributed non-uniformly in said graded composition zone so as to compensate, at least in part, the reverse electric field due to the composition grading of the material in the transition zone.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: June 15, 1999
    Assignee: France Telecom
    Inventors: Thomas Barrou, Andre Scavennec
  • Patent number: 5880490
    Abstract: The disclosed invention includes an apparatus and method for detecting radiation in a detector. The radiation to be detected ionizes the atoms in the intrinsic silicon lattice of the detector to produce a small signal of freed elections. The small signal is then amplified by avalanche multiplication in a self-limiting manner by preventing the amplified electrons from traveling through a resistive layer, thereby reducing the electric field to limit the avalanche multiplication. An imaging system incorporating the new detector design is also disclosed.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: March 9, 1999
    Assignee: Board of Regents, The University of Texas System
    Inventors: Peter P. Antich, Edward N. Tsyganov
  • Patent number: 5874752
    Abstract: A light detecting device includes a first conductivity type semiconductor substrate; an insulating semiconductor window layer disposed on the substrate; a concavity in a region of the window layer and penetrating through the window layer; successively disposed in the concavity, a first conductivity type lower cladding layer, a first conductivity type guide layer of a semiconductor material having a band gap energy smaller that the band gap energies of the lower cladding layer and the window layer, an undoped light absorption layer having a band gap energy smaller than that of the first conductivity type guide layer, and a second conductivity type guide layer having a composition approximately identical to that of the first conductivity type guide layer, edges of the first conductivity type guide layer, the light absorption layer, and the second conductivity type guide layer being exposed at a surface of the window layer; and a layer of an insulating material, covering the edges.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: February 23, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tatsuya Kimura
  • Patent number: 5866936
    Abstract: A mesa-structure avalanche photodiode in which a buffer region in the surface of the mesa structure effectively eliminates the sharply-angled, heavily doped part of the cap layer that existed adjacent the lightly-doped n-type multiplication layer and p-type guard ring before the buffer region was formed. This reduces electric field strength at the ends of the planar epitaxial P-N junction and prevents edge breakdown in this junction. The lateral extent of the guard ring is defined by a window formed in a masking layer prior to regrowth of the guard ring. This guard ring structure eliminates the need to perform additional processing steps to define the lateral extent of the guard ring and passivate the periphery of the guard ring.
    Type: Grant
    Filed: April 1, 1997
    Date of Patent: February 2, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Ghulam Hasnain, James N. Hollenhorst, Chung-Yi Su
  • Patent number: 5844291
    Abstract: A novel use of a solid state light detector with a low impedance substrate is described. Light that enters the substrate after traversing the antireflective layer creates an electron-hole pair. The electrons are collected in a crystalline epitaxial layer that spans the space charge region, or depletion layer. A high electric field accelerates free electrons inside the depletion region. The electrons collide with the lattice to free more holes and electrons resulting from the presence of a n-p junction, or diode. The diode is formed by placing the crystalline layer which has positive doping in close proximity with the electrodes which have negative doping. The continual generation of charge carriers results in avalanche multiplication with a large multiplication coefficient. During the avalanche process, electrons can be collected enabling light detection. A resistive layer is used to quench, or stop, the avalanche process.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: December 1, 1998
    Assignee: Board of Regents, The University of Texas System
    Inventors: Peter P. Antich, Edward N. Tsyganov
  • Patent number: 5831322
    Abstract: A large area avalanche photodiode device that has a plurality of contacts formed on a bottom side that are isolated from each other by various kinds of isolation structures. In one embodiment, a cavity is formed in one layer of the avalanche photodiode that extends to a depletion region that exists in the layer as a result of a voltage applied to the device. The plurality of contacts are formed in the cavity so that each of the contacts are positioned substantially adjacent the depletion region. In another embodiment, a plurality of contacts are formed in a cavity and an isolation structure comprised of a grid of semiconductor material is formed so as to be interposed between adjacent contacts. The isolation structure preferably forms a p-n junction with the surrounding semiconductor material and the p-n junction provides isolation between adjacent contacts.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: November 3, 1998
    Assignee: Advanced Photonix, Inc.
    Inventors: Andrzej J. Dabrowski, Vladimir K. Eremin, Anatoly I. Sidorov
  • Patent number: 5818096
    Abstract: A pin photodiode having a structure capable improving the frequency response and the saturation output while maintaining the effective internal quantum efficiency and CR time constant. A pin photodiode is formed by: a first semiconductor layer in a first conduction type; a second semiconductor layer in a second conduction type; a third semiconductor layer sandwiched between the first and second semiconductor layers, having a doping concentration lower than those of the first and second semiconductor layers; a fourth semiconductor layer in the first conduction type, provided at one side of the first semiconductor layer opposite to a side at which the third semiconductor layer is provided; and a cathode electrode and an anode electrode connected directly or indirectly to the second semiconductor layer and the fourth semiconductor layer, respectively.
    Type: Grant
    Filed: April 3, 1997
    Date of Patent: October 6, 1998
    Assignee: Nippon Telegraph and Telephone Corp.
    Inventors: Tadao Ishibashi, Tomofumi Furuta, Naofumi Shimizu, Koichi Nagata, Yutaka Matsuoka, Masaaki Tomizawa
  • Patent number: 5808350
    Abstract: An imaging device (10) has a plurality of unit cells that contribute to forming an image of a scene. The imaging device includes a layer of semiconductor material (16), for example silicon, that has low noise photogate charge-mode readout circuitry (20, 21, 26, 28) (e.g., CCD or CMOS readout circuitry and structures) that is disposed upon a first surface (18) of the layer. A second, opposing surface of the layer is a radiation admitting surface of the layer. The layer has a bandgap selected for absorbing electromagnetic radiation having wavelengths shorter than about one micrometer and for generating charge carriers from the absorbed radiation. The generated charge carriers are collected by the photogate charge-mode readout circuitry. A thermal sensing element (22) is disposed above and is thermally isolated from the first surface of the layer. The thermal sensing element may be, by example, one of a bolometer element, a pyroelectric element, or a thermopile element.
    Type: Grant
    Filed: January 3, 1997
    Date of Patent: September 15, 1998
    Assignee: Raytheon Company
    Inventors: Michael D. Jack, Michael Ray, Richard H. Wyles
  • Patent number: 5783838
    Abstract: Described is a semiconductor photo detector comprising, between two electrodes, at least one of said electrodes being a transparent electrode, an optical absorption layer which is composed of a non-single crystalline material, absorbs light and generates photo carriers and a carrier multiplication layer which is composed of a non-single crystalline material and multiplies the photo carriers generated by the optical absorption layer. The carrier multiplication layer is formed of a multilayer film obtained by stacking films each having plural layers which are composed of non-single crystalline Zn.sub.x Cd.sub.1-x M (0.ltoreq.x.ltoreq.1, M represents one selected from the group consisting of S, Se and Te) and are different in a composition ratio in accordance with a change in the value of x in said Zn.sub.x Cd.sub.1-x M, whereby a band discontinuity .DELTA.Ec of the conduction band can be made larger, an ionization rate of electrons can be heightened and the place where ionization occurs can be specified.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: July 21, 1998
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Shinya Kyozuka, Takeshi Nakamura, Takayuki Yamada, Yasuaki Miyamoto