Abstract: Disclosed herein is a transparent glass system that includes an optical grade silicon substrate, a transparent substrate layer; a titanium dioxide transparent layer, the transparent layer having an index of refraction of 2.35 or greater; and a polycrystalline diamond layer, wherein the transparent layer is between the substrate layer and the polycrystalline diamond layer.

Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.

Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. A semiconductor layer of a transistor is formed using a composite oxide semiconductor in which a first region and a second region are mixed. The first region includes a plurality of first clusters containing one or more of indium, zinc, and oxygen as a main component. The second region includes a plurality of second clusters containing one or more of indium, an element M (M represents Al, Ga, Y, or Sn), zinc, and oxygen. The first region includes a portion in which the plurality of first clusters are connected to each other. The second region includes a portion in which the plurality of second clusters are connected to each other.

Abstract: A display device includes a substrate including a display area and a non-display area. The display device further includes a plurality of pixels in the display area of the substrate. The display device additionally includes a plurality of gate lines and a plurality of data lines respectively connected to the plurality of pixels. The display device further includes a plurality of insulative step portions disposed in the non-display area of the substrate and arranged in a first direction parallel to sides of the display area. The display device further includes a crack detection line in the non-display area and extending primarily in the first direction. The crack detection line includes a first portion which does not overlap the plurality of insulative step portions, and a second portion overlapping each of the insulative step portions.

Abstract: A highly reliable semiconductor device includes a first insulator, a second insulator, a first conductor, a third insulator, an oxide semiconductor, second and third conductors, a fourth insulator, a fourth conductor overlapping with a region between the second and third conductors, a fifth insulator, and a sixth insulator in this order. The fourth insulator is in contact with top and side surfaces of the oxide semiconductor, and a top surface of the third insulator. The fifth insulator is in contact with the side surface of the oxide semiconductor and the top surface of the third insulator so as to cover the oxide semiconductor, the second to fourth conductors, and the fourth insulator. The first, second, fifth, and sixth insulators have low permeability for hydrogen, water, and oxygen. The first and sixth insulators have a thinner thickness than the second and sixth insulators, respectively.

Abstract: A touch display substrate and a touch detection method thereof. The touch display substrate includes: a base substrate, and a photo-sensitive touch element and an Organic Light-Emitting Diode (“OLED”) device that are arranged on the base substrate sequentially. The photo-sensitive touch element includes a touch electrode layer, a photo-sensitive material layer, an insulating layer and an ITO layer that are arranged sequentially, wherein an orthographic projection of a touch sensing area of the touch electrode layer completely covers an orthographic projection of a pattern of the photo-sensitive material layer, and is within an orthographic projection of the ITO layer. The arrangement of the photo-sensitive touch element neither changes the sequence of manufacturing the layers of the display substrate, nor affects the illumination of the touch display substrate and is suitable for manufacturing a large-size touch screen.

Abstract: A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric.

Abstract: A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.

Abstract: A display panel includes a first metal layer and a second metal layer sequentially stacked. The first metal layer includes a plurality of first metal lines and first gaps arranged between the first metal lines. The second metal layer includes a plurality of second metal lines arranged in a spaced manner. The second metal lines have an extension direction that is identical to an extension direction of the first metal lines. The second metal lines and the first metal lines are arranged to stagger, in position, with respect to each other. The second metal lines have orthogonal projections on the first metal layer that are located in areas of the first gaps in order to prevent shorting between the second metal lines in a process of manufacturing the second metal lines. A method for manufacturing the display panel and a display device are also provided.

Abstract: A flexible display device is disclosed, which may prevent a crack from being generated even though a bending area is folded and prevents a gate driving circuit from being damaged and prevents a gate shift clock line from being shorted even though the crack is generated. The flexible display device comprises a substrate including a display area for displaying an image, a non-display area surrounding the display area, and a bending area. A pixel for displaying an image, an inorganic film for covering the pixel and a first organic film for covering the inorganic film are arranged on an area corresponding to the display area of the bending area, and the first organic film is arranged on an area corresponding to the non-display area of the bending area.

Abstract: An object is to provide a semiconductor device using an oxide semiconductor having stable electric characteristics and high reliability. A transistor including the oxide semiconductor film in which a top surface portion of the oxide semiconductor film is provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film and functioning as a channel protective film is provided. In addition, the oxide semiconductor film used for an active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by heat treatment in which impurities such as hydrogen, moisture, a hydroxyl group, or a hydride are removed from the oxide semiconductor and oxygen which is a major constituent of the oxide semiconductor and is reduced concurrently with a step of removing impurities is supplied.

Abstract: A novel material is provided. A composite oxide semiconductor includes a first region and a second region. The first region contains indium. The second region contains an element M (the element M is one or more of Ga, Al, Hf, Y, and Sn). The first region and the second region are arranged in a mosaic pattern. The composite oxide semiconductor further includes a third region. The element M is gallium. The first region contains indium oxide or indium zinc oxide. The second region contains gallium oxide or gallium zinc oxide. The third region contains zinc oxide.

Abstract: Two dual-gate transistors, which are electrically connected in parallel and provided in a compact design, are disclosed.

Abstract: A metal oxide film containing a crystal part is provided. Alternatively, a metal oxide film with highly stable physical properties is provided. Alternatively, a metal oxide film with improved electrical characteristics is provided. Alternatively, a metal oxide film with which field-effect mobility can be increased is provided. A metal oxide film including In, M (M is Al, Ga, Y, or Sn), and Zn includes a first crystal part and a second crystal part; the first crystal part has c-axis alignment; the second crystal part has no c-axis alignment; and the existing proportion of the second crystal part is higher than the existing proportion of the first crystal part.

Abstract: Carbon allotropes, a thin-film transistor array substrate comprising the same, and a display device comprising the same are disclosed. The thin-film transistor array substrate comprising a substrate, a gate electrode on the substrate, a gate insulating film on the gate electrode, an active layer positioned on the gate insulating film and comprising a semiconductor material and a plurality of carbon allotropes, and a source electrode and a drain electrode that make contact with the active layer.

Abstract: A semiconductor device including a transistor and a wiring electrically connected to the transistor each of which has excellent electrical characteristics because of specific structures thereover is provided. A first conductive film, a first insulating film over the first conductive film, a second conductive film over the first insulating film, a second insulating film over the second conductive film, a third conductive film electrically connected to the first conductive film through an opening provided in the first insulating film and the second insulating film, and a third insulating film over the third conductive film are provided. The third conductive film includes indium, tin, and oxygen, and the third insulating film includes silicon and nitrogen and the number of ammonia molecules released from the third insulating film is less than or equal to 1×1015 molecules/cm3 by thermal desorption spectroscopy.

Abstract: A thin film transistor includes a gate electrode, a semiconductor layer, and source and drain electrodes contacting the semiconductor layer. The source and drain electrodes include a metal oxide having a crystal size in a c-axis direction Lc(002) that ranges from 67 ? or more to 144 ? or less.

Abstract: A method of preparing IGZO thin film transistor is provided. The method includes. step S1, using a first mask on a first metal layer to form a grid electrode, and sequentially forming grid insulating layer, IGZO semiconducting layer and second metal layer on grid electrode; step S2, coating photoresist layer on second metal layer, and exposure developing photoresist layer by second mask, and simultaneously etching second metal layer and IGZO semiconducting layer by hydrogen peroxide, and second metal layer is formed to source electrode and drain electrode by etching; step S3, forming passivation layer on source electrode and drain electrode, and forming a via hole above drain electrode by third mask; step S4, forming pixel electrode on passivation layer by fourth mask, and pixel electrode is connecting to drain electrode by via hole.

Abstract: A thin film transistor substrate may include a base substrate, a semiconductor member, a gate electrode, a first insulation layer, and a source/drain electrode. The semiconductor member may overlap the base substrate. The gate electrode may overlap the semiconductor member and may be insulated from the semiconductor member. The first insulation layer may be positioned on the gate electrode and may include a first contact hole. The source/drain electrode may include a first discharge hole, may be electrically connected to the semiconductor member, and may be at least partially positioned inside the first contact hole. The first discharge hole may partially expose the semiconductor member.

Abstract: A method for fabricating a thin film transistor substrate includes forming a buffer layer including at least one film on a base substrate, planarizing a surface of the buffer layer, and forming a thin film transistor on the buffer layer.

Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transmitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.

Abstract: A metal structure includes a patterned molybdenum tantalum oxide layer and a patterned metal layer. The patterned molybdenum tantalum oxide layer is disposed on a first substrate, in which the patterned molybdenum tantalum oxide layer includes about 2 to 12 atomic percent of tantalum. Both of an atomic percent of molybdenum and an atomic percent of oxygen of the patterned molybdenum tantalum oxide layer are greater than the atomic percent of tantalum of the patterned molybdenum tantalum oxide layer. The patterned metal layer is disposed on the patterned molybdenum tantalum oxide layer.

Abstract: An array substrate and a display panel; the array substrate includes a substrate (6), a gate elelctrode (2), a gate insulation layer (1), a semiconductor active layer, a first etching barrier layer (4), and a source-drain layer (5); the gate elelctrode (2) is disposed at the substrate (6); and the gate insulation layer (1) covers the gate elelctrode (2).

Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 ?m is 1 aA or less.

Abstract: A film forming method of forming a film on a substrate includes: annealing the substrate; and supplying mist of a raw material solution of the film to a surface of the substrate after the annealing while heating the substrate at a temperature lower than a temperature of the substrate during the annealing.

Abstract: A TFT substrate includes TFTs, patch electrodes formed in a patch metal layer, and gate connection wiring lines formed in a gate metal layer. The patch metal layer includes: a first portion having a layered structure including a lower metal layer containing a refractory metal and an upper metal layer containing Cu, Al, or Ag; and a second portion including the lower metal layer and not including the upper metal layer. The first portion includes the patch electrode, and the second portion includes a first patch connection section electrically connecting a source bus line to the gate connection wiring line. The first patch connection section is in contact with the source bus line in a first opening provided in a first insulating layer, and is in contact with the gate connection wiring line in a second opening provided in a gate insulating layer and the first insulating layer.

Abstract: Integrated active-matrix light emitting pixel arrays based displays and methods of fabricating the integrated displays are provided. One of the methods include: forming first color light emitting diodes (LEDs) and respective intermediate metallic layers on a first substrate, integrating the first color LEDs with pixel circuits in a backplane device, injecting laser pulses into particular first color LEDs, such that each particular first color LED is individually separated from the first substrate and locally bonded with a respective pixel circuit through a respective intermediate metallic layer, and removing the first substrate from the backplane device. The backplane device bonded with the particular first color LEDs can be further bonded with other different color LEDs formed on other substrates. Other first color LEDs without exposure of the laser pulses are removed with the first substrate and can be further used to integrate with another backplane device bonded with another color LEDs.

Abstract: A thin film transistor 100 according to the invention includes a gate electrode 20, a channel 44, and a gate insulating layer 34 provided between the gate electrode 20 and the channel 44 and made of oxide (possibly containing inevitable impurities; this applies to oxide hereinafter) containing lanthanum and zirconium. The channel 44 is made of channel oxide including first oxide containing indium, zinc, and zirconium (Zr) having an atomic ratio of 0.015 or more and 0.075 or less relative to indium assumed to be 1 in atomic ratio, second oxide containing indium and zirconium (Zr) having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio, or third oxide containing indium and lanthanum having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio.

Abstract: Microbolometer is a class of infrared detector whose resistance changes when the temperature changes. In this work, we deposited and characterized Germanium Oxide thin films mixed with Sn (Ge—Sn—O) for uncooled infrared detection. Ge—Sn—O were deposited by co-sputtering of Sn and Ge targets in the Ar+O environment using a radio frequency sputtering system. Optical characterization shows that the absorption in Ge—Sn—O was most sensitive in the wavelength ranges between 1.0-3.0 ?m. The transmission data was further used to determine the optical energy band gap (0.678 eV) of the thin-film using Tauc's equation. We also found the variations of absorption coefficient (1.4802×105 m?1-1.0097×107 m?1), refractive index (1.242-1.350), and the extinction coefficient (0.3255-8.010) for the wavelength ranges between 1.0-3.0 ?m. The thin film's resistivity measured by the four point probe was found to be 4.55 ?-cm and TCR was in the range of ?2.56-?2.25 (%/K) in the temperature range 292-312K.

Abstract: A transistor using an oxide semiconductor, which has good on-state characteristics is provided. A high-performance semiconductor device including the transistor capable of high-speed response and high-speed operation is provided. The transistor includes the oxide semiconductor film including a channel formation region and low-resistance regions in which a metal element and a dopant are included. The channel formation region is positioned between the low-resistance regions in the channel length direction. In a manufacturing method of the transistor, the metal element is added by heat treatment performed in the state where the oxide semiconductor film is in contact with a film including the metal element and the dopant is added through the film including the metal element by an implantation method so that the low resistance regions in which a metal element and a dopant are included are formed.

Abstract: A method of forming a lateral bipolar junction transistor (LBJT) that includes providing a germanium containing layer on a crystalline oxide layer, and patterning the germanium containing layer stopping on the crystalline oxide layer to form a base region. The method may further include forming emitter and collector extension regions on opposing sides of the base region using ion implantation, and epitaxially forming an emitter region and collector region on the crystalline oxide layer into contact with the emitter and collector extension regions. The crystalline oxide layer provides a seed layer for the epitaxial formation of the emitter and collector regions.

Abstract: A trench MOS-type Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer opposite to the first semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer opposite to the second semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench MOS gate that is embedded in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode.

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.

Abstract: A display device according to the present invention includes a substrate, and a plurality of pixels arranged in the substrate, wherein each of the plurality of pixels includes a light emitting element, a first transistor, a second transistor, a first insulation layer and a second insulation layer, the first transistor includes a first semiconductor layer, the second transistor includes a second semiconductor layer, the first insulation layer is arranged across the plurality of pixels between the first semiconductor layer and the second semiconductor layer, the second insulation layer is arranged between the first insulation layer and the second semiconductor layer, the first semiconductor layer is arranged on the substrate side sandwiching the first insulation layer with respect to the second semiconductor layer, the first insulation layer includes a silicon oxide layer; and the second insulation layer includes an aluminum oxide layer.

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. One of (a) a channel region of e transistor, or (b) a pair of electrodes of the capacitor, is directly above the other of (a) and (b). Additional embodiments and aspects are disclosed.

Abstract: A method for manufacturing a thin film transistor includes forming a light shielding layer and a buffer layer covering the light shielding layer on a substrate. The method includes forming an active layer including a peripheral region and a channel region. The method includes forming a gate insulating layer covering the channel region and forming a contact hole exposing the light shielding layer. The method includes forming a source region and a drain region disposed on both sides of the channel region. The method includes forming an electrode layer including a gate electrode, a source electrode and a drain electrode spaced apart one another. The method includes forming a dielectric layer covering the gate electrode, the source electrode, the drain electrode and the buffer layer.

Abstract: A liquid crystal cell according to the present invention includes a TFT board including a first dielectric substrate, TFTs supported by the first dielectric substrate, and patch electrodes, a slot board including a second dielectric substrate and a slot electrode having slots and supported by the second dielectric substrate, and a liquid crystal layer between the TFT board and the slot board, which are positioned with the patch electrodes and the slot electrode facing each other, and a sealant disposed between the TFT board and the slot board and surrounding the liquid crystal layer. The liquid crystal layer includes a liquid crystal compound containing an isothiocyanate group. The sealant includes an ene-thiol compound in which an ene compound and a thiol compound are bonded by using a radical.

Abstract: A manufacturing method of a thin-film transistor is provided. The method include: forming a gate pattern layer on a substrate; forming a gate insulating layer covering the gate pattern layer; depositing semi-conductive oxide material on the gate insulating layer to form an active pattern layer on the gate insulating layer; depositing reducing material on the active pattern layer to form a reducing pattern layer; and forming a source pattern layer and a drain pattern layer on the reducing pattern layer. A thin-film transistor is further provided.

Abstract: Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).

Abstract: A semiconductor device comprising a pixel portion comprising a capacitor and a transistor is provided. The capacitor comprises a first oxide semiconductor film and a transparent conductive material. The transistor comprises a second oxide semiconductor film, a source electrode, and a drain electrode. The transistor is electrically connected to the capacitor. The capacitor is provided to overlap with a first opening portion in an insulating film and a second opening portion in an organic resin film. The transparent conductive material comprises a region over the organic resin film. The second oxide semiconductor film comprises a channel formation region and a first region outside the channel formation region. Each of a carrier density of the first oxide semiconductor film and a carrier density of the first region is higher than a carrier density of the channel formation region.

Abstract: The present disclosure relates to array substrate, preparation method thereof and display panel. An array substrate comprises: a first thin film transistor and a second thin film transistor over a substrate; wherein the first thin film transistor comprises a first portion of a first insulating layer, the first insulating layer comprises a first recess corresponding to the second thin film transistor, and the second thin film transistor is located in the first recess; and wherein a thickness of a second portion of the first insulating layer, which is below the bottom of the first recess, is smaller than that of the first portion of the first insulating layer.

Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.

Abstract: A film touch sensor includes a base film, an adhesive layer, a separation layer and a conductive pattern layer, which are sequentially laminated. The base film has a retardation value Ro in a plane direction of 0 to 10 nm, and a retardation value Rth in a thickness direction of ?10 to 10 nm. When the film touch sensor is applied to a final product, interference between laminates may be minimized to significantly reduce a change in color sense of an image.

Abstract: A semiconductor device capable of retaining data for a long time is provided. A leakage current path between adjacent memory cells in a memory cell array included in the semiconductor device is blocked without increasing the number of manufacturing steps, so that memory retention characteristics can be improved.

Abstract: A display panel and manufacturing method for the same. The display panel includes an array substrate, a passivation layer, an organic planarization layer, a first color resist layer and a second color resist layer and an organic planarization layer. Each sub-pixel circuit includes at least two thin-film transistors; at least two via holes are prepared on the passivation layer and the organic planarization layer. The first color resist layer includes a first color resist region and multiple second color resist regions connected thereto. A projection of the first color resist region on the array substrate is located at two sides of the sub-pixel circuit. Each second color resist region is located above the at least two thin-film transistors; the second color resist layer is stacked above the second color resist region. The first color resist layer will not crack, and the main region spacer can reach a desired height.

Abstract: The present invention provides a thin-film transistor substrate including a base substrate and a thin-film transistor, the thin-film transistor including: a gate electrode; a gate insulating layer; a source electrode and a drain electrode; and an oxide semiconductor layer in this order. The source electrode and the drain electrode each include a first conductive layer and a second conductive layer covering the first conductive layer. The second conductive layer contains at least one element selected from the group consisting of molybdenum, tantalum, tungsten, and nickel. The gate insulating layer in a region between the source electrode and the drain electrode has a smaller thickness than in a region below the source electrode and in a region below the drain electrode.

Abstract: A semiconductor device includes an insulating substrate, a polysilicon layer, a first-gate-insulating layer, a first metal layer, an oxide-semiconductor layer, a second-gate-insulating layer, a second metal layer, a first insulating interlayer, a third metal layer, a first top gate planar type thin film transistor in which the polysilicon layer serves as a channel, and a second top gate planar self-aligned type thin film transistor in which the oxide-semiconductor layer serves as a channel. The gates of the first top gate planar type thin film transistor and the second top gate planar self-aligned type thin film transistor are made of the first and second metal layers, respectively. The sources and the drains of the first top gate planar type thin film transistor and the second top gate planar self-aligned type thin film transistor are made of the third metal layer.

Abstract: Provided are an array substrate and preparation method therefor, and a display apparatus. The array substrate includes: a substrate, the substrate having a first TFT region, a touch control region and a second TFT region; a photosensitive PN junction, the photosensitive PN junction being provided in the touch control region; a first thin-film transistor, provided in the first TFT region, and electrically connected to the photosensitive PN junction; and a second thin-film transistor, provided in the second TFT region, and electrically connected to a pixel electrode.

Abstract: A manufacturing method for an IGZO active layer is disclosed. The method comprises steps of: after depositing a first metal layer and a gate insulation layer on a substrate, depositing an IGZO material on the gate insulation layer, and forming an IGZO film; and performing a plasma cleaning treatment on a surface of the IGZO film by using an argon gas or a helium gas to adjust element contents on the surface of the IGZO film, and forming an IGZO active layer. The present invention also correspondingly discloses a manufacturing method for an oxide thin film transistor. By implementing the embodiments of the present invention, the elements on the film surface of the IGZO active layer can be adjusted to improve electrical properties.

Abstract: A display panel includes a base layer having a first region and a bent second region. An inorganic layer is disposed on the base layer. A lower opening is formed within the inorganic layer and overlaps the second region. A first thin-film transistor is disposed on the inorganic layer and includes a silicon semiconductor pattern overlapping the first region. A second thin-film transistor is disposed on the inorganic layer and includes an oxide semiconductor pattern overlapping the first region. Insulating layers overlap the first and second regions. An upper opening is formed within the insulating layers. A signal line electrically connects the second thin-film transistor. An organic layer overlaps the first and second regions and is disposed in the lower and upper openings. A luminescent device is disposed on the organic layer and overlaps the first region.