Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.

Abstract: Provided are an active-matrix substrate having a reliable line connection structure, a method for producing the same, and a display device including the same. A first metal line 122 and a second metal line 125 are electrically connected via an IGZO layer 124 rendered conductive. In this case, the second metal line 125 is isolated from an ITO layer 109 without contacting the ITO layer 109 because there are a passivation layer 107 and an organic insulating film 108 formed between the second metal line 125 and the ITO layer 109. Thus, no contact fault due to electric corrosion occurs between an aluminum layer 125a of the second metal line 125 and the ITO layer 109, whereby a reliable line connection structure is achieved.

Abstract: The array substrate includes: a substrate; a gate electrode; a gate insulating layer; an active layer; a source-drain electrode; a passivation layer; a pixel electrode; the active layer includes a first silicon layer, and the first silicon layer disposed below the channel is composed of polycrystalline silicon, and the remaining part of the first silicon layer is composed of amorphous silicon.

Abstract: A method for producing at least one optoelectronic semiconductor component and an optoelectronic semiconductor component are disclosed. In an embodiment, the method includes providing a semiconductor layer sequence comprising a first semiconductor material configured to emit a first radiation and applying a conversion element at least partially on the semiconductor layer sequence via a cold method, wherein the conversion element comprises a second semiconductor material, and wherein the second semiconductor material is configured to convert the first radiation into a second radiation.

Abstract: A display panel includes a substrate, a display element, a plurality of pixels arranged in a matrix, a drive circuit that drives the display element, a switching transistor in each of the plurality of pixels and selectively performs switching on the pixel that is to be caused to emit light, a first drive transistor in each of the plurality of pixels and drives a light-emitting element in the pixel, and a second drive transistor in the drive circuit. The switching transistor that is in each of the plurality of pixels, the first drive transistor that is in each of the plurality of pixels, and the second drive transistor in the drive circuit include oxide semiconductors. The switching transistor in each of the plurality of pixels and the second drive transistor in the drive circuit have a higher mobility than the first drive transistor in each of the plurality of pixels.

Abstract: A display panel includes a base layer including a first area and a second area. At least one inorganic layer disposed on the base layer overlaps the first area and the second area. The at least one inorganic layer comprises a lower opening. A first thin-film transistor is disposed on the at least one inorganic layer. The first thin-film transistor includes a silicon semiconductor pattern. A second thin-film transistor is disposed on the at least one inorganic layer. The second thin-film transistor includes an oxide semiconductor pattern. A plurality of insulation layers overlap the first area and the second area. An upper opening extends from the lower opening. A signal line is electrically connected to the second thin-film transistor. An organic layer is disposed in the lower opening and the upper opening. A light emitting element is disposed on the organic layer.

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

Abstract: A micro light-emitting diode display device including a driving transistor and a micro light-emitting diode is provided. The driving transistor includes a substrate, a bottom gate, a gate insulator, a semiconductor layer, an etch stopper, a drain electrode, a source electrode, and an insulating layer. The drain electrode is ring-shaped and a contact portion between the drain electrode and the semiconductor layer surrounds the semiconductor layer. The source electrode is in contact with the semiconductor layer and is enclosed by the drain electrode. The insulating layer has a via therein to expose a portion of the source electrode. The micro light-emitting diode is electrically connected to the source electrode. The micro light-emitting diode includes a current injection channel present in the micro-light emitting diode. The current injection channel is separated from a side surface of the micro light-emitting diode.

Abstract: A semiconductor device including a highly reliable transistor is provided. A semiconductor device includes a transistor. The transistor includes first and second gate electrodes, first and second gate insulators, a source electrode, a drain electrode, first to sixth oxides, first and second layers, and first and second gate insulators. The third oxide is under the source electrode. The fourth oxide is under the drain electrode. The sixth oxide is under the second gate electrode. The third and fourth oxides each have a function of supplying oxygen to the second oxide. The sixth oxide has a function of supplying oxygen to the second gate insulator.

Abstract: In a semiconductor device (MISFET) having a gate electrode formed over a nitride semiconductor layer with a gate insulating film interposed therebetween, the gate insulating film includes a first gate insulating film (oxide film of first metal) formed on the nitride semiconductor layer and a second gate insulating film (oxide film of second metal). The second metal (for example, Hf) has electronegativity lower than that of the first metal (for example, Al). Since the electronegativity of the second metal is lower than that of the first metal, negative charge is introduced into the oxide film of the first metal due to interfacial polarization, so that the flat-band voltage can be shifted in a positive direction. Accordingly, the threshold voltage which has become negative due to the heat treatment of the oxide film of the first metal can be shifted in the positive direction.

Abstract: A pixel structure includes a substrate, a thin film transistor and a common electrode. The thin film transistor is disposed on the substrate, wherein a semiconductive active layer of the thin film transistor has a channel region disposed between a source and a drain, the channel region includes a main channel region and at least one sub channel region, a channel length of the main channel region is less than a channel length of the at least one sub channel region, and the channel length of the main channel region is equal to a minimum of a channel length of the channel region. The common electrode is disposed on the thin film transistor, and the common electrode overlaps at least a portion of the at least one sub channel region, wherein the common electrode has an opening exposing the main channel region.

Abstract: According to one embodiment, a semiconductor device includes a first gate electrode, a semiconductor layer, a first insulating layer, a second gate electrode, a second insulating layer, a third insulating layer, a first contact hole, and a first electrode. The first electrode passes through the first contact hole and electrically connects the first gate electrode, the first region and the second gate electrode.

Abstract: An array substrate and a method for manufacturing the same, a display panel and a display device are provided. The array substrate includes a gate layer, a gate insulation layer, a source-drain layer, a first passivation layer and an ITO layer successively formed on a base substrate, a first through hole in the first passivation layer and a second through hole in the gate insulation layer, and a second passivation layer; and a part of the second passivation layer is arranged in the first and second through holes to cover a part of the ITO layer in the first through hole and the second through hole.

Abstract: To provide an input device and an input/output device with high detection sensitivity. The input device includes a first transistor, a second transistor, a capacitor, a node, a first wiring, a second wiring, a third wiring, and a fourth wiring. The first transistor includes a first gate and a second gate. The first and second gates of the first transistor overlap with each other with a semiconductor film therebetween. The second gate of the first transistor is electrically connected to the node. The first wiring is electrically connected to the second wiring through the first transistor. The third wiring is electrically connected to the node through the second transistor. A first terminal of the capacitor is electrically connected to the node, and a second terminal of the capacitor is electrically connected to the fourth wiring.

Abstract: Switches for electromagnetic radiation, including radiofrequency switches and optical switches, are provided. Also provided are methods of using the switches. The switches incorporate layers of high quality VO2 that are composed of a plurality of connected crystalline VO2 domains having the same crystal structure and orientation.

Abstract: Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.

Abstract: A display unit includes a first substrate, a transistor, first and second wiring layers, and an insulating film. The first substrate is provided with a display region and a peripheral region. The transistor is provided in the display region, and includes a semiconductor layer, a gate electrode facing the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and a source-drain electrode electrically coupled to the semiconductor layer. The first wiring layer is provided in the peripheral region, electrically coupled to the transistor, and disposed closer to the first substrate than the same layer as the gate electrode and the source-drain electrode. The second wiring layer is provided on the first substrate and has an electric potential different from the first wiring layer. The insulating film is provided between the second wiring layer and the first wiring layer.

Abstract: A method of fabricating a thin-film transistor is provided. In the method, an oxide semiconductor layer is formed above a substrate. A gate insulating layer is formed above the oxide semiconductor layer. A gate electrode is formed above the gate insulating layer. A metal oxide layer is formed on the oxide semiconductor layer by reactive sputtering to reduce a resistance of the oxide semiconductor layer in a region in contact with the metal oxide layer.

Abstract: According to an embodiment, a semiconductor device includes a plurality of first interconnections, a plurality of gate dielectric films, and a plurality of second interconnections. The plurality of first interconnections are oxide semiconductors formed in parallel at predetermined intervals in a first direction. The plurality of gate dielectric films are formed on surfaces of the first interconnections, respectively. The plurality of second interconnections are conductors formed at predetermined intervals in parallel to a second direction orthogonal to the first direction, respectively, to bridge over the gate dielectric films.

Abstract: A thin film transistor array panel includes a substrate, a gate insulating layer, an interface layer, and a semiconductor layer. The gate insulating layer is disposed on the substrate. The interface layer is disposed on the gate insulating layer. The semiconductor layer is disposed on the interface layer. The interface layer includes a fluorinated silicon oxide. The semiconductor layer includes a p-type oxide semiconductor material.

Abstract: The present invention provides a manufacture method and a structure of an oxide thin film transistor. The manufacture method of the structure of the oxide thin film transistor comprises providing a carrier; forming an oxide semiconducting layer (4); forming an etching stopper layer (5); forming two vias (51, 53) in the etching stopper layer (5) to expose the oxide semiconducting layer (4); removing a skin layer of the oxide semiconducting layer (4) in the two vias (51, 53) to form two recesses (41, 43) respectively connecting the two vias (51, 53); forming a source (61) and a drain (63) on the etching stopper layer (5), and the source (61) fills one via (51) and the recess (41) connecting therewith, and the drain (63) fills the other via (53) and the recess (43) connecting therewith; performing a post process.

Abstract: Provided is a technique of causing less display irregularities to occur when the scanning of the gate lines is resumed in a display device in which the scanning of gate lines is performed intermittently. A display device includes a display panel, and a driving circuitry that includes a plurality of drive circuits for scanning gate lines. The driving circuitry alternately switches a scanning period in which the gate lines are scanned, and a non-scanning period in which the scanning of the gate lines is suspended, during one vertical scanning period, according to a control signal. Each driving circuit 301n includes a first switching element N that applies a selection voltage to the gate line; an internal line netA; a second switching element A that charges the internal line netA to a first potential; and a third switching element B that includes a drain electrode connected to the internal line netA, and a source electrode having a second potential that is lower than the first potential.

Abstract: To provide a novel resistor. To provide a display device having a novel structure that can improve its reliability. To provide a display device having a novel structure that can reduce electrostatic discharge damages. The resistor includes a semiconductor layer and an insulating layer formed over the semiconductor layer, and the semiconductor layer is an oxide represented by an In-M-Zn oxide that contains at least indium (In), zinc (Zn), and M (M is a metal such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) and the insulating layer contains at least hydrogen.

Abstract: An organic light emitting diode display device comprises a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on the first semiconductor layer. The device further includes a storage capacitor including a first capacitor electrode electrically coupled to a drain electrode of the driving thin film transistor, a buffer layer formed on the first capacitor electrode, a second semiconductor layer formed on the buffer layer, and a second capacitor electrode formed on the second semiconductor layer and electrically coupled to a gate electrode of the driving thin film transistor. The device also includes an organic light emitting diode connected to the drain electrode of the driving transistor. The gate insulating layer has at least one hole in a region where the gate insulating layer overlaps the second semiconductor layer, thereby exposing the second semiconductor layer to the second capacitor electrode.

Abstract: An organic light-emitting display device comprises a first thin-film transistor disposed on a substrate; and a second thin-film transistor disposed on the substrate and spaced apart from the first thin-film transistor. The first thin-film transistor comprises a first semiconductor layer, a first conductive layer disposed on the first semiconductor layer and that overlaps the first semiconductor layer, and a first insulating layer disposed between the first semiconductor layer and the first conductive layer. The second thin-film transistor comprises a second semiconductor layer, and a second conductive layer disposed on the second semiconductor layer and that overlaps the second semiconductor layer.

Abstract: A display panel includes a base substrate. A semiconductor layer is disposed on the base substrate. A source electrode and a drain electrode are disposed on the semiconductor layer. A first insulating layer is disposed on both the source electrode and the drain electrode. A data line is disposed on the first insulating layer. The data line is electrically connected to the source electrode via a contact hole penetrating through the first insulating layer.

Abstract: The light-emitting device includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a light-emitting element and a thin-film transistor controlling the light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the thin-film transistor and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the light-emitting element and the thin-film transistor.

Abstract: A display panel comprises a first substrate, a second substrate, a display layer and transistors. One of the transistors includes a gate electrode disposed on the base plate, a first insulating layer disposed on the gate electrode, an active layer disposed on the first insulating layer, and a source electrode and a drain electrode disposed on the active layer, wherein the active layer includes a channel region between the source electrode and the drain electrode. At least one of the source and drain electrodes includes a first conductive layer disposed on the active layer, and a second conductive layer disposed on and contacting the first conductive layer, wherein the second conductive layer exposes a portion of top surface of the first conductive layer so that the first conductive layer possesses a first protrusion portion protruding from the edge of the second conductive layer and extending towards the channel region.

Abstract: A highly reliable semiconductor device capable of retaining data for a long period is provided. The transistor includes a first gate electrode, a first gate insulator over the first gate electrode, a first oxide and a second oxide over the first gate insulator, a first conductor over the first oxide, a second conductor over the second oxide, a third oxide covering the first gate insulator, the first oxide, the first conductor, the second oxide, and the second conductor, a second gate insulator over the third oxide, and a second gate electrode over the second gate insulator. An end portion of the second gate electrode is positioned between an end portion of the first conductor and an end portion of the second conductor in a channel length direction.

Abstract: A capacitor structure includes a first electrode plate disposed on a substrate, a first capacitor dielectric layer disposed on the first electrode plate, and a second electrode plate disposed on the first capacitor dielectric layer. A portion of the first electrode plate extends beyond an end of the second electrode plate to form a step. The capacitor structure also includes an etching stop layer, an inter-metal dielectric layer, a first via and a second via. The etching stop layer is disposed on the second electrode plate. The inter-metal dielectric layer covers the etching stop layer, the second electrode plate, the first capacitor dielectric layer and the first electrode plate. The first via penetrates through the inter-metal dielectric layer to contact the first electrode plate at the portion extending beyond the second electrode plate. The second via penetrates through the inter-metal dielectric layer to contact the second electrode plate.

Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.

Abstract: A novel amorphous oxide applicable, for example, to an active layer of a TFT is provided. The amorphous oxide comprises microcrystals.

Abstract: A method for manufacturing a thin-film transistor is disclosed, which includes forming an active layer over a substrate, and performing oxidation treatment to a channel region of the active layer for controlling a carrier concentration in the channel region of the active layer. The active layer having a high carrier concentration is directly formed, and the oxidation treatment can be configured to reduce a carrier concentration of the channel region of the active layer to a level where a gating property of the thin-film transistor is still maintained. In the thin-film transistor manufactured thereby, there is a relatively small contact resistance between a source electrode and a source electrode region of the active layer and between the drain electrode and the drain electrode region of the active layer.

Abstract: An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

Abstract: A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern.

Abstract: A semiconductor device with reduced parasitic capacitance is provided. A stack is formed on an insulating layer, the stack comprising a first oxide insulating layer, an oxide semiconductor layer over the first oxide insulating layer, and a second oxide insulating layer are formed on the second oxide insulating layer, a first low-resistance region is formed by adding a first ion to the second oxide semiconductor layer using the gate electrode layer as a mask; a sidewall insulating layer is formed on an outer side of the gate electrode layer; a second conductive layer is formed over the gate electrode layer, the sidewall insulating layer, and the second insulating layer; and an alloyed region in the second oxide semiconductor layer is formed by performing heat treatment.

Abstract: The present disclosure relates to a display unit and a method of producing the same, and a display panel. In an embodiment, the display unit comprises: a substrate; an electroluminescent unit on the substrate; and at least one magnetic layer on the substrate, wherein the electroluminescent unit is in a magnetic field of the magnetic layer.

Abstract: An object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film.

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers.

Abstract: A thin-film transistor is disclosed. The thin-film transistor includes a gate electrode disposed on a substrate, an oxide semiconductor layer disposed so as to overlap at least a portion of the gate electrode in the state of being isolated from the gate electrode, a gate insulation film disposed between the gate electrode and the oxide semiconductor layer, a source electrode connected to the oxide semiconductor layer, and a drain electrode connected to the oxide semiconductor layer in the state of being spaced apart from the source electrode, wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O), the content of indium (In) in the oxide semiconductor layer is greater than the content of gallium (Ga), the content of indium (In) is substantially equal to the content of zinc (Zn), and the content ratio (Sn/In) of tin (Sn) to indium (In) is 0.1 to 0.25.

Abstract: Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 ?m is 1 aA or less.

Abstract: A semiconductor device includes a first conductor; a first insulator thereover; a first oxide thereover; a second oxide thereover; a second conductor and a third conductor that are separate from each other thereover; a third oxide over the first insulator, the second oxide, the second conductor, and the third conductor; a second insulator thereover; a fourth conductor thereover; and a third insulator over the first insulator, the second insulator, and the fourth conductor. The second oxide includes a region where the energy of the conduction band minimum of an energy band is low and a region where the energy of the conduction band minimum of the energy band is high. The energy of the conduction band minimum of the third oxide is higher than that of the region of the second oxide where the energy of the conduction band minimum is low. Side surfaces of the first oxide and the second oxide are covered with the third oxide.

Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT including an oxide semiconductor layer supported by the substrate and having a multilayer structure including a protective oxide semiconductor layer and a channel oxide semiconductor layer disposed closer to the substrate than the protective oxide semiconductor layer, an upper insulating layer on the oxide semiconductor layer, an upper gate electrode disposed on the upper insulating layer, an interlayer insulating layer covering the oxide semiconductor layer and the upper gate electrode, and first and second electrodes electrically connected to the oxide semiconductor layer, wherein a first opening extends through at least the interlayer insulating layer and the protective oxide semiconductor layer, and exposes a portion of the channel oxide semiconductor layer, and the first electrode is disposed on the interlayer insulating layer and within the first opening, and is in direct contact with, within the first opening, the portion.

Abstract: A highly flexible display device and a method for manufacturing the display device are provided. A transistor including a light-transmitting semiconductor film, a capacitor including a first electrode, a second electrode, and a dielectric film between the first electrode and the second electrode, and a first insulating film covering the semiconductor film are formed over a flexible substrate. The capacitor includes a region where the first electrode and the dielectric film are in contact with each other, and the first insulating film does not cover the region.

Abstract: A display device includes: a flexible substrate; a pixel over the flexible substrate, the pixel including a transistor and a display element; a first wiring for transmitting a signal to the pixel, the first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; an inorganic insulating layer on a higher level than the first wiring or the second wiring; and an organic insulating layer on a higher level than the inorganic insulating layer, wherein the inorganic insulating layer has an opening exposing a part of the upper surface of the first wiring or the second wiring is exposed, and the organic insulating layer is provided in such a way as to fill the opening.

Abstract: The present application provides a graphene light emitting transistor, including: a gate electrode disposed on a substrate; a gate insulating layer disposed on the substrate and the gate electrode; a source electrode and a drain electrode disposed on the gate insulating layer, wherein the source electrode and the drain electrode are formed by graphene; a graphene oxide layer disposed on the gate insulating layer and located between the source electrode and the drain electrode; a graphene quantum dot layer disposed on the graphene oxide layer, the source electrode and the drain electrode; and a water and oxygen resistant layer disposed on the graphene quantum dot layer. The present application also provides a method of fabricating the graphene light emitting transistor and an active graphene light emitting display apparatus having the graphene light emitting transistor.

Abstract: Disclosed are a thin film transistor and a display device including the thin film transistor. The thin film transistor comprises: a bottom gate electrode on a substrate; a semiconductor layer overlapping with the bottom gate electrode, wherein the semiconductor layer comprises a N-type semiconductor layer and a P-type semiconductor layer, and the N-type semiconductor layer is overlapped partly with the P-type semiconductor layer; a first source electrode and a first drain electrode respectively connected to the P-type semiconductor layer; a second source electrode and a second drain electrode respectively connected to a portion of the N-type semiconductor layer which is not overlapped with the P-type semiconductor layer; and a top gate electrode above the semiconductor layer. According to the embodiment of the present disclosure, a complexity of a manufacturing process of the thin film transistor is reduced.

Abstract: The present technology relates to an imaging device, a manufacturing device, and a manufacturing method capable of preventing a substance such as hydrogen from entering and preventing change in performance. The imaging device includes an organic photoelectric conversion film, an upper electrode provided in an upper portion of the organic photoelectric conversion film, a lower electrode provided in a lower portion of the organic photoelectric conversion film, and a metal thin film provided between the organic photoelectric conversion film and the upper electrode or between the organic photoelectric conversion film and the lower electrode. The metal thin film is provided between the organic photoelectric conversion film and the upper electrode. The upper electrode is formed of an oxide semiconductor, a metal oxide, and the metal thin film. The present technology can be applied to a vertical spectral imaging device.

Abstract: There are provided a method of manufacturing a display substrate, a method of manufacturing a display device, and a display substrate. The method of manufacturing a display substrate comprises: providing a base substrate; forming a thin film transistor on the base substrate; forming a first conductive layer on the base substrate on which the thin film transistor is formed, the first conductive layer being electrically connected to a drain of the thin film transistor; forming a light-emitting material block; and transferring the light-emitting material block to a surface of the first conductive layer.