Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.

Abstract: A semiconductor device comprises: a GaAs substrate; a buffer layer provided on the GaAs substrate; a laminated structure provided on the buffer layer; a Schottky contact layer provided on the laminated structure; a n-type Inx(Ga1−yAly)1−xP layer provided on the Schottky contact layer; a n-type Inu2Ga1−u2As ohmic contact layer provided on the n-type Inx(Ga1−yAly)1−P layer; a gate electrode provided on the Schottky contact layer; and a source electrode and a drain electrode provided on the ohmic contact layer. The buffer layer is made of a semiconductor, and at least a part of the semiconductor has a lattice constant larger than a lattice constant of GaAs. The channel layer is made of Inu1Ga1−u1As, and the electron supply layer is made of n-type Inv1Al1−v1As. At least a part of the Schottky contact layer is made of non-doped Inv2Al1−v2As.

Abstract: A preferred embodiment of the present invention provides a Schottky diode formed from a conductive anode contact, a semiconductor junction layer supporting the conductive contact and a base layer ring formed around at least a portion of the conductive anode contact. In particular, the base layer ring has material removed to form layer material gap (e.g., a vacuum gap) adjacent to the conductive anode contact. A dielectric layer is also provided to form one boundary of the base layer material gap.

Abstract: A power semiconductor device includes a substrate of first conductivity having a dopant concentration of a first level. The substrate is a group III-V compound material. A transitional layer of first conductivity is epitaxially grown over the substrate. The transitional layer has a dopant concentration of a second level and is a group III-V compound material. An epitaxial layer of first conductivity is grown over the transitional layer and has a dopant concentration of a third level. Electrical currents flow through the transitional and epitaxial layers when the device is operating.

Abstract: A local oscillation FET has a source connecting pad, a drain connecting pad and a gate connecting pad. The source connecting pad occupies one corner of a substrate, and the drain and gate connecting pads are placed at the neighboring corners so that the three connecting pads form an L shape on the substrate. As a modification to this configuration, another source connecting pad is placed at the remaining corner of the substrate so that the drain and gate connecting pads are shielded from each other by the two source connecting pads. These device configurations contribute to size reduction of the local oscillation FET.

Abstract: A Schottky barrier field effect transistor has a gate electrode formed with a field plate in order to achieve a high withstanding voltage, where the thickness of the dielectric layer between the channel layer and the field plate, the distance between the Schottky contact and the drain and the length of the field plate falls within the range of 300 nanometers to 600 nanometers thick, the range from 800 nanometers to 3000 nanometers long and the range of the distance between the Schottky contact and the drain is plus or minus 400 nanometers, respectively, so that the distortion and the return-loss are improved without sacrifice of the withstanding voltage.

Abstract: SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs.

Abstract: The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source of at least one transistor of a field effect transistor integrated circuit. The use of one or more Schottky barriers is useful for reducing the susceptibility of latch-up for circuits having two opposite type transistors, i.e., two opposite polarity carriers, in which the two transistors are in close enough proximity to experience latch-up. This can allow the spacing between n- and p-type transistors to be reduced, thus reducing the area of the circuit. The subject invention can also allow the elimination of a metal contact by utilizing the metal layer used to form the metal-semiconductor junction in a complementary IGFET structure, to further reduce the circuit area. The subject invention is applicable to complementary metal oxide silicon (CMOS) devices.

Abstract: A preferred embodiment of the present invention provides a Schottky diode (100) formed from a conductive anode contact (102), a semiconductor junction layer (104) supporting the conductive contact (102) and a base layer ring (108) formed around at least a portion of the conductive anode contact (102). In particular, the base layer ring (108) has material removed to form a base layer material gap (118) (e.g., a vacuum gap) adjacent to the conductive anode contact (102). A dielectric layer (110) is also provided to form one boundary of the base layer material gap (118).

Abstract: A Schottky diode that achieves a predetermined reverse-direction breakdown voltage even if a state of a surface in a vicinity of a Schottky junction interface changes due to a welding of a bonding wire. The semiconductor device having the Schottky junction includes a semiconductor substrate of a first conductivity type. A well region of a second conductivity type is formed in a top surface of the semiconductor substrate. A Schottky electrode is formed on the top surface of the semiconductor substrate. A connecting conductive member is electrically connected to the Schottky electrode. The connecting conductive member is selectively connected to the Schottky electrode above the well region such that a connection surface between the connecting conductive member and the Schottky electrode is not extended above a Schottky junction between the Schottky electrode and the semiconductor substrate of the first conductivity type.

Abstract: An integrated semiconductor circuit, in particular a semiconductor memory circuit, having at least one integrated electrical antifuse structure is described. The antifuse structure is located within an insulated well composed of semiconductor material.

Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof. The field effect transistor semiconductor of this invention comprises a source/drain electrode 6 positioned in a predetermined position in a GaAs substrate 1, a channel region provided in the GaAs substrate 1 and between the source/drain electrodes 6, a gate electrode 11 which is in schottky contact with a part of a channel region and is positioned between the source/drain electrodes 6, and an insulating film 7 which electrically insulates a surface of the GaAs substrate and the gate electrode 11 at both side surfaces of the gate electrode 11.

Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.

Abstract: This disclosure describes one-chip micro-integrated optoelectronic sensors and methods for fabricating and using the same. The sensors may include an optical emission source, optical filter and a photodetector fabricated on the same transparent substrate using the same technological processes. Optical emission may occur when a bias voltage is applied across a metal-insulator-semiconductor Schottky contact or a p-n junction. The photodetector may be a Schottky contact or a p-n junction in a semiconductor. Some sensors can be fabricated on optically transparent substrate and employ back-side illumination. In the other sensors provided, the substrate is not transparent and emission occurs from the edge of a p-n junction or through a transparent electrode. The sensors may be used to measure optical absorption, optical reflection, scattering or fluorescence.

Abstract: A semiconductor module includes a semiconductor chip, a lead frame having lead fingers, and a down set member within an encapsulant for reduce warpage and providing a more planar package by balancing thermal stress between the lead fingers and the encapsulant. The down set member can be a bent portion of the lead frame. It can also be a separate body, such as a dummy semiconductor chip.

Abstract: On an In-containing compound semiconductor are sequentially formed Zn (p-type dopant-containing layer), Ta (high-melting metal layer) and a low-resistance conductor layer in this order as a Schottky electrode, and the resulting assemblage is annealed to diffuse Zn into the semiconductor to thereby convert the surface of the semiconductor layer only in a region in contact with the Schottky electrode metal into a p-type layer. The p-type dopant-containing layer can be, instead of Zn, a compound between Zn and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy. The high-melting metal layer can be, instead of Ta, an intermetallic compound between Ta and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy.

Abstract: A compound semiconductor device includes a cap layer formed on a channel layer and an insulating film formed on the cap layer, and a &Ggr;-shaped gate electrode is provided in a gate recess opening, wherein an extension part of the &Ggr;-shaped gate electrode extends over the insulating film toward a drain electrode, and the total thickness of the insulating film and the cap layer being is set such that the electric field formed right underneath the extension part of the gate electrode includes a component acting in a direction perpendicular to the substrate.

Abstract: This patent is generally directed towards a method and device for providing a diode structure that has a barrier height that may be readily engineered with a series resistance that may be independently varied while simultaneously providing for the complete characterization and discernment of the barrier height in a microwave and millimeter-wave rectifying diode without the need for device fabrication and electrical measurement. The present invention generally relates to microwave and millimeterwave diodes, and more particularly to low barrier structures within these diodes that are capable of rectification of microwave and millimeterwave radiation.

Abstract: A high-speed, soft-recovery semiconductor device that reduces leakage current by increasing the Schottky ratio of Schottky contacts to pn junctions. In one embodiment of the present invention, an n− drift layer is formed on an n+ cathode layer 1 by epitaxial growth, and ring-shaped ring trenches having a prescribed width are formed in the n− drift layer. Oxide films are formed on the side walls of each ring trench. The ring trenches are arranged such that the centers of the rings of the ring trenches adjacent to one another form a triangular lattice unit. A p− anode layer is formed at the bottom of each ring trench. Schottky contacts are formed at the interface between an anode electrode and the surface of the n− drift layer. Ohmic contact is established between the surfaces of polysilicon portions and the anode electrode.

Abstract: An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.

Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: The invention relates to a semiconductor component with adjacent Schottky (5) and pn (9) junctions positioned in a drift area (2, 10) of a semiconductor material. The invention also relates to a method for producing said semiconductor component.

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Abstract: A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.

Abstract: A microwave monolithic integrated circuit comprises a T-shaped gate electrode including a Schottky gate electrode formed on a first region of a compound semiconductor substrate, a pair of ohmic electrodes making an ohmic contact with a surface of the substrate in the first region at respective sides of the T-shaped gate electrode, a lower capacitor electrode pattern formed on a second region of the compound semiconductor substrate with a composition substantially identical with a low-resistance, top electrode constituting the T-shaped gate electrode on the Schottky gate electrode, a dielectric film formed on the lower electrode pattern, and an upper electrode pattern formed on the dielectric film.

Abstract: A switching device receives two pairs of balanced signals and outputs one of the two pairs of the signals. The device is composed of two SPDT switches which share two control signals provided to the gates of the FET of the SPDT switches. The package of the device has eight external electrodes on the back side of the package. The eight external electrodes are configured so that they are aligned symmetrically with respect to the center line of the package. The device requires only a small package space and is suitable for mobile communication application such as cell phone accommodating CDMA and GPS signals.

Abstract: On a semiconductor layer 1 consisting of a substrate of a semiconductor single crystal or the like, a metallic layer 2 of a thickness of 20 nm or less is formed. The metallic layer 2 comprises a first area A directly contacting with the semiconductor layer 1, and a second area B that is interposed by an intermediate layer 3 consisting of an insulator, a metal different from the metallic layer 2 or a semiconductor different from the semiconductor layer 1 between the semiconductor 1 and the metallic layer 2, and of a thickness of 10 nm or less. The first area and the second area are different in their Schottky currents, further in their Schottky barrier heights. Any one of the respective areas A and B has an area of nanometer level, and the respective interfaces in each of the areas A and B have an essentially uniform potential barrier, respectively. Such a film-like composite structure contributes to a minute semiconductor device of nanometer level and realization of a new functional device.

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Abstract: This patent is generally directed towards a method and device for providing a diode structure that has a barrier height that may be readily engineered with a series resistance that may be independently varied while simultaneously providing for the complete characterization and discernment of the barrier height in a microwave and millimeter-wave rectifying diode without the need for device fabrication and electrical measurement. The present invention generally relates to microwave and millimeterwave diodes, and more particularly to low barrier structures within these diodes that are capable of rectification of microwave and millimeterwave radiation.

Abstract: The invention relates to a semiconductor component which is capable of blocking such as an (IGBT), a thyristor, a GTO or diodes, especially schottky diodes. An insulator profile section (10a, 10b, 10c, 10d, 11) provided in the border area of an anode metallic coating (1, 31) is fixed (directly in the edge area) on the substrate (9) of the component. The insulator profile has a curved area (KB) and a base area (SB), said curved area having a surface (OF) which begins flat and curves outward and upward in a steadily increasing manner. A metallic coating MET1; 30a, 30b, 30c, 30d, 31b) is deposited on the surface (OF). Said coating directly follows the surface curvature and laterally extends the inner anode metallic coating. The upper end of the curved metallic coating (MET1; 30a, 30b . . . ) is distanced and insulated from one of these surrounding outer metallic coatings (MET2; 3) by the surrounding base area (SB) of the insulator profile (10a, . . .

Abstract: A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, a metal layer on the grooved surface and forming a Schottky junction with sidewalls of the grooved surface and ohmic contacts with top portions of the grooved surface. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body, and a plurality of doped regions at the bottom of grooves and forming P-N junctions with the semiconductor body. The P-N junctions of the doped regions form carrier depletion regions across and spaced from the grooves to increase the reverse bias breakdown voltage and reduce the reverse bias leakage current. The ohmic contacts of the metal layer increase forward current and reduce forward voltage of the Schottky diode.

Abstract: An indium layer sandwiched between palladium layers are treated with heat so that the indium is diffused into a p-type gallium arsenide, and is alloyed with the palladium, whereby the p-type indium gallium arsenide layer decreases a Schottky barrier between the p-type gallium arsenide and the palladium-indium alloy layer.

Abstract: A Schottky diode, and a method of making the same, which is fabricated on InP material and employs a Schottky layer including InxAl1−xAs with x>0.6, or else including a chirped graded supperlattice in which successive periods of the superlattice contain progressively less GaInAs and progressively more AlInAs, the increase in AlInAs being terminated before the proportion of AlInAs within the last period (adjacent the anode metal) exceeds 80%. Such fabrication creates an InP-based Schottky diode having a low turn-on voltage which may be predictably set within a range by adjusting the fabrication parameters.

Abstract: A Schottky barrier field effect transistor has a gate electrode formed with a field plate in order to achieve a high withstanding voltage, wherein the thickness of the dielectric layer between the channel layer and the field plate, the distance between the Schottky contact and the drain and the length of the field plate are to be fallen within the range between 300 nanometers thick to 600 nanometers thick, the range from 800 nanometers long to 3000 nanometers long and the range between the distance between the Schottky contact and the drain plus minus 400 nanometers, respectively, so that the distortion and the return-loss are improved without sacrifice of the withstanding voltage.

Abstract: An edge termination for a semiconductor component containing a semiconductor body formed of silicon carbide. The edge termination has at least one diode chain that is insulated from the semiconductor body and provided with a plurality of semiconductor layers having alternating conductivity types.

Abstract: A semiconductor device has an improved schottky barrier junction. The device includes: a substrate; an epitaxial layer covering the substrate and lightly doped with a dopant selected from a group consisting of a rare earth element and an oxidant of a rare earth element; and a metal layer covering the epitaxial layer and forming said schottky barrier junction with said epitaxial layer.

Abstract: In this invention, a new, simple and small-size hydrogen-sensitive palladium (Pd) membrane/semiconductor Schottky diode sensor has been developed and fabricated. First, a high quality undoped GaAs buffer layer and an n-type GaAs epitaxial layer with the carrier concentration of 2.times.10.sup.17 cm.sup.31 3 is grown by molecular beam epitaxy (MBE) on a semi-insulated GaAs substrate. Then a thin Pd membrane is evaporated on the surface of the n-type GaAs epitaxial layer by the vacuum evaporation technique. It is well-known that palladium metal has excellent selectivity and sensitivity on hydrogen gas. When hydrogen gas diffuses to the Pd membrane surface, the hydrogen molecules will dissociate into hydrogen atoms. Some of the hydrogen atoms diffuse through the thin metal layer and form the palladium hydride near the metal-semiconductor interface. The hydride may effectively lower the work function of Pd metal.

Abstract: The invention concerns the fabrication and characterization of vertical geometry transparent Schottky barrier ultraviolet detectors based on n.sup.- /n.sup.+ -GaN and AlGaN structures grown over sapphire substrates. Mesa geometry devices of different active areas were fabricated and characterized for spectral responsitivity, speed and noise characteristics. The invention also concerns the fabrication and characterization of an 8.times.8 Schottky barrier photodiode array on GaN with a pixel size of 200 .mu.m by 200 .mu.m.

Abstract: A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).

Abstract: A Schottky high power rectifier having a nitride insulator formed on the surface of a GaN substrate. The nitride insulator increases the electric field breakdown suppression at or near the surface of the rectifier below the insulator. In a preferred embodiment, the nitride insulator is an epitaxially grown aluminum nitride insulator.

Abstract: In a method for manufacturing a semiconductor device, an insulating layer is formed on a semiconductor substrate, and a refractory metal is formed layer on the insulating layer. Then, a first opening is perforated in the refractory metal layer, and a part of the insulating layer is etched by using the refractory metal as a mask. Then, a second opening is perforated in the refractory metal layer. The second opening is superposed onto the first opening and is larger than the first opening. Then, the insulating layer is again etched by using the refractory metal layer as a mask, so that a T-shaped opening is perforated in the insulating layer. Finally, a modified T-shaped gate metal electrode is formed on the insulating layer having the T-shaped opening.

Abstract: Group III-V composites, which is used to manufacture Schottky contacts having the characteristics of higher energy gap, higher carriers mobility, etc., are applied for manufacturing high-speed devices. Therefore, in there years, Group III-V composite Schottky contacts are continuously being developed. In the invention, the surface treatment of composite semiconductor is used for reduce a surface state and oxidation, thereby increased the Schottky barriers of the Group III-V composite (such as, GaAs, InP, InAs and InSb) Schottky contacts. During experiments, a phosphorus sulphide/ammonia sulphide solution and hydrogen fluoride solution are used for the surface treatment to increase the amount of sulphur contained on the surfaces of substrates, reduce the surface state and remove various oxides. Furthermore, ultra-thin and really stable sulphur fluoride/phosphorus fluoride layers having high energy gaps are formed on various substrates.

Abstract: A method for forming a Schottky diode structure is disclosed. The method includes the steps of: a) Providing a substrate; b) forming a rare-earth containing layer over the substrate; and c) forming a metal layer over the rare-earth containing layer. The Schottky diode structure with a rare-earth containing layer has the properties of high-temperature stability, high Schottky barrier height (SBH), and low reverse leakage current.

Abstract: A semiconductor device includes a gate structure formed on a substrate in which an LDD structure is formed, wherein gate structure includes a Schottky electrode making a Schottky contact with a channel region in the substrate, a low-resistance layer provided above the Schottky electrode, and a stress-relaxation layer interposed between the Schottky electrode and the stress-relaxation layer. The low-resistance layer and said stress-relaxation layer form an overhang structure with respect to the Schottky electrode.

Abstract: A compound semiconductor transistor has a structure in which a first insulating film is formed only under a overhang of a gate electrode an upper part of which is formed widely, and a second insulating film for threshold voltage adjustment is formed on the side of a gate electrode and the first insulating film.

Abstract: An enhancement mode periodic table group III-IV semiconductor field-effect transistor device is disclosed. The disclosed transistor includes single metallization for ohmic and Schottky barrier contacts, a permanent non photosensitive passivation layer (a layer which has also been used for masking purposes during fabrication of the transistor) and a gate element of small dimension and shaped cross section as needed to provide desirable microwave spectrum electrical characteristics. The transistor of the invention is fabricated from undoped semiconductor materials disposed in a layered wafer structure and selectively doped by ion implantation to achieve either a p-channel or an n-channel transistor. The semiconductor materials may include two, one or zero buffer layers in their layer structure. The disclosed transistor is of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Abstract: In a method for fabricating a semiconductor device, an insulating layer is formed on a semiconductor substrate, then a resist layer is formed on the insulating layer to have an opening therein. Next, removing the insulating layer at the bottom of the opening, then a reflow process is performed to the resist layer to have a curved surface thereon.

Abstract: An n-semiconductor layer is arranged on a low-resistance n-substrate. A drain electrode is in ohmic contact with the n-substrate. A source electrode forms a Schottky junction with the n-semiconductor layer. A gate electrode is arranged adjacent to the source electrode on the n-semiconductor layer through a gate insulating film. When a voltage is applied to the gate electrode to lower the Schottky barrier height at the interface between the source electrode and the n-semiconductor layer, electrons are injected from the source electrode into the n-semiconductor layer, and a current flows in the semiconductor device. A diffusion layer which prevents a decrease in manufacturing time is not required to form in the n-semiconductor layer, and a channel which causes an increase in ON state voltage is not present.

Abstract: A semiconductor diode structure with a Schottky junction, wherein a metal contact and a silicon carbide semiconductor layer of a first conducting type form the junction and wherein the edge of the junction exhibits a junction termination divided into a transition belt (TB) having gradually increasing total charge or effective sheet charge density closest to the metal contact and a Junction Termination Extension (JTE) outside the transition belt, the JTE having a charge profile with a stepwise or uniformly deceasing total charge or effective sheet charge density from an initial value to a zero or almost zero total charge at the outermost edge of the termination following a radial direction from the center part of the JTE towards the outermost edge of the termination.