Abstract: A heterojunction semiconductor device includes a first Schottky contact layer made of a first semiconductor, a second Schottky contact layer made of a second semiconductor and a metal electrode. The first Schottky contact layer, the second Schottky contact layer and the metal electrode are laminated in this order on a semiconductor substrate or on a main structure of a semiconductor device laminated on a semiconductor substrate from the substrate side or from the main structure side. The first Schottky contact layer serves as a barrier layer toward the second Schottky contact layer, and a layer thickness of the second Schottky contact layer is greater than the mean free pass of carriers in the second Schottky contact layer.

Abstract: A Schottky diode having a series of stacked layers starting with a conventional substrate having a semi-insulating GaAs layer and an un-doped GaAs buffer layer. An n-type Si--GaAs channel layer is grown on the GaAs buffer layer. A low-temperature-grown GaAs barrier layer covers the center portion of the upper surface of the n-type channel layer. The Schottky diode comprises two terminals. One diode terminal comprises a ohmic contact deposited on the upper surface of the channel layer. This ohmic contact, which is ring-shaped, encircles the barrier layer. The other diode terminal includes a metal layer that forms a Schottky contact with the upper surface of the barrier layer. The Ga-to-As ratio in the low-temperature-grown GaAs barrier layer is adjusted so that the barrier layer contains a sufficient number of free electrons to support current flow for bias voltages above the Schottky barrier height.

Abstract: A superconductor device comprises a Schottky barrier region S.sub.B for selectively passing injected carriers and a collector barrier region L.sub.B for selectively blocking leakage carriers. The Schottky barrier region is formed in a low permittivity region .epsilon..sub.L between the first operating region (B) made of superconductor material and the second operating region (C) made of either semiconductor material or metallic material. A resonance region R is formed in the low permittivity region .epsilon..sub.L.

Abstract: A semiconductor device has an improved schottky barrier junction. The device includes: a substrate; an epitaxial layer covering the substrate and lightly doped with a dopant selected from a group consisting of a rare earth element and an oxide of a rare earth element; and a metal layer covering the epitaxial layer and forming said schottky barrier junction with said epitaxial layer.

Abstract: A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.

Abstract: A MESFET structure (20) and a method that minimizes the effects of processing steps and device performance of the MESFET structure (20). The MESFET structure (20) has a gate (30) positioned over a channel region (28) and between a source region (36) and a drain region (34). The MESFET structure (20) further includes a hole injector region (32) formed near the channel region (28). The hole injector region (32) injects holes beneath the channel region (28) which decrease the ability of the trap sites to attract electrons generated by impact ionization. Thus, this supply of holes beneath the channel region (28) prevents the effects of IV-kink and hysteresis caused by electrons that are accumulated in the trap sites.

Abstract: In a semiconductor electron emission device for causing an avalanche breakdown by applying a reverse bias voltage to a Schottky barrier junction between a metallic material or metallic compound material and a p-type semiconductor, and externally emitting electrons from a solid-state surface, a p-type semiconductor region (first region) for causing the avalanche breakdown contacts a p-type semiconductor region (second region) for supplying carriers to the first region, and a semi-insulating region is formed around the first region.

Abstract: A FET including a channel region and a drift region in a channel layer with a source in the channel region and a drain in the drift region. The current channel between the source and drain defining a straight transistor portion and a curved transistor portion. An oxide with a thin portion overlying the channel region and a thick portion overlying the drift region, and a gate on the thin oxide overlying the current channel. A drain field plate and a gate field plate on the thick oxide with spaced apart edges and a damaged region underlying the edges of the field plates only in the curved transistor portion to reduce electric fields at the edges of the field plates. Also, the current channel has a greater length and the edges are spaced apart farther in the curved transistor portions.

Abstract: A metal-semiconductor type field effect transistor has a Y-letter shaped gate electrode standing on an active layer, and the Y-letter shaped gate electrode prevents piezoelectric charges induced beneath both ends of the wing portions thereof from undesirable merger so as to restrict variation of the threshold regardless of the orientation of the Y-letter shaped gate electrode.

Abstract: A periodic table group III-IV HEMT/PHEMT field-effect transistor device and its fabrication is described. The disclosed fabrication arrangement uses a single metallization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non photoresponsive secondary mask element affording several practical advantages during fabrication and in the completed transistor. The invention includes provisions for both an all-optical lithographic fabrication process and a combined optical and electron beam lithographic process. These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Abstract: A periodic table group III-IV field-effect transistor device is described. The disclosed device uses a single metalization for ohmic and Schottky barrier contacts, permanent plural etch stop layers, employs a non-alloyed ohmic connection semiconductor layer and includes a permanent semiconductor material-comprised secondary mask element, a mask element which can be grown epitaxially during wafer fabrication to perform useful functions in both the device processing and device utilization environments. The device of the invention may be achieved with both an all optical lithographic process and a combined optical and electron beam lithographic process The disclosed device provides a field-effect transistor of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Abstract: A silicon carbide trench MOSFET is provided that includes a first conductivity type semiconductor substrate made of silicon carbide. A first conductivity type drift layer and a second conductivity type base layer, both made of silicon carbide, are sequentially formed by epitaxial growth on the semiconductor substrate. The first conductivity type drift layer has a lower impurity concentration than the semiconductor substrate. A first conductivity type source region is formed in a part of a surface layer of the second conductivity type base layer. A gate electrode is received through an insulating film, in a first trench extending from a surface of the first conductivity type source region to reach the first conductivity type drift layer. A Schottky electrode disposed on an inner surface of a second trench having a greater depth than the first trench.

Abstract: In a Schottky barrier diode, concentration of an electrical field at an edge of an insulation layer is suppressed to improve the reverse breakdown voltage. An n- layer of a compound semiconductor substrate having an n+ layer and the n- layer is configured in the form of a mesa. An insulation layer is formed on at least a skirt portion and a slant portion of the mesa. An anode is formed on the insulation layer and n- layer, and a cathode is formed on the n+ layer. Thus, concentration of an electrical field at an edge of the insulation layer is canceled at least in part by an electrical field generated at the anode on the slant portion to improve the reverse breakdown voltage.

Abstract: A semiconductor device includes a semi-insulating semiconductor substrate, a semiconductor layer structure including at least an undoped layer of a first semiconductor, an undoped spacer layer of a second semiconductor having an electron affinity smaller than that of the first semiconductor, and an n type electron supply layer of the second semiconductor successively laminated on the substrate, the undoped layer having a flat top surface and a flat rear surface on the flat top surface of the undoped spacer layer, having, at a top surface, a concavo-convex periodic structure, and a flat rear surface, the n-type electron supply layer of the second semiconductor having a flat top surface and a rear surface that buries concavities of the concavo-convex structure of the undoped spacer layer, and a plurality of periodically arranged Schottky electrodes on the flat top surface of the n type electron supply layer, arranged in a direction perpendicular to the concavo-convex periodic structure of the undoped spacer lay

Abstract: A Schottky barrier diode having improved breakdown characteristics has an n.sup.+ semiconductor layer and an n.sup.- semiconductor layer provided on the n.sup.+ semiconductor layer. The n.sup.- semiconductor layer is configured to form a mesa. An insulating layer is formed so as to expose the upper surface of the mesa. An anode electrode is provided on the exposed surface and a side surface of the mesa, while a cathode is electrically connected to the n.sup.+ layer. A plasma treated layer is provided in the n.sup.- semiconductor layer so as to extend inwardly from at least a portion of the side surface of the mesa.

Abstract: It is suggested for a metal-semiconductor diode that the depletion zone layer be grown epitaxially from deformed In.sub.x Ga.sub.1-x As with an indium content x increasing in the direction of the metal contact and/or that a diode area be delimited by surrounding insulation regions in a planar design consisting of a flat layer sequence and that the metal contact be provided on the surface of the layer sequence. Corresponding advantageous manufacturing processes are described.

Abstract: A new Schottky diode structure, Pt/Al/n-InP, is disclosed in the present invention. The thickness of Al layer of the Schottky diode structure is restricted in a range of about 80-120 .ANG.. This structure gives a barrier height of 0.74 eV and an ideality factor of 1.11 after it was annealed at 300.degree. C. for 10 min. This is due to the formation of Aluminum-oxide, as the interfacial layer to improve barrier height. A method of preparing this Schottky diode structure is also disclosed in the present invention.

Abstract: A field effect group III-V compound semiconductor device having a Schottky gate electrode includes: a semiconductor substrate; a plurality of group III-V compound semiconductor crystal layers including an active layer for transferring carriers and formed on the semiconductor substrate; an InAlP layer formed at least a partial surface of the group III-V compound semiconductor crystal layers; a gate electrode formed on the InAlP layer and forming Schottky contact therewith; and a pair of source/drain electrodes disposed to interpose therebetween the gate electrode, and forming ohmic contact with the active layer. A group III-V compound semiconductor device is provided with a Schottky electrode highly resistant to a current flow.

Abstract: To provide a Schottky junction device having a super-lattice arranged in the Schottky interface in order to secure a high Schottky barrier and at the same time showing a high speed response by resolving the phenomenon of piled-up holes at the upper edge of the valence band, while maintaining the height of the Schottky barrier. A Schottky junction device having a Schottky junction of a semiconductor and a metal and a superlattice on the interface of the semiconductor and the metal, wherein the upper edge of the valence band of said superlattice is varied to show a turn to a specific direction. The phenomenon of hole-piling up at the upper end of the valence band is resolved while maintaining the height of the Schottky barrier and consequently such a Schottky junction device shows an excellent high speed response.

Abstract: A Schottky gate electrode of a refractory metal silicide is formed on a compound semiconductor, by which the barrier height is maintained satisfactorily even after heat treatment above 800.degree. C. Accordingly, it is possible to form an impurity diffused region using the Schottky gate electrode as a mask and then to effect the recrystallization of the semiconductor or the activation of the impurity by heat treatment, so that source and drain regions can be positioned by self-alignment relative to the gate electrode.

Abstract: A high speed diode with a low forward-bias turn-on voltage is formed by a heterojunction between a layer of doped semiconductor material that has a narrow bandgap energy of not more than about 0.4 eV, and a layer of oppositely doped semiconductor material that has a substantially wider bandgap energy. The device operates with a lower turn-on voltage than has previously been attainable, despite lattice mismatches between the two materials that can produce strain and substantial lattice dislocations in the low bandgap material. The two materials are selected so that the valence and conduction band edge discontinuities at the heterojunction enable a forward carrier flow but block a reverse carrier flow across the junction under forward-bias conditions. Preferred material systems are InAs for the narrow bandgap material, InGaAs for the wider bandgap material and InP for the substrate, or AlSb for the wider bandgap material and GaSb for the substrate.

Abstract: A sensing transducer (10,30) and a method therefor uses a Schottky junction (12) having a conductive layer (16) disposed on a semiconductor substrate (14). The conductive layer (16) is generally formed from the reaction of a metal with a portion of the semiconductor substrate (14). One example of the conductive layer (16) is a metal silicide layer. In one pressure sensing approach, a substantially constant reverse current (I.sub.1) is applied to the Schottky junction (12). The change in reverse output voltage of the junction (12) is proportional to the change in pressure on the junction (12) itself, and can thus be used to sense pressure. This output voltage change is significantly higher than that achieved with prior pressure transducers and permits the output signal of the transducer (10,30) according to the present invention to be substantially used without extra amplification or other conditioning.

Abstract: A new Schottky diode structure, Pt/Al/n-InP, is disclosed in the present invention. The thickness of Al layer of the Schottky diode structure is restricted in a range of about 80-120 .ANG.. This structure gives a barrier height of 0.74 eV and an ideality factor of 1.11 after it was annealed at 300.degree. C. for 10 min. This is due to the formation of Aluminum-oxide, as the interfacial layer to improve barrier height. A method of preparing this Schottky diode structure is also disclosed in the present invention.

Abstract: A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.

Abstract: Gold, which is the commonly used metallization on .beta.-silicon carbide, is known to degrade at temperatures above 450.degree. C. It also exhibits poor adhesion to silicon carbide. Schottky contacts with platinum metallization have rectifying characteristics similar to contacts with gold metallization. The platinum Schottky contacts remain stable up to 800.degree. C. Adhesion of the platinum deposited at slightly elevated temperatures is also superior to that for gold. Platinum provides a metallization that is physically more rugged and thermally more stable than conventional gold metallization.

Abstract: In this MESFET, an undoped AlInAs layer 120, an undoped InP layer 130, an n-InGaAs layer 140, an undoped InP layer 150, and an AlInAs layer 160 are formed on a semi-insulating InP substrate 110. A source electrode 410, a drain electrode 430, and a gate electrode 420 are formed on the AlInAs layer 160. The source electrode 410 and the drain electrode 430 are in ohmic contact with the AlInAs layer 160, and the gate electrode 420 forms a Schottky junction with the AlInAs layer 160.

Abstract: A MODFET device has highly doped source and drain regions separated by an undoped semiconductor alloy in which the mole fraction is graded between the source and the drain and with a conduction (and/or valence) band discontinuity at the heterojunction between the source and semiconductor alloy channel region of the device. Due to the graded mole fraction, the bandgap of the undoped semiconductor alloy decreases along the channel from the source to the drain and creates a built-in electric field. The higher bandgap in the source compared to that in the channel permits high energy carrier injection into the channel, with the built-in longitudinal electric field increasing carrier drift velocity and reducing transit time between the source and drain. In a preferred embodiment, the MODFET device has a vertical structure with the source and semiconductor alloy layers stacked on a drain substrate.

Abstract: A field effect transistor including a first compound semiconductor layer (2) serving as a buffer layer, an InAs layer (3) serving as a channel layer, and a second compound semiconductor layer (4) serving as an electron donor layer or a barrier layer which are, in this order, deposited on a semiconductor substrate (1) having a lattice constant different from that of InAs. The first compound semiconductor layer (2) is formed from a material selected from AlGaAsSb, AlGaPSb, AlInAsSb and AlInPSb which are substantially in lattice matching with InAs and have a bandgap greater than that of InAs, and hence the first layer (2) has a simple structure. An FET having excellent high frequency characteristics can be obtained on the substrate (1) having a lattice constant different from that of the InAs layer (3).

Abstract: A method for producing a T-shaped gate electrode of a semiconductor device including forming an insulating film on a semiconductor substrate, etching away a prescribed portion of the insulating film, depositing a metal film having a prescribed thickness, forming a first photoresist film and removing the photoresist film except where the insulating film has been removed, forming a second photoresist film, patterning the second photoresist film to expose the metal film along a side wall of the insulating film, etching away a portion of the metal film using the first and second photoresist films as a mask, depositing a gate metal and removing the first and second photoresist films and overlying gate metal by lift-off, and etching away the metal films remaining on the semiconductor substrate and the insulating film. Thereby, a T-shaped gate electrode with shortened length is formed.

Abstract: A field effect semiconductor device which restricts current flow through a drain-gate path, but allows current to easily flow through a gate-source path. A high potential barrier layer is formed on the drain side of an active layer. The potential barrier layer has a wider energy band gap than the active layer. A source electrode and a drain electrode make ohmic contact with the active layer and a gate electrode exists between the source electrode and the drain electrode. The gate electrode is partially formed on the potential barrier layer and makes Schottky contact with the active layer on the source side of the semiconductor device and makes Schottky contact with the potential barrier layer on the drain side of the semiconductor device.

Abstract: A MESFET which includes a semi-insulating substrate, e.g., a GaAs substrate, an insulating layer formed on a portion of the upper surface of the substrate, a first semiconductor layer formed on the upper surface of the substrate adjacent to opposite sides of the insulating layer, the first semiconductor layer having sidewalls defining a void therein, a nitride layer formed on a portion of the upper surface of the insulating layer, an oxide layer formed on the nitride layer, a second semiconductor layer formed on the sidewalls of the first semiconductor layer and in covering relationship to the void, a gate electrode formed on at least a portion of the upper surface of the second semiconductor layer, and, source and drain electrodes formed on the upper surface of the first semiconductor layer, on opposite sides of the gate electrode.

Abstract: Disclosed is a semiconductor device such as a light emitting diode, a MOS transistor, a Schottky diode, and CCD. The semiconductor device comprises a SiC layer of a first conductivity type and another SiC layer of a second conductivity type. At least one of the SiC layers of the first and second conductivity types is doped with at least one element selected from the group consisting of Cr, Mo and W.

Abstract: Radiation-emitting semiconductor diodes in the form of a laser diode or in the form of an LED form important components in data-processing systems. There is a particular need for diodes which emit in the visible part of the spectrum, which have a low starting current and which can be manufactured at low cost. A radiation-emitting semiconductor diode comprising above the active layer a cladding layer and a GaAs contact layer, into which a mesa-shaped strip is etched, and provided on the upper and the lower side with a conductive layer, which forms outside the mesa-shaped strip a junction forming a barrier with a subjacent semiconductor layer, partly satisfies the aforementioned requirements.

Abstract: In one form of the invention, a field effect transistor is disclosed, the transistor comprising: a channel between a source and a drain, the channel comprising: a first region 22 of a first semiconductor material having a first doping concentration; a second region 20 of a second semiconductor material having a second doping concentration, the second region 20 lying above the first region 22; a third region 18 of the first semiconductor material having a third doping concentration, the third region lying above the second region 20, wherein the first doping concentration is higher than the second and third doping concentrations; and a gate electrode 12 lying above the third region 18, whereby an electrical current flows in the channel primarily in the first region 22 or primarily in the second region 20 by varying a voltage on the gate electrode 12.

Abstract: A compound semiconductor device includes an undoped semiconductor layer; a doped semiconductor layer formed on the undoped semiconductor layer and having smaller electron affinity than the undoped semiconductor layer; a gate electrode formed on the doped semiconductor layer; a cap layer formed on the doped semiconductor layer; and a source electrode and a drain electrode respectively formed on the cap layer. In the device, an undoped-material layer having greater electron affinity than the doped semiconductor layer and the cap layer, is formed between the doped semiconductor layer and the cap layer. A layer which has the same composition and impurities as those of the doped semiconductor layer and whose impurity concentration is sufficiently higher than an impurity concentration of the doped semiconductor layer may, be provided between the doped semiconductor layer and the cap layer.

Abstract: An advanced MESFET switching structure which includes an interdigitated source region and an interdigitated drain region, also includes a gate electrode region disposed between adjacent portions of the interdigitated source and drain regions having a series gate electrode in Schottky barrier contact therewith. The use of the series connect gate electrode rather than conventional parallel coupled gate fingers eliminates the need for an airbridge overlays to interconnect the source regions as in a conventional MESFET transducer. Moreover, the topography permits smaller MESFET structures and thus higher integration of circuits employing the advanced MESFET switch structure. The smaller transistors will also have lower parasitic reactances. In a preferred embodiment, all interconnections for drain, gate, and source electrodes are disposed on the active layer portion of the transistor providing an even smaller transistor structure.

Abstract: A Schottky barrier diode includes a semiconductor substrate, an ohmic electrode formed on a first region of the semiconductor substrate, and a Schottky metal electrode formed on a second region spaced apart from the first region on the semiconductor substrate. The Schottky electrode includes at least one ohmic portion forming an ohmic contact with the semiconductor substrate, whereby rectifying characteristics of the Schottky barrier diode are improved.

Abstract: A Schottky diode is presented which has reduced minority carrier injection and reduced diffusion of the metallization into the semiconductor. These improvements are obtained by interposing a layer comprising a mixture of silicon and chromium between the anode metallization layer and the semiconductor in a Schottky diode. The layer including chromium acts an effective barrier against the diffusion of the metallization layer into the semiconductor, and at the same time reduces the amount of minority carrier injection into the substrate. The layer including chromium requires no addition photolithograpic masks because it can be plasma etched using the metallization layer as a mask after that layer has been patterned.

Abstract: A quantum semiconductor device comprises a channel region formed with a two-dimensional carrier gas, a Schottky electrode structure provided on the channel region for creating a depletion region in the channel region to extend in a lateral direction such that the two-dimensional carrier gas is divided into a first region and a second region, a quantum point contact formed in the depletion region to connect the first and second regions of the two-dimensional carrier gas in a longitudinal direction, an emitter electrode provided on the channel region in correspondence to the first region of the two-dimensional carrier gas, one or more collector electrodes provided on the channel region in correspondence to the second region of the two-dimensional carrier gas, and another Schottky electrode structure provided in correspondence to the first region for creating a depletion region therein such that a path of the carriers entering into the quantum point contact is controlled asymmetrical with respect to a hypothetic

Abstract: A field effect transistor is disclosed in which a source region and a drain region are formed to be reverse mesa on a semi-insulating semiconductor substrate with an insulating layer thereon by using a crystal growth characteristic corresponding to the crystal orientation. A channel layer and a gate electrode are formed by self-alignment on the upper part of a void formed according to the reverse mesa of the source and the drain regions, so that the channel layer and the semiconductor substrate are electrically separated by the void. By such a construction, a leakage current and backgating effect are removed, and a fast field effect transistor is attained owing to the reduction of an effective channel length and a gate resistance.

Abstract: An EEPROM cell is implemented by a field effect transistor comprising a channel layer of an intentionally undoped gallium arsenide, a carrier supplying layer formed on the channel layer and of a heavily doped n-type aluminum gallium arsenide having deep energy level, and a gate electrode formed on the carrier supplying layer, in which the deep energy level causes a current-voltage collapse phenomenon to take place due to trapping hot electrons injected from the channel layer to the carrier supplying layer in the presence of a stress voltage of about 1.2 volts between the source and drain for minimizing channel conductivity and in which the stress voltage of about 3 volts ionizes the deep energy level so as to allow recovering from the current-voltage collapse phenomenon, thereby providing the low and high channel conductivities to two logic levels.

Abstract: A high power, high frequency, metal-semiconductor field-effect transistor comprises a bulk single crystal silicon carbide substrate, an optional first epitaxial layer of p-type conductivity silicon carbide formed upon the substrate, and a second epitaxial layer of n-type conductivity silicon carbide formed upon the first epitaxial layer. The second epitaxial layer has two separate well regions therein that are respectively defined by higher carrier concentrations of n-type dopant ions than are present in the remainder of the second epitaxial layer. Ohmic contacts are positioned upon the wells for respectively defining one of the well regions as the source and the other as the drain. A Schottky metal contact is positioned upon a portion of the second epitaxial layer that is between the ohmic contacts and thereby between the source and drain for forming an active channel in the second epitaxial layer when a bias is applied to the Schottky contact.

Abstract: A quantum interference semiconductor device comprises a channel layer of a first semiconductor material, a carrier supplying layer of a second semiconductor material provided on the channel layer and whereby a two-dimensional carrier gas is formed in the channel layer along an upper major surface thereof, a source electrode provided on the carrier supplying layer for injecting carriers, a drain electrode provided on the carrier supplying layer and displaced from the source electrode in a first direction defining a region of the channel layer therebetween which collects the injected carriers after travelling through the carrier gas in the first direction and a gate electrode structure provided on the region of the carrier supplying layer and in Schottky contact therewith.

Abstract: A semiconductor device having active parts made from semiconductor diamond. The active parts include a high doped diamond layer for supplying free carriers and a non- or low doped diamond layer for giving the free carriers a conductive region. The free carriers are transferred from the high doped diamond layer to the non- or low doped diamond layer by diffusion or an applied electric field. Since the free carriers move at high speeds in the non- or low doped diamond layer without being scattered by dopant atoms, the semiconductor device is applicable to high frequency devices with stability against a change in temperature.

Abstract: The semiconductor device somprises a silicon substrate, a boron-doped high resistant silicon carbide layer formed on said silicon substrate and a silicon carbide layer formed on said high resistant silicon carbide layer.

Abstract: In a semiconductor device constituting a GaAs MESFET, a GaAs substrate is prepared from a base material containing boron ions as a dopant impurity having a total impurity concentration of 2.times.10.sup.17 atoms/cm.sup.3 or more. The boron ions are introduced into the GaAs substrate during crystal growth so that a uniform distribution of boron ions in the substrate results. Electrode layers are formed at predetermined portions on the GaAs substrate, and an active layer is formed to be adjacent to the electrode layers by ion implantation. Source and drain electrodes are formed on the electrode layers respectively, and a gate electrode is formed on the active layer.

Abstract: A transversal filter comprises an acoustic charge transport device comprising an input contact for introducing a signal into a buried channel through which the signal is transported by a high frequency acoustic wave and a plurality of non-destructive sense electrodes overlying the channel for successively sampling the signal. A memory device is provided for storing a plurality of tap weight signals, with each tap weight signal for being associated with one of the electrodes. A multiplier system is operably connected with each of the electrodes and with the storage device for generating the product of the signal sampled at each electrode and the associated tap weight signal. A summer is operably associated with the multiplier for summing the products and thereby generating an output signal.

Abstract: A mushroom-shaped gate electrode has a lower end in a recess in a semiconductor active layer on a semiconductor substrate. The gate electrode has an enlarged head. A metallic side wall is disposed on a portion of the leg of the gate electrode adjacent the head. Thus, the gate length of a semiconductor device, such as a field effect transistor, is reduced while the effective cross-sectional area of the gate electrode is increased whereby the noise characteristics of the semiconductor device are improved.

Abstract: A silicon carbide field-effect transistor is disclosed which includes an MOS structure composed successively of a silicon carbide layer, a gate insulator film, and a gate electrode. The field-effect transistor has source and drain regions formed in the silicon carbide layer, between which the MOS structure is disposed, wherein at least one of the source and drain regions is formed by the use of a Schottky contact on the silicon carbide layer.

Abstract: A rectifying contact for use at high temperatures including a monocrystalline semiconducting diamond layer on a substrate and a heteroepitaxial metal layer thereon. The metal layer has a lattice match with the diamond and is deposited on the diamond substantially in atomic registry therewith. The metal and diamond form a rectifying contact which has good mechanical adhesion and provides stable rectifying operation at elevated temperatures. The metal layer may be formed by deposition in an ultra-high vacuum. In alternate embodiments, the metal layer may be formed on a monocrystalline semiconducting diamond substrate or on at least one monocrystalline diamond area of a textured polycrystalline layer.