Abstract: A blue-violet-near-ultraviolet pin-photodiode with small dark current, high reliability and long lifetime. The pin-photodiode has a metallic n-electrode, a n-ZnSe single crystal substrate, an optionally added n-ZnSe buffer layer, an n-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, a p-Zn1-xMgxSySe1-y layer, a p-(ZnTe/ZnSe)m SLE, a p-ZnTe contact layer, an optionally provided antireflection film and a metallic p-electrode. A blue-violet-near-ultraviolet avalanche photodiode with small dark current, high reliability and long lifetime. The avalanche photodiode has a metallic n-electrode, a n-ZnSe single crystal substrate, an optionally added n-ZnSe buffer layer, an n-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, a p-Zn1-xMgxSySe1-y layer, a p-(ZnTe/ZnSe)m SLE, a p-ZnTe contact layer, an optionally provided antireflection film and a metallic p-electrode. Upper sides of the layered structure are etched into a mesa-shape and coated with insulating films.

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: An object of the present invention is to improve the relationship between the switching loss and the conduction loss in a semiconductor device comprising a diode and a switching device made of silicon carbide, while suppressing occurrence of voltage oscillation of the device having a high amplitude. A resistor (12) is connected in parallel to a diode (11) made of silicon carbide. Although a resistive component of the diode (11) varies widely with turn-on and turn-off of the diode (11), connecting the resistor (12) in parallel to the diode (11) allows suppression of variations in a resistive component of an LCR circuit formed by the diode (11) and an external wiring. Accordingly, the LCR circuit is unlikely to satisfy the condition of natural oscillation and an increase in the quality factor of the LCR circuit is suppressed.

Abstract: A field oxide surrounding an active region, an N-type doped layer formed in the active region, and an electrode formed on the field oxide in the vicinity of the active region are provided on a P-type semiconductor substrate. During the operation as a constant voltage device, a desired voltage is applied to the electrode. Then, trapping of carriers in the interface between the field oxide and the semiconductor region can be suppressed, although such trapping is ordinarily caused by a reverse breakdown phenomenon at the pn junction between the doped layer and the P-type semiconductor substrate. Accordingly, the variation in strength of the electric field between the doped layer and the semiconductor substrate can be suppressed. As a result, it is possible to suppress a variation in reverse withstand voltage, which is usually caused by a reverse breakdown voltage at a pn junction, for a semiconductor device functioning as a constant voltage device.

Abstract: The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source of at least one transistor of a field effect transistor integrated circuit. The use of one or more Schottky barriers is useful for reducing the susceptibility of latch-up for circuits having two opposite type transistors, i.e., two opposite polarity carriers, in which the two transistors are in close enough proximity to experience latch-up. This can allow the spacing between n- and p-type transistors to be reduced, thus reducing the area of the circuit. The subject invention can also allow the elimination of a metal contact by utilizing the metal layer used to form the metal-semiconductor junction in a complementary IGFET structure, to further reduce the circuit area. The subject invention is applicable to complementary metal oxide silicon (CMOS) devices.

Abstract: A semiconductor device which can prevent an operation thereof from being uncontrollable to obtain a high reliability, and can be manufactured easily and can reduce a manufacturing cost. A p-type impurity layer containing a p-type impurity in a relatively high concentration is provided as an operation region of a diode in one of main surfaces of a silicon substrate containing an n-type impurity in a relatively low concentration and a plurality of ring-shaped Schottky metal layers are concentrically provided on the main surface of the silicon substrate around the p-type impurity layer with a space formed therebetween to surround the p-type impurity layer. A silicon oxide film is provided on the main surface of the silicon substrate around the p-type impurity layer and an anode electrode is provided on the p-type impurity layer.

Abstract: A preferred embodiment of the present invention provides a Schottky diode (100) formed from a conductive anode contact (102), a semiconductor junction layer (104) supporting the conductive contact (102) and a base layer ring (108) formed around at least a portion of the conductive anode contact (102). In particular, the base layer ring (108) has material removed to form a base layer material gap (118) (e.g., a vacuum gap) adjacent to the conductive anode contact (102). A dielectric layer (110) is also provided to form one boundary of the base layer material gap (118).

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: The invention relates to the protection of devices in a monolithic chip fabricated from an epitaxial wafer, such as a wafer for a Group III-V compound semiconductor or a wafer for a Group IV compound semiconductor. Devices fabricated from Group III-V compound semiconductors offer higher speed and better isolation than comparable devices from silicon semiconductors. Semiconductor devices can be permanently damaged when exposed to an undesired voltage transient such as electrostatic discharge (ESD). However, conventional techniques developed for silicon devices are not compatible with processing techniques for Group III-V compound semiconductors, such as gallium arsenide (GaAs). Embodiments of the invention advantageously include transient voltage protection circuits that are relatively efficiently and reliably manufactured to protect sensitive devices from undesired voltage transients.

Abstract: This disclosure describes one-chip micro-integrated optoelectronic sensors and methods for fabricating and using the same. The sensors may include an optical emission source, optical filter and a photodetector fabricated on the same transparent substrate using the same technological processes. Optical emission may occur when a bias voltage is applied across a metal-insulator-semiconductor Schottky contact or a p-n junction. The photodetector may be a Schottky contact or a p-n junction in a semiconductor. Some sensors can be fabricated on optically transparent substrate and employ back-side illumination. In the other sensors provided, the substrate is not transparent and emission occurs from the edge of a p-n junction or through a transparent electrode. The sensors may be used to measure optical absorption, optical reflection, scattering or fluorescence.

Abstract: Disclosed is an avalanche photodiode for use in super-high speed optical communication, more particularly, to a structure of an avalanche photodiode device capable of suppressing edge breakdown to increase avalanche gain factor of a light signal and to reduce a noise. The avalanche photodiode includes a wafer characterized in that the guard ring has a depth equal to that of a center part of the active region (diffused region), an edge of the active region is shallower than the center part, and the guard ring is electrically isolated from the active region. Therefore, a gain-bandwidth characteristic may be increased, and also the higher receiver sensitivity may be achieved.

Abstract: The invention relates to a semiconductor device, in particular a Schottky hybrid diode with a guard ring (S). The semiconductor device comprises a semiconductor substrate (1), an epitaxial layer (2) on which an insulating layer (3) with an opening (10) is deposited, with a Schottky metal layer (9) covering the epitaxial layer (2) lying at the bottom of the opening (10), and with an annular semiconductor region (4) which is present in the epitaxial layer (2). A doping region (6) is present in the epitaxial layer (2) along the outer contour of the semiconductor device, and in addition an oxide layer (8) is present on the epitaxial layer (2).

Abstract: Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are formed in a semiconductor substrate such as silicon. Furthermore, a cathode side P layer 103 is also formed facing a cathode electrode 105 in a position on the N layer 101 that a depletion layer extended during application of a reverse bias voltage does not reach. By providing the cathode side P layer 103, a current density of a reverse current obtained during a reverse recovery operation can be increased, the sudden change of a resistance component of a diode can be prevented and the generation of a voltage oscillation can be suppressed. The cathode side P layer 103 has a diameter W of approximately 400 &mgr;m or less and a rate of an area of the cathode side P layer 103 occupying a cathode surface is kept at approximately ⅖ or less.

Abstract: A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings in an implant and drive system. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or palladium contact layer. A thin high resistivity layer of amorphous silicon is deposited over the full upper surface of the wafer and is disposed between the wafer upper surface and all of the metal rings.

Abstract: A semiconductor device comprises a semiconductor body (10) in and on which a power transistor (T; 1, 2, 3) and a suppression diode (D; 100) are integrated. A diode junction (40; 40′) is present between the back metallization (22) and the adjacent region (2) of the power transistor so as to provide the diode in series with this region (2) and adjacent to the back surface (12) of the body. This diode junction (40; 40′) opposes the p-n junction (42) between the collector or drain region (2) of the transistor and its base region (3), so as to suppress reverse current flow in the transistor. The higher doped part (2b) of the adjacent transistor region (2) is sufficiently thick as to prevent any minority charge carriers injected by the diode junction (40; 40′) from reaching the p-n junction (42) with the base region (3). The diode junction may be a p-n junction (40) or a Schottky barrier (40′).

Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: A semiconductor component includes a semiconductor layer (210) and at least one diode (220) in the semiconductor layer. The semiconductor component also includes an electrically insulative layer (230) over the semiconductor layer and the diode. The semiconductor component further includes at least one more diode (240, 250, 280, 290, 440, 450) over the electrically insulative layer, the semiconductor layer, and the diode in the semiconductor layer.

Abstract: A semiconductor device is provided which minimizes a reduction in the breakdown voltage caused by a metal electrode to which a high voltage is applied. An n− semiconductor layer (3) is formed on a p− semiconductor substrate (1). A p+ impurity region (4) is formed within the n− semiconductor layer (3), extending from the surface of the n− semiconductor layer (3) to the interface of the n− semiconductor layer (3) and the p− semiconductor substrate (1). The p+ impurity region (4) is formed to surround part of the n− semiconductor layer (3) and forms a high-potential island region (101) where a logic circuit (103), an n+ impurity region (5) which is a cathode region of a bootstrap diode (102), and a p+ impurity region (6) which is an anode region are located.

Abstract: A power semiconductor device of the present invention comprises a voltage drive type power MOS transistor, a series connection of a first resistor and Zener diode, a second resistor, and a series connection of a third resistor and MOS transistor. The power MOS transistor has a gate, source and drain. A drain-to-source voltage of the power MOS transistor is applied across the series connection of the first resistor and Zener diode. A gate-to-source voltage of the power MOS transistor is applied across the second resistor. The gate-to-source voltage of the power MOS transistor is applied across a series connection of a third resistor and the MOS transistor. The MOS transistor has a gate, source and drain. The gate of the MOS transistor is connected to a node between the first resistor and the Zener diode.

Abstract: An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.

Abstract: Chemically assembled electronic nanotechnology (CAEN) provides an alternative to using Complementary Metal Oxide Semiconductor (CMOS) for constructing circuits with feature sizes in the tens of nanometers. A molecular latch and a method using the latch that enables it to act as a state holding device, perform voltage restoration, and to provide I/O isolation is disclosed.

Abstract: A FRED device having an ultralow Irr employs a contact layer which contacts spaced P diffusions in an N type silicon substrate and also contacts the silicon surface spanning between the P diffusions. The contact layer is formed of a contact having a lower barrier height than the conventional aluminum, and is palladium silicide with a top contact layer of aluminum.

Abstract: The invention relates to a semiconductor component which is capable of blocking such as an (IGBT), a thyristor, a GTO or diodes, especially schottky diodes. An insulator profile section (10a, 10b, 10c, 10d, 11) provided in the border area of an anode metallic coating (1, 31) is fixed (directly in the edge area) on the substrate (9) of the component. The insulator profile has a curved area (KB) and a base area (SB), said curved area having a surface (OF) which begins flat and curves outward and upward in a steadily increasing manner. A metallic coating MET1; 30a, 30b, 30c, 30d, 31b) is deposited on the surface (OF). Said coating directly follows the surface curvature and laterally extends the inner anode metallic coating. The upper end of the curved metallic coating (MET1; 30a, 30b . . . ) is distanced and insulated from one of these surrounding outer metallic coatings (MET2; 3) by the surrounding base area (SB) of the insulator profile (10a, . . .

Abstract: Trenches are formed in the surface of a second semiconductor layer of a first conductivity type. A semiconductor filled material of a second conductivity type is filled in the trench. A Schottky metal electrode is formed on the surface of the second semiconductor layer and the surface of the semiconductor filled material. A Schottky junction is formed between the Schottky metal electrode and the second semiconductor layer. An ohmic contact is formed between the Schottky metal electrode and the semiconductor filled material. An avalanche breakdown voltage is increased when the impurity concentration of the second semiconductor layer and the semiconductor filled material and the interval between the trenches are set such that both the second semiconductor layer interposed between the semiconductor filled materials and the semiconductor filled material are completely depleted when the Schottky junction is reverse biased.

Abstract: A Schottky diode, and a method of making the same, which is fabricated on InP material and employs a Schottky layer including InxAl1−xAs with x>0.6, or else including a chirped graded supperlattice in which successive periods of the superlattice contain progressively less GaInAs and progressively more AlInAs, the increase in AlInAs being terminated before the proportion of AlInAs within the last period (adjacent the anode metal) exceeds 80%. Such fabrication creates an InP-based Schottky diode having a low turn-on voltage which may be predictably set within a range by adjusting the fabrication parameters.

Abstract: A gas sensor having a pn junction including two discrete electrical conductive-type layers, namely, a first semiconductor layer and a second semiconductor layer, disposed in contact with each other. Ohmic electrodes are formed on the respective surfaces of the semiconductor layers. A catalytic layer containing a metallic catalytic component which dissociates hydrogen atom from a molecule having hydrogen atom is formed on one of the ohmic electrodes. The pn junction diode-type gas sensor has a simple constitution, exhibits a small change in diode characteristics with time in long-term service and is capable of detecting a gas concentration of a molecule having a hydrogen atom, for example, H2, NH3, H2S, a hydrocarbon and the like, contained in a sample gas.

Abstract: A monolithic assembly of a vertical fast diode with at least one additional vertical component, in which the fast diode is formed by an N-type substrate in one surface of which an N+-type continuous region is formed and in the other surface of which a P+-type discontinuous region is formed. The bottom surface of the assembly is coated with a single metallization. The other vertical component is, for example, a diode.

Abstract: A low impurity concentration semiconductor layer (2) of n−-type is formed by epitaxial growth method on a high impurity concentration semiconductor substrate (1) of n+-type. A plurality of p+-type semiconductor regions (6) are formed in the surface side of the semiconductor layer (2). On the surface of the semiconductor layer and p+-type semiconductor regions, a metal layer (3) is provided to form Schottky barrier with the semiconductor layer (2). Further, p+-type semiconductor regions are arranged regularly so that the plan configuration of each of the semiconductor regions on the surface side of n−-type semiconductor layer is a circularity or a polygon, and that the furthest portion of the plan configulation neighbors or overlaps with immediate adjacent ones, or so that the ratio of the total area of the semiconductor regions (6) to the other portion except for the regions is (2 to 6):1.

Abstract: An avalanche photodiode (APD) of the present invention uses a distortion-compensated superlattice multiplication layer (103) for the superlattice multiplication layer. It also uses a multi-layered light-reflecting layer as the light-reflecting layer. This structure of the present invention makes it possible to reduce a layer thickness of the superlattice multiplication layer without decreasing an electron multiplication factor and increasing a dark current. Accordingly, the APD of the present invention shows high response and low operating voltage, while it also maintains low dark current, low noise and broad band at the same time.

Abstract: An edge termination for a semiconductor component containing a semiconductor body formed of silicon carbide. The edge termination has at least one diode chain that is insulated from the semiconductor body and provided with a plurality of semiconductor layers having alternating conductivity types.

Abstract: Inner trenches (11) of a trenched Schottky rectifier (1a; 1b; 1c; 1d) bound a plurality of rectifier areas (43a) where the Schottky electrode (3) forms a Schottky barrier 43 with a drift region (4). A perimeter trench (18) extends around the outer perimeter of the plurality of rectifier areas (43a). These trenches (11, 18) accommodate respective inner field-electrodes (31) and a perimeter field-electrode (38) that are connected to the Schottky electrode (3). The inner field-electrodes (11) are capacitively coupled to the drift region (4) via dielectric material (21) that lines the inner trenches (11). The perimeter field-electrode (38) is capacitively coupled across dielectric material (28) on the inside wall (18a) of the perimeter trench 18, without acting on any outside wall (18b). Furthermore, the inner and perimeter trenches (11, 18) are closely spaced and the intermediate areas (4a, 4b) of the drift region (4) are lowly doped.

Abstract: A MOS type semiconductor apparatus is provided that includes a first MOS type semiconductor device through which main current flows, and a second MOS type semiconductor device through which current that is smaller than the main current flows. The first and second MOS type semiconductor devices provided on the same semiconductor substrate have substantially the same structure, and have a common drain electrode. A gate electrode of the second MOS type semiconductor device is connected to the common drain electrode. The semiconductor apparatus further includes a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device. Each pair of Zener diodes are reversely connected to each other.

Abstract: A high power rectifier device has an N− drift layer on an N+ layer. A number of trench structures are recessed into the drift layer opposite the N+ layer; respective mesa regions separate each pair of trenches. Each trench structure includes oxide side-walls, a shallow P+ region at the bottom of the trench, and a conductive material between the top of the trench and its shallow P+ region. A metal layer contacts the trench structures and mesa regions, forming Schottky contacts. Forward conduction through both Schottky and P+ regions occurs when the device is forward-biased, with the Schottky contact's low barrier height providing a low forward voltage drop. When reversed-biased, depletion regions around the shallow P+ regions and the side-walls provide a potential barrier which shields the Schottky contacts, providing a high reverse blocking voltage and reducing reverse leakage current.

Abstract: The present invention provides a power semiconductor device comprising a semiconductor substrate; a voltage-controlled transistor comprising a first electrode formed on the lower surface of the semiconductor substrate, a gate formed on the semiconductor substrate with a gate oxide interpolated in between and a second electrode formed on the semiconductor substrate; and a zener diode formed on the upper surface of the semiconductor substrate so as to be connected between the gate and the second electrode; wherein p-type regions and n-type regions alternately formed between the zener diode and the second electrode on the semiconductor substrate, a plurality of pad electrodes on the semiconductor substrate provided with the alternate p-type regions and n-type regions so as to allow one or not less than two diodes are series connected between the zener diode and the second electrode, and the distance between the adjacent pad electrodes is set so that when the diode is subjected to a current not less than a predet

Abstract: The invention provides a zener zap diode having a high reliability and a method of manufacturing the same that can remove the problems accompanied with the zener zap trimming. In order to attain the object, the zener zap diode according to the invention is constructed such that, in an area adjacent to the surface of a semiconductor substrate, an active base region, an outer base region, and an emitter region are formed. Furthermore, a base lead electrode (one polysilicon layer) is formed to overlay the outer base region, and an emitter lead electrode (another polysilicon layer) is formed above the active base region. A contact between the one polysilicon layer and a metal interconnecting layer is disposed right above the outer base region. Since the insulation film that hinders the filament from being formed is not disposed under the one polysilicon layer, a filament is widely formed into an N-type well region when a PN junction is zapped by the zener zap trimming method.

Abstract: A fast recovery diode (FRED) is fabricated by a process using a reduced number of masking steps. The FRED is a vertical conduction device in which P type anode regions are isolated using either LOCOS oxidation or deposited low temperature oxide. The first masking step defines the anode and isolation regions, and a second masking step defines the aluminum contact layer. For devices having a breakdown voltage greater than 800 volts, a third masking step is included which defines the passivated area.

Abstract: A semiconductor device which has few peripheral element malfunctions and superior performance is obtained. The semiconductor device includes a p-type buried layer on a main surface of a semiconductor substrate, an n-type cathode region provided on the p-type buried layer, and a p-type anode region in contact with the side surface of the n-type cathode region, the p-type buried layer being higher than the p-type anode region in acceptor content, and the p-type buried layer being in contact with the bottom surfaces of the anode and cathode regions.

Abstract: A Schottky barrier diode is provided which has a substrate including a first-conductivity-type low concentration layer and a first-conductivity-type high concentration layer, and a guard ring region, comprising a second-conductivity-type diffusion layer having an impurity surface concentration of not greater than 5×1017/cm3, formed in the first-conductivity-type low concentration layer. The first-conductivity-type low concentration layer has a thickness large enough to prevent a depletion layer that appears in the low concentration layer upon application of the maximum reverse voltage from reaching the first-conductivity-type high concentration layer.

Abstract: A semiconductor device of the present invention is a semiconductor device of a complementary MIS field effect transistor, wherein an anode of a first diode is connected to a silicon substrate of a first conduction type while a cathode of the first diode is connected to a first power supply while a cathode of a second diode is connected to a well of the other conduction type and an anode of the second diode is connected to a second power supply.

Abstract: A monolithic integrated device includes a protection structure and is formed in a semiconductor material substrate having a first conductivity type, which device includes at least a first epitaxial layer formed on the substrate. The integrated device further includes a bipolar first transistor formed of a base region having a second conductivity type and including a first buried region formed in the first epitaxial layer, and having a first diffused region which extends from the first buried region to contact a top surface of the integrated device through a surface contact region with a high concentration of dopant material. The first transistor also has an emitter region with the first conductivity type, embedded in the base region, and including a second buried region formed on the first buried region and a second diffused region, with a high concentration of dopant material, which extends from the second buried region to contact the top surface of the integrated device.

Abstract: A semiconductor device is provided which includes a first conductivity type semiconductor substrate, a second conductivity type Zener region formed in a surface layer of the first conductivity type semiconductor substrate, a first conductivity type anode region formed within the second conductivity type Zener region, an anode electrode which is formed in contact with both of the semiconductor substrate and first conductivity type anode region and is grounded, and a cathode electrode formed on a surface of the second conductivity type Zener region and connected to input and output terminals. A diode that consists of the first conductivity type semiconductor substrate and the second conductivity type Zener region and a diode that consists of the first conductivity type anode region and the second conductivity type Zener region serve as protective elements for preventing electrostatic breakdown of the semiconductor device.

Abstract: A semiconductor device of the present invention is a semiconductor device of a complementary MIS field effect transistor, wherein an anode of a first diode is connected to a silicon substrate of a first conduction type while a cathode of the first diode is connected to a first power supply while a cathode of a second diode is connected to a well of the other conduction type and an anode of the second diode is connected to a second power supply.

Abstract: A semiconductor power device (100) that includes a number of bipolar or FET power devices (116), an over-voltage clamp (118), and an edge termination structure (110) that separates the power devices (116) and the over-voltage clamp (118). The power devices (116) are formed in an interior region (100a) of a semiconductor substrate (128), while the over-voltage clamp (118) is formed in a peripheral region (100b) of the substrate. The over-voltage clamp (118) and the gate/base terminals of the power devices (116) are formed in a polysilicon layer (126) overlying the substrate (128), such that the over-voltage clamp (118) is connected between the anode and gate/base terminals of each power device (116) to provide over-voltage protection.

Abstract: According to the present invention, an improved method for buried diode formation in CMOS processing is disclosed. Using a hybrid photoresist process, a self-aligning Zener diode is created using a two-step photolithography mask process. Since the process disclosed in the invention uses only the p-well and the n-well masks to create the Zener diode, photolithography alignment problems are reduced and Zener diodes can be create at the sub-micron scale.

Abstract: A light-emitting-diode array includes a non-doped compound semiconductor layer between a substrate and a first compound semiconductor layer. A plurality of isolation regions extend from the first compound semiconductor layer to the surface of the non-doped compound semiconductor layer, and provide separation into isolated block regions each containing an equal number of diffusion regions. A plurality of shared electrode lines are connected to the diffusion regions in a plurality of the block regions, in such a relationship that diffusion regions selected from each of the block regions are connected to a common shared electrode. At least a surface portion of the substrate is formed of silicon. The density of the diffusion regions can be increased without increasing the number of the electrode pads. Moreover, the substrate is free from breakage or cracks.

Abstract: A vertical conduction Schottky device having a reverse voltage rating in excess of 400 volts uses an aluminum barrier metal in contact with an N.sup.- epitaxial silicon surface. A diffused P.sup.+ guard ring surrounds the barrier metal contact and is spaced therefrom by a small gap which is fully depleted at a low reverse voltage to connect the ring to the barrier contact under reverse voltage conditions. Lifetime killing is used for the body of the diode.

Abstract: In a semiconductor electron emission device for causing an avalanche breakdown by applying a reverse bias voltage to a Schottky barrier junction between a metallic material or metallic compound material and a p-type semiconductor, and externally emitting electrons from a solid-state surface, a p-type semiconductor region (first region) for causing the avalanche breakdown contacts a p-type semiconductor region (second region) for supplying carriers to the first region, and a semi-insulating region is formed around the first region.

Abstract: A MOS transistor formed in a silicon on insulator structure includes a rectifying connection between a body portion and the gate. The connection decreases the threshold voltage of the transistor in the reverse bias state and limits a difference in voltage between the body and gate in the forward bias state of the rectifying contact.

Abstract: To provide a field-effect transistor having a large power conversion capacity and its fabrication method by decreasing the leakage current between the source and the drain of a semiconductor device made of hexagonal-system silicon carbide when the gate voltage of the semiconductor device is turned off and also decreasing the electrical resistance of the semiconductor device when the gate voltage of the semiconductor device is turned on. The main current path of the field-effect transistor is formed so that the current flowing between the source and the drain of, for example, a field-effect transistor flows in the direction parallel with the {0001} plane and a channel forming plane is parallel with the {1120} plane. ?Selected Drawing!FIG.

Abstract: A latch-type SRAM memory cell having a number of MOS transistors arranged to maintain symmetry with each other circuitwise, in which the source regions of the MOS transistors are arranged so as to be adjacent semiconductor regions of opposite conductivity with respect thereto. Zener diodes are formed between the adjacent source and semiconductor regions with each of these Zener diodes being connected between their respective source regions and a power supply. Since current to each source region of paired MOS transistors flows effectively to the power supply or ground side via a Zener diode using a tunneling effect, a rise in the source region potential can be reduced, and an increase in the transistor threshold value can be controlled. In this way, symmetry of the paired transistors can be maintained, and the performance of the memory cell, e.g., memory cell data retention ability and drive current ability, can be increased.