Abstract: A low-noise Zener diode that enables to improve the surge resistance performance without degeneration of its low-noise characteristic is provided. The diode contains a semiconductor substrate of a first conductivity type and a first impurity doped region of a second conductivity type formed in a surface area of the substrate. The first impurity doped region has spaces into which no impurity of the second conductivity type is doped. The diode further contains a second impurity doped region of the second conductivity type formed in the first impurity doped region. The second impurity doped region has a depth less than that of the first impurity doped region. The second impurity doped region is contacted with the substrate in the spaces, producing main p-n junctions of the diode at respective interfaces of the second impurity doped regions and the substrate. The second impurity doped region is contacted with the first impurity doped region other than in the spaces.

Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.

Abstract: An electrostatic discharge protection circuit 11 coupled between an input pad 12 and operational circuitry 20 includes a primary clamp circuit 14 coupled to input pad 12, and a current limit circuit 16 coupled to primary clamp circuit 14. Primary clamp circuit 14 clamps an electrostatic discharge voltage to a first voltage value. Operational circuitry 20, susceptible to damage due to an electrostatic discharge, is coupled to current limit circuit 16 and a zener diode 30 is coupled between current limit circuit 16 and a ground potential. Zener diode 30 has a cathode terminal coupled to current limit circuit 16 and an anode terminal coupled to ground potential. Zener diode 30 further clamps a voltage across operational circuitry 20 to a second voltage which is less than 10 V, thereby protecting operational circuitry 20 from damage due to electrostatic discharge.

Abstract: A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.

Abstract: A voltage regulator diode according to the present invention comprises: a semiconductor substrate (W); a highly doped source region (3) formed in the substrate (W) to adjoin one surface thereof; a highly doped drain region (D) formed in tile substrate (W) to adjoin the above-mentioned surface; a source electrode (4) held in contact with the source region (3); a shorting electrode (9) held in contact with the drain region (D); a gate insulating portion (8a) formed between the source region (3) and the drain region (4) to partly cover the above-mentioned surface of the substrate (W); and a gate electrode (10) formed to cover the gate insulating portion (8a). The gate electrode (19) is shorted to the drain region (D) through the shorting electrode (9). As a result, a channel (12) is formed in the substrate (W) to establish conduction between the source region (3) and the drain region (4) when a gate voltage not less than a predetermined threshold value is applied.

Abstract: A high speed soft recovery diode having a large breakdown voltage is disclosed. Anode P layers (3) are selectively formed in a top portion of an N.sup.- body (2). A P.sup.- layer (4a) is disposed in the top portion of the N.sup.- body (2) so as to be spacewise complementary to the anode P layers (3). In the N.sup.- body (2), P regions (5) are selectively formed below the P.sup.- layer (4a). On the N.sup.- body (2), an anode electrode (6) is disposed in contact with both the P.sup.- layer (4a) and the anode P layers (3). A cathode electrode (7) is disposed under the N.sup.- body (2) through a cathode layer (1). When the diode is reverse-biased, a depletion layer does not have a sharply curved configuration due to the P regions (5). Hence, concentration of electric field is avoided and a breakdown voltage would not deteriorate. During forward-bias state of the diode, injection of excessive holes from the anode P layers (3) into the N.sup.- body (2) is prevented, thereby reducing a recovery current.

Abstract: A semiconductor device including first and second diodes which are provided on the same side of a semiconductor substrate of a first conductivity type and which are connected in series with each other through the substrate. A main surface of the substrate is covered with an insulator film having first and second windows. A first patterned conductive film of a second conductivity type is in contact with the main surface of the substrate through the first window. The first conductive film and the substrate forme a p-n junction of a first diode at their interface. A second patterned conductive film is formed on the first conductive film acting as one of electrodes of the semiconductor device. A first conductive region of the second conductivity type is formed in a surface area of the substrate adjacent to the main surface. The first conductive region and the substrate form a p-n junction of a second diode at their interface.

Abstract: Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a p-n junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two p-n junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. Minority carriers injected by the diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device.

Abstract: The hold current of a breakover type surge protection device is increased by irradiating the device with .gamma. or x rays so as to form crystal lattice defects in the semiconductor regions thereof.

Abstract: An integrated circuit including an array of diodes includes first Schottky diodes, each of which is connected by its cathode to a point to be protected and by its anode to a reference voltage, and second Schottky diodes, each of which is connected by its anode to a point to be protected and by its cathode to the cathode of an avalanche diode, the anode of which is connected to the reference voltage. This integrated circuit includes, in a P-type substrate, a first and a second group of N-type wells; an ohmic contact and a Schottky contact on each well; an N-type region on the upper surface of the substrate; a metallization connecting the ohmic contacts of the first group of wells to the N-type region; a metallization connecting the Schottky contacts of the second wells; metallizations respectively connecting a Schottky contact of the second group of wells to an ohmic contact of the first wells; and a rear surface metallization.

Abstract: An avalanche diode structure incorporated in an integrated circuit is embodied by the lateral junction between two adjacent buried layers having opposite conductivity types and a high doping level. This diode includes: a first highly doped buried layer of the same first conductivity type as the integrated circuit substrate; a second highly doped buried layer of the second conductivity type, surrounding the first buried layer and laterally contacting the first layer; and a third low doped buried layer of the second conductivity type disposed beneath the first buried layer and overlapping with respect to the second layer so as to also contact a portion of the second buried layer.