Field Relief Electrode Patents (Class 257/488)
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Patent number: 8293614Abstract: An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.Type: GrantFiled: December 21, 2011Date of Patent: October 23, 2012Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Sanford Chu, Yisuo Li, Guowei Zhang, Verma Purakh
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Patent number: 8264057Abstract: A semiconductor device includes a low-side circuit, high-side circuit, a virtual ground potential pad, a common ground potential pad and a diode, formed on a semiconductor substrate. The low-side circuit drives a low-side power transistor. The high-side circuit is provided at a high potential region, and drives a high-side power transistor. The virtual ground potential pad is arranged at the high potential region, and coupled to a connection node of both power transistors to supply a virtual ground potential to the high-side circuit. The common ground potential pad supplies a common ground potential to the low-side circuit and high-side circuit. The diode has its cathode connected to the virtual ground potential pad and its anode connected to the common ground potential pad.Type: GrantFiled: December 24, 2009Date of Patent: September 11, 2012Assignee: Mitsubishi Electric CorporationInventor: Kazuhiro Shimizu
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Patent number: 8237196Abstract: A semiconductor device includes: a first semiconductor layer of non-doped AlXGa1-XN (0?X<1); a second semiconductor layer of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) on the first semiconductor layer; a first electrode on the second semiconductor layer; a second electrode on the second semiconductor layer that is separated from the first electrode and electrically connected to the second semiconductor layer; a first insulating film covering the first and second electrodes; a first field plate electrode electrically connected to the first electrode and covered by a second insulating film; and a second field plate electrode on the second insulating film, wherein a length of at least one of the first and second field plate electrodes in a first direction from the first electrode toward the second electrode changes periodically in a second direction intersecting the first direction.Type: GrantFiled: February 24, 2010Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Wataru Saito
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Publication number: 20120193749Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.Type: ApplicationFiled: April 16, 2012Publication date: August 2, 2012Applicant: Fuji Electric Device Technology Co., Ltd.Inventors: Ryouichi KAWANO, Tomoyuki Yamazaki, Michio Nemoto, Mituhiro Kakefu
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Publication number: 20120193748Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.Type: ApplicationFiled: April 11, 2012Publication date: August 2, 2012Inventors: Joseph A. Yedinak, Daniel Calafut, Dean E. Probst
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Patent number: 8232593Abstract: A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer, at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer, at least one insulator buried in the at least one trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semicoType: GrantFiled: February 26, 2010Date of Patent: July 31, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Hiroshi Ohta, Munehisa Yabuzaki, Nana Hatano, Miho Watanabe
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Patent number: 8222691Abstract: In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.Type: GrantFiled: August 25, 2009Date of Patent: July 17, 2012Assignee: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Martin H. Manley
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Patent number: 8188574Abstract: A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip.Type: GrantFiled: February 12, 2010Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Matthew S. Angyal, Mahender Kumar, Effendi Leobandung, Jay W. Strane
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Patent number: 8174048Abstract: A III-nitride device includes a recessed electrode to produce a nominally off, or an enhancement mode, device. By providing a recessed electrode, a conduction channel formed at the interface of two III-nitride materials is interrupted when the electrode contact is inactive to prevent current flow in the device. The electrode can be a schottky contact or an insulated metal contact. Two ohmic contacts can be provided to form a rectifier device with nominally off characteristics. The recesses formed with the electrode can have sloped sides. The electrode can be formed in a number of geometries in conjunction with current carrying electrodes of the device. A nominally on device, or pinch resistor, is formed when the electrode is not recessed. A diode is also formed by providing non-recessed ohmic and schottky contacts through an insulator to an AlGaN layer.Type: GrantFiled: January 21, 2005Date of Patent: May 8, 2012Assignee: International Rectifier CorporationInventor: Robert Beach
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Patent number: 8173510Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of the surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.Type: GrantFiled: February 15, 2011Date of Patent: May 8, 2012Assignee: Texas Instruments IncorporatedInventors: Marie Denison, Taylor Rice Efland
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Patent number: 8159024Abstract: In one aspect, a lateral MOS device is provided. The lateral MOS device includes a gate electrode disposed at least partially in a gate trench to apply a voltage to a channel region, and a drain electrode spaced from the gate electrode, and in electrical communication with a drift region having a boundary with a lower end of the channel region. The device includes a gate dielectric layer in contact with the gate electrode, and disposed between the gate electrode and the drain electrode. The channel region is adjacent to a substantially vertical wall of the gate trench. The device includes a field plate contacting the gate electrode and configured to increase a breakdown voltage of the device.Type: GrantFiled: April 20, 2008Date of Patent: April 17, 2012Assignee: Rensselaer Polytechnic InstituteInventors: Tat-sing Paul Chow, Kamal Raj Varadarajan
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Patent number: 8148783Abstract: Semiconductor device including semiconductor layer, first impurity region on surface layer portion of semiconductor layer, body region at interval from first impurity region, second impurity region on surface layer portion of body region, field insulating film at interval from second impurity region, gate insulating film on surface of the semiconductor layer between second impurity region and field insulating film, gate electrode on gate insulating film, first floating plate as ring on field insulating film, and second floating plate as ring on same layer above first floating plate. First and second floating plates formed by at least three plates so that peripheral lengths at centers in width direction thereof are entirely different from one another, alternately arranged in plan view so that one having relatively smaller peripheral length is stored in inner region of one having relatively larger peripheral length, and formed to satisfy relational expression: L/d=constant.Type: GrantFiled: December 24, 2009Date of Patent: April 3, 2012Assignee: Rohm Co., Ltd.Inventor: Yoshikazu Nakagawa
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Patent number: 8143679Abstract: A semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. The termination region includes a first silicon region of a first conductivity type extending to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. The second silicon region has a recessed portion extending below the first depth and out to an edge of a die housing the semiconductor power device. The recessed portion forms a vertical wall at which the first silicon region terminates. A first conductive electrode extends into the recessed portion and is insulated from the second silicon region.Type: GrantFiled: June 8, 2009Date of Patent: March 27, 2012Assignee: Fairchild Semiconductor CorporationInventor: Christopher Boguslaw Kocon
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Publication number: 20120043638Abstract: A semiconductor device includes: a first insulating layer; a semiconductor layer provided on the first insulating layer; a first semiconductor region selectively provided in the semiconductor layer; a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region; a first main electrode provided in contact with the first semiconductor region; a second main electrode provided in contact with the second semiconductor region; a second insulating layer provided on the semiconductor layer; a first conductive material provided in the second insulating layer above a portion of the semiconductor layer located between the first semiconductor region and the second semiconductor region; and a second conductive material provided in a trench provided in a portion of the semiconductor layer opposed to the first conductive material, being in contact with the first conductive material, and reaching the first insulating layer.Type: ApplicationFiled: November 2, 2011Publication date: February 23, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Mitsuhiko Kitagawa
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Patent number: 8120136Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.Type: GrantFiled: November 2, 2009Date of Patent: February 21, 2012Assignee: Analog Devices, Inc.Inventors: William Allan Lane, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, Bernard Patrick Stenson
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Patent number: 8120064Abstract: A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance Lf from the edge of the gate contact toward the drain contact. The field plate is electrically connected to the gate contact and provides a reduction in the peak operational electric field.Type: GrantFiled: January 21, 2009Date of Patent: February 21, 2012Assignee: Cree, Inc.Inventors: Primit Parikh, Yifeng Wu
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Patent number: 8110888Abstract: High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection.Type: GrantFiled: September 9, 2008Date of Patent: February 7, 2012Assignee: Microsemi CorporationInventors: Jinshu Zhang, Dumitru Sdrulla, Dah Wen Tsang
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Patent number: 8080858Abstract: A Semiconductor component having a space saving edge structure is disclosed. One embodiment provides a first side, a second side, an inner region, an edge region adjoining the inner region in a lateral direction of the semiconductor body, and a first semiconductor layer extending across the inner region and the edge region and having a basic doping of a first conductivity type. At least one active component zone of a second conductivity type, which is complementary to the first conductivity type, is disposed in the inner region in the first semiconductor layer. An edge structure is disposed in the edge region and includes at least one trench extending from the first side into the semiconductor body. An edge electrode is disposed in the trench, a dielectric layer is disposed in the trench between the edge electrode and the semiconductor body, a first edge zone of the second conductivity type adjoin the trench and are at least partially disposed below the trench.Type: GrantFiled: August 3, 2007Date of Patent: December 20, 2011Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Ralf Siemieniec, Christian Geissler
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Patent number: 8076749Abstract: A semiconductor device includes: a first insulating layer; a semiconductor layer provided on the first insulating layer; a first semiconductor region selectively provided in the semiconductor layer; a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region; a first main electrode provided in contact with the first semiconductor region; a second main electrode provided in contact with the second semiconductor region; a second insulating layer provided on the semiconductor layer; a first conductive material provided in the second insulating layer above a portion of the semiconductor layer located between the first semiconductor region and the second semiconductor region; and a second conductive material provided in a trench provided in a portion of the semiconductor layer opposed to the first conductive material, being in contact with the first conductive material, and reaching the first insulating layer.Type: GrantFiled: February 13, 2008Date of Patent: December 13, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Mitsuhiko Kitagawa
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Publication number: 20110291203Abstract: A semiconductor device according to an embodiment of the present invention includes a active region, a drain electrode, a source electrode, a gate electrode, a passivation layer, a source field plate, and a electrical connection. The active region is formed on a semiconductor substrate. The drain electrode, the source electrode, and the gate electrode are formed on a surface of the active region to be separated from each other. The passivation layer is formed on a surface of the active region between the drain electrode and the source electrode to cover the gate electrode. The source field plate is formed at least at a position including an upper portion of the drain-side end portion of the gate electrode on a surface of the passivation layer. The electrical connection is formed on the passivation layer to connect the source field plate and the source electrode. The electrical connection has a width of the electrical connection smaller than electrode widths of the source field plate and the source electrode.Type: ApplicationFiled: February 8, 2011Publication date: December 1, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Akio MIYAO
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Patent number: 8048765Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.Type: GrantFiled: August 28, 2009Date of Patent: November 1, 2011Assignee: Broadcom CorporationInventors: Xiangdong Chen, Bruce Chih-Chieh Shen, Henry Kuo-Shun Chen
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Patent number: 7999287Abstract: In one embodiment a lateral HEMT has a first layer, the first layer including a semiconducting material, and a second layer, the second layer including a semiconducting material and being at least partially arranged on the first layer. The lateral HEMT further has a passivation layer and a drift region, the drift region including a lateral width wd. The lateral HEMT further has at least one field plate, the at least one field plate being arranged at least partially on the passivation layer in a region of the drift region and including a lateral width wf, wherein wf<wd.Type: GrantFiled: October 26, 2009Date of Patent: August 16, 2011Assignee: Infineon Technologies Austria AGInventors: Markus Zundel, Franz Hirler, Walter Rieger
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Patent number: 7973382Abstract: A gate electrode 20 and first field plates 22a to 22d and 23 are provided on a field oxide film 19. The gate electrode 20 and first field plates 22a to 22d and 23 are covered with an insulating film 24. A high-voltage wiring conductor 28 is provided on the insulating film 24. A shielding electrode 29 is provided between the first field plate 22a positioned closest to a source side and the high-voltage wiring conductor 28.Type: GrantFiled: July 24, 2007Date of Patent: July 5, 2011Assignee: Mitsubishi Electric CorporationInventor: Tetsuo Takahashi
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Patent number: 7915644Abstract: A HEMT comprising an active region comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the active region. A spacer layer is formed on at least a portion of a surface of said active region and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT.Type: GrantFiled: May 7, 2009Date of Patent: March 29, 2011Assignee: Cree, Inc.Inventors: Yifeng Wu, Primit Parikh, Umesh Mishra, Marcia Moore
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Patent number: 7888732Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.Type: GrantFiled: April 11, 2008Date of Patent: February 15, 2011Assignee: Texas Instruments IncorporatedInventors: Marie Denison, Taylor Rice Efland
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Patent number: 7875951Abstract: A semiconductor with active component and method for manufacture. One embodiment provides a semiconductor component arrangement having an active semiconductor component and a semiconductor body having a first semiconductor zone, a third semiconductor zone, and also a drift zone arranged between the first semiconductor zone and the third semiconductor zone. A patterned fourth semiconductor zone doped complementarily to the drift zone is arranged in the drift zone. A potential control structure is provided, which is connected to the patterned fourth semiconductor zone. The potential control structure is designed to connect the patterned fourth semiconductor zone, in the off state of the semiconductor component, to an electrical potential lying between the electrical potential of the first semiconductor zone and the electrical potential of the third semiconductor zone.Type: GrantFiled: December 12, 2007Date of Patent: January 25, 2011Assignee: Infineon Technologies Austria AGInventors: Walter Rieger, Franz Hirler
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Patent number: 7833876Abstract: In a manufacturing of a semiconductor device, at least one of elements is formed in each of element formation regions of a substrate having a main side and a rear side, and the substrate is thinned by polished from a rear side of the substrate, and then, multiple trenches are formed on the rear side of the substrate, so that each trench reaches the main side of the substrate. After that, an insulating material is deposited over an inner surface of each trench to form an insulating layer in the trench, so that the element formation regions are isolated. Thereby, generation of cracks and structural steps in the substrate and separation of element formation regions from the substrate can be suppressed.Type: GrantFiled: August 26, 2008Date of Patent: November 16, 2010Assignee: DENSO CORPORATIONInventors: Nozomu Akagi, Yasuhiro Kitamura, Tetsuo Fujii
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Patent number: 7816731Abstract: In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.Type: GrantFiled: January 20, 2009Date of Patent: October 19, 2010Assignee: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Wayne Bryan Grabowski
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Publication number: 20100259321Abstract: Embodiments include but are not limited to apparatuses and systems including a field-effect transistor switch. A field-effect transistor switch may include a first field plate coupled with a gate electrode, the first field plate disposed substantially equidistant from a source electrode and a drain electrode. The field-effect transistor switch may also include a second field plate proximately disposed to the first field plate and disposed substantially equidistant from the source electrode and the drain electrode. The first and second field plates may be configured to reduce an electric field between the source electrode and the gate electrode and between the drain electrode and the gate electrode.Type: ApplicationFiled: April 14, 2009Publication date: October 14, 2010Applicant: TRIQUINT SEMICONDUCTOR, INC.Inventors: Hua-Quen Tserng, Deep C. Dumka, Martin E. Jones, Charles F. Campbell, Anthony M. Balistreri
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Publication number: 20100230745Abstract: A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer, at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer, at least one insulator buried in the at least one trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semicoType: ApplicationFiled: February 26, 2010Publication date: September 16, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Syotaro ONO, Hiroshi OHTA, Munehisa YABUZAKI, Nana HATANO, Miho WATANABE
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Patent number: 7791132Abstract: A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: GrantFiled: January 4, 2010Date of Patent: September 7, 2010Assignee: Power Integrations, Inc.Inventors: Sujit Banerjee, Donald Ray Disney
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Patent number: 7786533Abstract: A high-voltage transistor includes a drain, a source, and one or more drift regions extending from the drain toward the source. A field plate member laterally surrounds the drift regions and is insulated from the drift regions by a dielectric layer. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).Type: GrantFiled: February 3, 2005Date of Patent: August 31, 2010Assignee: Power Integrations, Inc.Inventor: Donald Ray Disney
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Patent number: 7750428Abstract: A semiconductor device with a field ring in an edge pattern of a semiconductor body with a central cell area and with field plate discharge pattern. The edge pattern exhibits at least one horizontal field plate which is arranged with one end over the field ring and with its other end on insulating layers towards the edge of the semiconductor body. A first ring-shaped area of a type of conduction doped complementary to a drift section material exhibits a field ring effect. A second highly doped ring-shaped area which contacts the one end of the horizontal field plate and forms a pn junction with the first ring-shaped area and which is arranged within the first area exhibits a locally limited punch-through effect or a resistive contact to the drift section material.Type: GrantFiled: April 30, 2008Date of Patent: July 6, 2010Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Elmar Falck, Hans-Joachim Schulze
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Patent number: 7737524Abstract: In a lateral thin-film Silicon-On-Insulator (SOI) device, a field plate is provided to extend substantially over a lateral drift region to protect the device from package and surface charge effects. In particular, the field plate comprises a layer of plural metallic regions which are isolated laterally from one another by spacing so as to assume a lateral electric field profile which is established by a volume doping gradient in the silicon drift region.Type: GrantFiled: September 27, 2004Date of Patent: June 15, 2010Assignee: NXP B.V.Inventor: Theodore James Letavic
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Patent number: 7719076Abstract: A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region of a second conductive type positioned in the first ion well. Therefore, a first interface and a second interface between the first ion well and the first doped region are formed, and the first interface and the second interface are respectively positioned near the drain and the source. In addition, the first interface is positioned under a respective field plate to produce a smooth field distribution and to increase the breakdown voltage of the HV transistor device.Type: GrantFiled: August 10, 2007Date of Patent: May 18, 2010Assignee: United Microelectronics Corp.Inventors: Shih-Ming Shu, Chih-Jen Huang, Tun-Jen Cheng, Chao-Yuan Su
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Patent number: 7692263Abstract: A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 m?-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 m?-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.Type: GrantFiled: November 21, 2006Date of Patent: April 6, 2010Assignee: Cree, Inc.Inventors: Yifeng Wu, Primit Parikh, Umesh Mishra
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Patent number: 7692239Abstract: A MIS-type semiconductor device has reduced ON-resistance by securing an overlapping area between the gate electrode and the drift region, and has low switching losses by reducing the feedback capacitance. The MIS-type semiconductor device includes a p-type base region, an n-type drift region, a p+-type stopper region in the base region, a gate insulation film on the base region, a gate electrode on the gate insulation film, an oxide film on the drift region, a field plate on the oxide film, and a source electrode. The position (P) of the impurity concentration peak in base region is located more closely to the drift region. The oxide film is thinner on the side of the gate electrode. The field plate is connected electrically to the source electrode, the spacing (dg) between the gate insulation film and the stopper region is 2.5 ?m or narrower, and the minimum spacing (x) between the drain region and the stopper region is 5.6 ?m or narrower.Type: GrantFiled: May 12, 2006Date of Patent: April 6, 2010Assignee: Fuji Electric Device Technology Co., Ltd.Inventor: Tatsuji Nagaoka
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Patent number: 7675120Abstract: A composite integrated circuit incorporating two LDMOSFETs of unlike designs, with the consequent creation of a parasitic transistor. A multipurpose resistor is integrally built into the composite integrated circuit in order to prevent the parasitic transistor from accidentally turning on. In an intended application of the composite integrated circuit to a startup circuit of a switching-mode power supply, the multipurpose resistor serves as startup resistor for limiting the flow of rush current during the startup period of the switching-mode power supply.Type: GrantFiled: November 10, 2006Date of Patent: March 9, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Keiichi Sekiguchi, Kazuya Aizawa
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Patent number: 7671408Abstract: A vertical drain extended metal-oxide semiconductor field effect (MOSFET) transistor or a vertical double diffused metal-oxide semiconductor (VDMOS) transistor includes: a buried layer having a first conductivity type in a semiconductor backgate having a second conductivity type; an epitaxial (EPI) layer having the first conductivity type and formed above the buried layer; a deep well having the first conductivity type in the EPI layer extending down to the buried layer; at least one shallow well having the second conductivity type in the EPI layer; a shallow implant region having the first conductivity type and formed in the shallow well; a gate electrode having a lateral component extending over an edge of the shallow well and stopping at some spacing from an edge of the shallow implant and having a vertical trench field plate extending vertically into the EPI layer.Type: GrantFiled: July 9, 2008Date of Patent: March 2, 2010Assignee: Texas Instruments IncorporatedInventor: Marie Denison
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Patent number: 7659607Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.Type: GrantFiled: January 4, 2008Date of Patent: February 9, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Iwasaki
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Patent number: 7649223Abstract: An n-type drift region includes an active element region and a peripheral region. A p-type base region is formed at least in the active element region. A trench-type gate electrode is formed in each of the active element region and the peripheral region. An n-type source region formed in the base region. A plurality of p-type column regions is selectively formed separately from one another in each of the active element region and the peripheral region. In a peripheral region, a p-type guard region is formed below the gate electrode. In the active element region, the p-type guard region is not formed below the gate electrode. As a result, it is possible to hold the breakdown voltage in the peripheral region at a higher level than in the active element region while maintaining the low ON resistance due to a superjunction structure and to raise the breakdown voltage performance of the semiconductor device.Type: GrantFiled: June 28, 2007Date of Patent: January 19, 2010Assignee: NEC Electronics CorporationInventor: Yoshiya Kawashima
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Publication number: 20090294891Abstract: A semiconductor layer of a vertical diode is divided into a center region and a surrounding region. An anode electrode contacts a surface of the center region in the semiconductor layer. An insulation layer contacts a surface of the surrounding region in the semiconductor layer. Ring-shaped FLR regions are formed in the surface of the surrounding region in the semiconductor layer. The innermost FLR region extends from an inside to an outside of a boundary between the anode electrode and the insulation layer and extends along the boundary. A shoulder portion is formed in the surface of the semiconductor layer in a manner such that a portion that contacts the insulation layer is higher than a portion that contacts the anode electrode. Flows of holes directed toward the anode electrode pass through a plurality of positions in the shoulder portion.Type: ApplicationFiled: May 22, 2009Publication date: December 3, 2009Inventor: Fumikazu NIWA
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Patent number: 7605446Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.Type: GrantFiled: July 14, 2006Date of Patent: October 20, 2009Assignee: Cambridge Semiconductor LimitedInventors: Florin Udrea, Nishad Udugampola, Gehan A. J. Amaratunga
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Patent number: 7598585Abstract: A structure for preventing leakage of a semiconductor device is provided. The structure comprises a conductive layer, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The conductive layer is wider than the conductive line.Type: GrantFiled: May 24, 2006Date of Patent: October 6, 2009Assignee: Himax Technologies LimitedInventor: Chan-Liang Wu
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Patent number: 7595523Abstract: In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.Type: GrantFiled: February 16, 2007Date of Patent: September 29, 2009Assignee: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Martin H. Manley
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Publication number: 20090189240Abstract: A semiconductor component with at least one field plate. One embodiment provides the field plate to make contact with the semiconductor body at a connection contact. The semiconductor body has in the region of the connection contact a doping concentration that is less than 5·1017 cm?3.Type: ApplicationFiled: January 25, 2008Publication date: July 30, 2009Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Armin Willmeroth, Anton Mauder, Michael Rueb, Franz Hirler
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Patent number: 7566918Abstract: Field effect transistors having a power density of greater than 5 W/mm when operated at a frequency of at least 30 GHz are provided. The power density of at least 5 W/mm may be provided at a drain voltage of 28 V. Transistors with a power density of at least 8 W/mm when operated at 40 GHz at a drain voltage of 28 V are also provided.Type: GrantFiled: February 23, 2006Date of Patent: July 28, 2009Assignee: Cree, Inc.Inventors: Yifeng Wu, Primit Parikh, Marcia Moore
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Patent number: 7564107Abstract: A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.Type: GrantFiled: September 9, 2004Date of Patent: July 21, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Yanagisawa, Satoshi Aida, Shigeo Kouzuki, Hironori Yoshioka, Ichiro Omura, Wataru Saito
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Patent number: 7560787Abstract: In accordance with an embodiment of the invention, a semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. A first silicon region of a first conductivity type extends to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. At least one termination trench is formed in the termination. The termination trench extends into the second silicon region, and is laterally spaced from the first silicon region. An insulating layer lines the sidewalls and bottom of the termination trench. A conductive electrode at least partially fills the termination trench.Type: GrantFiled: December 22, 2005Date of Patent: July 14, 2009Assignee: Fairchild Semiconductor CorporationInventor: Christopher Boguslaw Kocon
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Patent number: RE41866Abstract: There is disclosed a semiconductor device having an MOS gate for reducing variations in threshold voltage (Vth) with time wherein a surface protective film is not formed in a device area including channels but only in a device peripheral area, thereby reducing the amount of hydrogen atoms migrating to a silicon-silicon oxide interface in a cell area and, accordingly, reducing the number of Si—H chemical bonds at the interface.Type: GrantFiled: June 27, 2001Date of Patent: October 26, 2010Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuhiro Yano, Kouichi Mochizuki