With Physical Configuration Of Semiconductor Surface To Reduce Electric Field (e.g., Reverse Bevels, Double Bevels, Stepped Mesas, Etc.) Patents (Class 257/496)
  • Patent number: 10199227
    Abstract: A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: February 5, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Satoru Mayuzumi, Mark Fischer, Michael Violette
  • Patent number: 10186425
    Abstract: In a method of manufacturing a semiconductor device having an oxide film removing step where an oxide film formed on a surface of a semiconductor substrate is partially removed, the oxide film removing step includes: a first step where a resist glass layer is selectively formed on an upper surface of the oxide film without using an exposure step; a second step where the resist glass layer is densified by baking the resist glass layer; and a third step where the oxide film is partially removed using the resist glass layer as a mask, wherein the resist glass layer is made of resist glass which contains at least SiO2, B2O3, Al2O3, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na, K, and Zn.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: January 22, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Atsushi Ogasawara
  • Patent number: 9607851
    Abstract: Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: March 28, 2017
    Assignee: CMSC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Qiang Rui, Shuo Zhang, Genyi Wang, Xiaoshe Deng
  • Patent number: 9601605
    Abstract: A bipolar junction transistor (BJT), which includes a collector layer, a base layer on the collector layer, an emitter layer on the base layer, and a recess region embedded in the collector layer, is disclosed. A base-collector plane is between the base layer and the collector layer. The recess region is may be below the base-collector plane. Further, the recess region and the base layer are a first type of semiconductor material. By embedding the recess region in the collector layer, the recess region and the collector layer form a first P-N junction, which may provide a point of avalanche for the BJT. Further, the collector layer and the base layer form a second P-N junction. By separating the point of avalanche from the second P-N junction, the BJT may avalanche robustly, thereby reducing the likelihood of avalanche induced failures, particularly in silicon carbide (SiC) BJTs.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: March 21, 2017
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal, Lin Cheng
  • Patent number: 9525021
    Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: December 20, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Byron Lovell Williams
  • Patent number: 9368674
    Abstract: A method for fabricating an epitaxial structure includes providing a wafer comprising one or more epitaxial layers. The wafer is divided into dice where the area between the dice are called streets. Each street has a slot formed on either side of the street. The slots penetrate through the epitaxial layer but not the substrate leaving a portion of the epitaxial layer intact between the slots creating a “W” shaped cross section. A protective layer is then formed on the wafer. A laser may be used to singulate the wafer in to individual dice. The laser divides each street between the slots. The barrier walls of the epitaxial layers protect the individual dice from debris created by laser separation.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: June 14, 2016
    Assignee: Koninklijke Philips N.V.
    Inventors: Songnan Wu, Boris Kharas
  • Patent number: 9356140
    Abstract: A device comprises a substrate, an n-layer and a p-layer, an n-electrode, and a p-electrode. A step is formed at an outer circumference of the device. A protective film is formed so as to continuously cover a side surface and a bottom surface of the step. A field plate electrode connected with the p-electrode is formed on the protective film. When a distance from the pn junction interface to the surface of the protective film on the bottom surface of the step is defined as h (?m), a dielectric constant of the protective film is defined as ?s, and a thickness of the protective film at the pn junction interface on the side surface of the step is defined as d (?m), (?s·h)/d is 4 or more, and ?s/d is 3 (1/?m) or more.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: May 31, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yukihisa Ueno, Toru Oka
  • Patent number: 9349797
    Abstract: The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (m?·cm2) and even more preferably less than 5 m?·cm2. In another embodiment, the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 m?·cm2 and even more preferably less than 7 m?·cm2. In yet another embodiment, the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 m?·cm2 and even more preferably less than 10 m?·cm2. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: May 24, 2016
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant K. Agarwal, Michael John O'Loughlin, Albert Augustus Burk, Jr., John Williams Palmour
  • Patent number: 9337268
    Abstract: A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: May 10, 2016
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Craig Capell, Anant Agarwal, Sei-Hyung Ryu
  • Patent number: 9306004
    Abstract: A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: April 5, 2016
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Craig Capell, Anant Agarwal, Sei-Hyung Ryu
  • Patent number: 9112022
    Abstract: A super junction semiconductor device includes a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction. Each one of the first areas includes a first semiconductor region of a first conductivity type. Each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type. A width w1 of the first of the first semiconductor region in a transistor cell area is greater than in an edge termination area, and a width w2 of each one of the second semiconductor regions in the transistor cell area is greater than in the edge termination area.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: August 18, 2015
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Hans Weber
  • Patent number: 9064738
    Abstract: Methods of forming a power semiconductor device having an edge termination are provided in which the power semiconductor device that has a drift region of a first conductivity type is formed on a substrate. A junction termination extension is formed on the substrate adjacent the power semiconductor device, the junction termination extension including a plurality of junction termination zones that are doped with dopants having a second conductivity type. The junction termination zones have different effective doping concentrations. A dopant activation process is performed to activate at least some of the dopants in the junction termination zones. An electrical characteristic of the power semiconductor device is measured. Then, the junction termination extension is etched in order to reduce the effective doping concentration within the junction termination extension.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: June 23, 2015
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Vipindas Pala, Lin Cheng, Anant Kumar Agarwal
  • Patent number: 8994141
    Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Takami Otsuki
  • Patent number: 8993426
    Abstract: The invention provides a semiconductor device with a junction termination extension structure on a mesa and a method of fabricating the same. The device comprises: a type-I semiconductor substrate having a first surface and a second surface; a type-I epitaxial layer disposed on the first surface; at least one depression disposed on the type-I epitaxial layer; a mesa-type junction termination extension structure surrounding the at least one depression wherein the mesa-type junction termination extension structure is of type-II; and at least one semiconductor component formed one the depression.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: March 31, 2015
    Inventor: Chii-Wen Jiang
  • Patent number: 8969949
    Abstract: The present disclosure provides one embodiment of a SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters. The pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel.
    Type: Grant
    Filed: March 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Yi-Ren Chen, Ming Zhu
  • Patent number: 8890293
    Abstract: A guard ring for a through via, and a method of manufacture thereof, is provided. The guard ring comprises one or more rings around a through via, wherein the rings may be, for example, circular, rectangular, octagon, elliptical, square, or the like. The guard ring may be formed from a contact through an inter-layer dielectric layer and interconnect structures (e.g., vias and lines) extending through the inter-metal dielectric layers. The guard ring may contact a well formed in the substrate.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Lu, Song-Bor Lee, Ching-Chen Hao
  • Patent number: 8878331
    Abstract: A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: November 4, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Mickael Gros-Jean, Clement Gaumer, Emmanuel Bayard Perrin
  • Publication number: 20140319646
    Abstract: An electronic device includes a semiconductor layer, a primary junction in the semiconductor layer, a lightly doped region surrounding the primary junction and a junction termination structure in the lightly doped region adjacent the primary junction. The junction termination structure has an upper boundary, a side boundary, and a corner between the upper boundary and the side boundary, and the lightly doped region extends in a first direction away from the primary junction and normal to a point on the upper boundary by a first distance that is smaller than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner. At least one floating guard ring segment may be provided in the semiconductor layer outside the corner of the junction termination structure. Related methods are also disclosed.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Inventors: Jason Henning, Qingchun Zhang, Sie-Hyung Ryu
  • Publication number: 20140312452
    Abstract: A termination region structure of a semiconductor device is provided, which includes: a semiconductor layer; a plurality of trenches, formed on a surface of the semiconductor layer; a connecting trench, formed on the surface of the semiconductor layer, for connecting two adjacent trenches in the plurality of trenches; a first insulating layer, formed on surfaces of the plurality of trenches, the connecting trench, and the semiconductor layer; a conductive material, formed in the plurality of trenches and the connecting trench; a second insulating layer, covering part of a surface of the first insulating layer and part of a surface of the conductive material; and a metal layer, covering part of a surface of the second insulating layer.
    Type: Application
    Filed: April 18, 2014
    Publication date: October 23, 2014
    Applicant: ECONOMIC SEMICONDUCTOR CORPORATION
    Inventor: WEN-BIN LIN
  • Patent number: 8853782
    Abstract: A semiconductor device has a so-called SOI structure in which an element is constituted by a semiconductor layer on an insulating surface, and the semiconductor layer is extremely thin as 5 nm to 30 nm. The semiconductor device is provided with a field effect transistor that includes in addition to such a semiconductor layer, a gate insulating layer with a thickness of 2 nm to 20 nm and a gate electrode, and a channel length is ten times or more and less than 40 times the thickness of the semiconductor layer. When the semiconductor layer is formed to be thin, the semiconductor device operates so as not to be easily influenced by a concentration of impurity imparting one conductivity type added to a channel formation region.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: October 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Patent number: 8803278
    Abstract: A semiconductor device includes a semiconductor substrate, a surface electrode formed on the semiconductor substrate, an ineffective region formed to surround the surface electrode, and an ID-indicating portion made of a different material than the surface electrode and formed on the surface electrode to indicate an ID. The area of the ineffective region is smaller than the area of the surface electrode.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: August 12, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuo Ata, Takahiro Okuno, Tetsujiro Tsunoda
  • Patent number: 8803277
    Abstract: An electronic device includes a semiconductor layer, a primary junction in the semiconductor layer, a lightly doped region surrounding the primary junction and a junction termination structure in the lightly doped region adjacent the primary junction. The junction termination structure has an upper boundary, a side boundary, and a corner between the upper boundary and the side boundary, and the lightly doped region extends in a first direction away from the primary junction and normal to a point on the upper boundary by a first distance that is smaller than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner. At least one floating guard ring segment may be provided in the semiconductor layer outside the corner of the junction termination structure. Related methods are also disclosed.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: August 12, 2014
    Assignee: Cree, Inc.
    Inventors: Jason Henning, Qingchun Zhang, Sei-Hyung Ryu
  • Publication number: 20140145292
    Abstract: The invention provides a semiconductor device with a junction termination extension structure on a mesa and a method of fabricating the same. The device comprises: a type-I semiconductor substrate having a first surface and a second surface; a type-I epitaxial layer disposed on the first surface; at least one depression disposed on the type-I epitaxial layer; a mesa-type junction termination extension structure surrounding the at least one depression wherein the mesa-type junction termination extension structure is of type-II; and at least one semiconductor component formed one the depression.
    Type: Application
    Filed: January 11, 2013
    Publication date: May 29, 2014
    Inventor: CHII-WEN JIANG
  • Patent number: 8723219
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra10 nm and Ra5 ?m at edges of wafers.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: May 13, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro Nakayama, Masato Irikura
  • Patent number: 8710617
    Abstract: In a region located between a collector electrode and a semiconductor substrate, there are a portion where a hollow region is located and a portion where no hollow region is located. Between the collector electrode and the portion where no hollow region is located in the semiconductor substrate, a floating silicon layer electrically isolated by insulating films is formed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 29, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Junichi Yamashita, Tomohide Terashima
  • Patent number: 8648445
    Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 11, 2014
    Assignee: Agere Systems LLC
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 8564088
    Abstract: In a semiconductor body, a semiconductor device has an active region with a vertical drift section of a first conduction type and a near-surface lateral well of a second, complementary conduction type. An edge region surrounding this active region comprises a variably laterally doped doping material zone (VLD zone). This VLD zone likewise has the second, complementary conduction type and adjoins the well. The concentration of doping material of the VLD zone decreases to the concentration of doping material of the drift section along the VLD zone towards a semiconductor chip edge. Between the lateral well and the VLD zone, a transitional region is provided which contains at least one zone of complementary doping located at a vertically lower point than the well in the semiconductor body.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: October 22, 2013
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Schmidt
  • Publication number: 20130256826
    Abstract: An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.
    Type: Application
    Filed: April 2, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Mark D. Levy, John C. Malinowski
  • Patent number: 8536623
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, an HEMT stack spaced apart from the substrate, and a pseudo-insulation layer (PIL) disposed between the substrate and the HEMT stack. The PIL layer includes at least two materials having different phases. The PIL layer defines an empty space that is wider at an intermediate portion than at an entrance of the empty space.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: September 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Jae-won Lee, Hyo-ji Choi
  • Patent number: 8497552
    Abstract: A semiconductor device may include a semiconductor buffer layer having a first conductivity type and a semiconductor mesa having the first conductivity type on a surface of the buffer layer. In addition, a current shifting region having a second conductivity type may be provided adjacent a corner between the semiconductor mesa and the semiconductor buffer layer, and the first and second conductivity types may be different conductivity types. Related methods are also discussed.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 30, 2013
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Patent number: 8487372
    Abstract: A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of dual trench MOSFETs connected together with multiple sawing trenched gates across a space between the two trench MOSFETs having a width same as scribe line.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: July 16, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8482032
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 ?m at edges of wafers.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: July 9, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro Nakayama, Masato Irikura
  • Publication number: 20130154048
    Abstract: A guard ring for a through via, and a method of manufacture thereof, is provided. The guard ring comprises one or more rings around a through via, wherein the rings may be, for example, circular, rectangular, octagon, elliptical, square, or the like. The guard ring may be formed from a contact through an inter-layer dielectric layer and interconnect structures (e.g., vias and lines) extending through the inter-metal dielectric layers. The guard ring may contact a well formed in the substrate.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Lu, Song-Bor Lee, Ching-Chen Hao
  • Patent number: 8431460
    Abstract: A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: April 30, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shin-Chuan Huang, Guang-Yaw Hwang, Hsiang-Ying Wang, Yu-Hsiang Hung, I-Chang Wang
  • Patent number: 8426945
    Abstract: To provide a semiconductor device in which a channel formation region can be thinned without adversely affecting a source region and a drain region through a simple process and a method for manufacturing the semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film, having a thickness smaller than a height of a projection of a substrate, is formed over a surface of the substrate having the projections; the semiconductor film is etched to have an island shape with a resist used as a mask; the resist is etched to expose a portion of the semiconductor film which covers a top surface of the projection; and the exposed portion of the semiconductor film is etched to be thin, while the adjacent portions of the semiconductor film on both sides of the projection remain covered with the resist.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: April 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaharu Nagai, Takafumi Mizoguchi
  • Patent number: 8390030
    Abstract: A semiconductor device includes: a first semiconductor layer made of an AlxGa1?xN (0?×<1); a second semiconductor layer provided on the first semiconductor layer and made of an undoped or first conductivity type AlyGa1?yN (0<y?1, x<y); an anode electrode and a cathode electrode which are connected to the second semiconductor layer; and a third semiconductor layer of second conductivity type provided between the anode electrode and the cathode electrode when viewed from a direction perpendicular to an upper surface of the second semiconductor layer. The third semiconductor layer is depleted when a predetermined magnitude or more of voltage is applied between the anode electrode and the cathode electrode.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Hidetoshi Fujimoto, Takao Noda, Yasunobu Saito, Tomohiro Nitta
  • Publication number: 20130020672
    Abstract: A method and an electronic device structure comprising at least one access lead to adapted to be connected to an electrical circuit; at least one substrate region; at least one semiconductor die positioned on the substrate; the at least one semiconductor die being operatively connected to the at least one access lead; a dielectric region extending below the at least one semiconductor die; the dielectric region being formed by creating a cavity in the at least one substrate region; whereby the dielectric region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 24, 2013
    Applicant: U.S. Govermment as represented by the Secretary of the Army
    Inventors: Charles W. Tipton, Oladimeji O. Ibitayo
  • Publication number: 20130009273
    Abstract: A semiconductor device and a method for fabricating a semiconductor device are provided. The method for fabricating a semiconductor device includes forming an isolation layer over a semiconductor substrate defining first and second regions, etching the isolation layer at an edge of the first region to form a guard ring pattern, forming a buried guard ring filling the guard ring pattern, selectively etching the isolation layer of the first region to form a plurality of patterns, forming a plurality of conductive patterns in the respective patterns, and completely removing the isolation layer of the first region through a dip-out process.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Inventors: Jin-A KIM, Seok-Ho Jie
  • Publication number: 20130009272
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element disposed in the semiconductor substrate, a guard ring surrounding at least a part of a periphery of the semiconductor element, a guard ring terminal coupled with the guard ring, a power supply line divided from a line coupled with a power source and applying a first constant voltage to the semiconductor element based on a voltage generated by the power source, a guard ring terminal fixation line divided from the line coupled with the power source and applying a second constant voltage to the guard ring terminal, a bypass capacitor disposed on the guard ring terminal fixation line so as to be coupled in parallel with the guard ring, and a resistor disposed on the guard ring terminal fixation line between the power source and the bypass capacitor.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 10, 2013
    Applicant: DENSO CORPORATION
    Inventors: Shinya SAKURAI, Akira Yamada
  • Patent number: 8350366
    Abstract: A power semiconductor component having a pn junction, a body with a first basic conductivity, a well-like region with a second conductivity which is arranged horizontally centrally in the body, has a first two-level doping profile and has a first penetration depth from the first main surface into the body. In addition, this power semiconductor component has an edge structure which is arranged between the well-like region and the edge of the power semiconductor component and which comprises a plurality of field rings with a single-level doping profile, a second conductivity and a second penetration depth, wherein the first penetration depth is no more than about 50% of the second penetration depth.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: January 8, 2013
    Assignee: Semikron Elektronik GmbH & Co., KG
    Inventor: Bernhard Koenig
  • Patent number: 8314471
    Abstract: In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to disperse an electric field.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: November 20, 2012
    Assignee: Diodes Incorporated
    Inventors: Chiao-Shun Chuang, Tony Huang
  • Patent number: 8283749
    Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 9, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20120205666
    Abstract: An electronic device includes a semiconductor layer, a primary junction in the semiconductor layer, a lightly doped region surrounding the primary junction and a junction termination structure in the lightly doped region adjacent the primary junction. The junction termination structure has an upper boundary, a side boundary, and a corner between the upper boundary and the side boundary, and the lightly doped region extends in a first direction away from the primary junction and normal to a point on the upper boundary by a first distance that is smaller than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner. At least one floating guard ring segment may be provided in the semiconductor layer outside the corner of the junction termination structure. Related methods are also disclosed.
    Type: Application
    Filed: February 10, 2011
    Publication date: August 16, 2012
    Inventors: Jason Henning, Qingchun Zhang, Sei-Hyung Ryu
  • Patent number: 8212323
    Abstract: A seal ring structure for an integrated circuit includes a seal ring being disposed along a periphery of the integrated circuit and being divided into at least a first portion and a second portion, wherein the second portion is positioned facing an analog and/or RF circuit block and is different from the first portion in structure. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: July 3, 2012
    Assignee: Mediatek Inc.
    Inventors: Tung-Hsing Lee, Tien-Chang Chang, Yuan-Hung Chung
  • Patent number: 8183669
    Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: May 22, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Hidenori Mikami, Naoki Matsumoto
  • Patent number: 8143679
    Abstract: A semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. The termination region includes a first silicon region of a first conductivity type extending to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. The second silicon region has a recessed portion extending below the first depth and out to an edge of a die housing the semiconductor power device. The recessed portion forms a vertical wall at which the first silicon region terminates. A first conductive electrode extends into the recessed portion and is insulated from the second silicon region.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: March 27, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Christopher Boguslaw Kocon
  • Publication number: 20120061793
    Abstract: A parasitic PNP bipolar transistor, wherein a base region includes a first and a second region; the first region is formed in an active area, has a depth larger than shallow trench field oxides, and has its bottom laterally extended into the bottom of the shallow trench field oxides on both sides of an active area; the second region is formed in an upper part of the first region and has a higher doping concentration; an N-type and a P-type pseudo buried layer is respectively formed at the bottom of the shallow trench field oxides; a deep hole contact is formed on top of the N-type pseudo buried layer to pick up the base; the P-type pseudo buried layer forms a collector region separated from the active area by a lateral distance; an emitter region is formed by a P-type SiGe epitaxial layer formed on top of the active area.
    Type: Application
    Filed: September 8, 2011
    Publication date: March 15, 2012
    Inventors: Donghua Liu, Wensheng Qian
  • Patent number: 8120059
    Abstract: A nitride semiconductor substrate includes a front surface, a rear surface on an opposite side to the front surface, and a first edge portion including a chamfered edge on the front surface. A ratio of an average surface roughness of the front surface to an average surface roughness of the first edge portion is not more than 0.01.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: February 21, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Kazutoshi Watanabe, Takehiro Yoshida
  • Patent number: 8105911
    Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: January 31, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 8097919
    Abstract: An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P?N junction with the drift layer, and a junction termination extension region having the second conductivity type in the drift layer adjacent the P?N junction. The buffer layer includes a step portion that extends over a buried portion of the junction termination extension. Related methods are also disclosed.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: January 17, 2012
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal