With Physical Configuration Of Semiconductor Surface To Reduce Electric Field (e.g., Reverse Bevels, Double Bevels, Stepped Mesas, Etc.) Patents (Class 257/496)
  • Patent number: 8093676
    Abstract: A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A first semiconductor zone of a first conduction type is arranged in the inner region and in the edge region. A second semiconductor zone of a second conduction type is arranged in the inner region and adjacent to the first semiconductor zone. A trench is arranged in the edge region and has first and second sidewalls and a bottom, and extends into the semiconductor body. A doped first sidewall zone of the second conduction type is adjacent to the first sidewall of the trench. A doped second sidewall zone of the second conduction type is adjacent to the second sidewall of the trench. A doped bottom zone of the second conduction type is adjacent to the bottom of the trench. Doping concentrations of the sidewall zones are lower than a doping concentration of the bottom zone.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: January 10, 2012
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Schmidt
  • Patent number: 8080858
    Abstract: A Semiconductor component having a space saving edge structure is disclosed. One embodiment provides a first side, a second side, an inner region, an edge region adjoining the inner region in a lateral direction of the semiconductor body, and a first semiconductor layer extending across the inner region and the edge region and having a basic doping of a first conductivity type. At least one active component zone of a second conductivity type, which is complementary to the first conductivity type, is disposed in the inner region in the first semiconductor layer. An edge structure is disposed in the edge region and includes at least one trench extending from the first side into the semiconductor body. An edge electrode is disposed in the trench, a dielectric layer is disposed in the trench between the edge electrode and the semiconductor body, a first edge zone of the second conductivity type adjoin the trench and are at least partially disposed below the trench.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: December 20, 2011
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Ralf Siemieniec, Christian Geissler
  • Publication number: 20110298081
    Abstract: A semiconductor device includes a semiconductor substrate, a surface electrode formed on the semiconductor substrate, an ineffective region formed to surround the surface electrode, and an ID-indicating portion made of a different material than the surface electrode and formed on the surface electrode to indicate an ID. The area of the ineffective region is smaller than the area of the surface electrode.
    Type: Application
    Filed: April 1, 2011
    Publication date: December 8, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuo ATA, Takahiro Okuno, Tetsujiro Tsunoda
  • Patent number: 8063467
    Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a first protrusion and a cavity having a boundary that is below a surface of the semiconductor material, wherein the first protrusion extends from the boundary of the cavity. The method further includes forming a non-conformal material over a first portion of the first protrusion using an angled deposition of the non-conformal material, wherein the angle of deposition of the non-conformal material is non-perpendicular to the surface of the semiconductor material. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: November 22, 2011
    Assignee: HVVi Semiconductors, Inc.
    Inventor: Michael Albert Tischler
  • Publication number: 20110278693
    Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.
    Type: Application
    Filed: July 26, 2011
    Publication date: November 17, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Martin B. Mollat, Tony Thanh Phan
  • Patent number: 7999343
    Abstract: An arrangement for use in a semiconductor component includes a semiconductor body and an edge structure. The semiconductor body having a first face, a second face, a first semiconductor zone of a first conductance type, at least one second semiconductor zone of a second conductance type, and a semiconductor junction formed therebetween running substantially parallel to the first face. The edge structure is laterally adjacent to the second semiconductor zone and includes at least a first trench. The first trench extends in a vertical direction into the semiconductor body and is filled with a dielectric material. The edge structure further includes a third semiconductor zone of the second conductance type, which, at least partially, is adjacent to a face of the at least one trench which faces away from the first face. The edge structure further includes a fourth semiconductor zone of the first conductance type, which is more heavily doped than the first semiconductor zone, and is proximate to the first face.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: August 16, 2011
    Assignee: Infineon Technologies AG
    Inventors: Jenoe Tihanyi, Nada Tihanyi, legal representative
  • Patent number: 7999347
    Abstract: A semiconductor layer of a vertical diode is divided into a center region and a surrounding region. An anode electrode contacts a surface of the center region in the semiconductor layer. An insulation layer contacts a surface of the surrounding region in the semiconductor layer. Ring-shaped FLR regions are formed in the surface of the surrounding region in the semiconductor layer. The innermost FLR region extends from an inside to an outside of a boundary between the anode electrode and the insulation layer, and extends along the boundary. A shoulder portion is formed in the surface of the semiconductor layer in a manner such that a portion that contacts the insulation layer is higher than a portion that contacts the anode electrode. Flows of holes directed toward the anode electrode pass through a plurality of positions in the shoulder portion.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: August 16, 2011
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Fumikazu Niwa
  • Patent number: 7982296
    Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: July 19, 2011
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
  • Patent number: 7928347
    Abstract: A heating unit includes an AlN substrate having a main surface on which an elongated heat-generating resistor is provided. A protection layer is formed on the main surface of the substrate for the heat-generating resistor. The protection layer includes a first cover layer covering the heat-generating resistor and a second cover layer covering the first cover layer. The first cover layer is made of crystallized or semi-crystallized glass having a higher crystallization temperature by at least 50° C. than the softening point of the glass. The second cover layer is made of non-crystalline glass.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: April 19, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Teruhisa Sako
  • Patent number: 7923767
    Abstract: Shallow trench isolation regions are positioned between NAND strings (or other types of non-volatile storage). These isolation regions include sections that form concave cut-out shapes in the substrate for the NAND string (or other types of non-volatile storage). The floating gates (or other charge storage devices) of the NAND strings hang over the sections of the isolation region that form the concave cut-out shape in the substrate. To manufacture such a structure, a two step etching process is used to form the isolation regions. In the first step, isotropic etching is used to remove substrate material in multiple directions, including removing substrate material underneath the floating gates. In the second step, anisotropic etching is used to create the lower part of the isolation region.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: April 12, 2011
    Assignee: SanDisk Corporation
    Inventor: Masaaki Higashitani
  • Patent number: 7915705
    Abstract: A SiC semiconductor device includes: a SiC substrate; a SiC drift layer on the substrate having an impurity concentration lower than the substrate; a semiconductor element in a cell region of the drift layer; an outer periphery structure including a RESURF layer in a surface portion of the drift layer and surrounding the cell region; and an electric field relaxation layer in another surface portion of the drift layer so that the electric field relaxation layer is separated from the RESURF layer. The electric field relaxation layer is disposed on an inside of the RESURF layer so that the electric field relaxation layer is disposed in the cell region. The electric field relaxation layer has a ring shape.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: March 29, 2011
    Assignee: Denso Corporation
    Inventors: Takeo Yamamoto, Eiichi Okuno
  • Patent number: 7902637
    Abstract: A nano structure formed on the surface of a substrate containing Si and having a pattern of at least 2 ?m in depth, in which Ga or In is contained in the surface of the pattern, and the Ga or the In has a concentration distribution that an elemental composition ratio Ga/Si or In/Si of Si and Ga or In detected by an X-ray photoelectron spectroscopy is at least 0.4 atomic percent in the depth direction of the substrate, and the maximum value of the concentration is positioned within 50 nm of the surface of the pattern.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: March 8, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Taiko Motoi, Kenji Tamamori, Shinan Wang, Masahiko Okunuki, Haruhito Ono, Toshiaki Aiba, Nobuki Yoshimatsu
  • Patent number: 7880260
    Abstract: A semiconductor device includes an active region with a vertical drift path of a first conduction type and with a near-surface lateral well of a second, complementary conduction type. In addition, the semiconductor device has an edge region surrounding the active region. This edge region has a variable lateral doping material zone of the second conduction type, which adjoins the well. A transition region in which the concentration of doping material gradually decreases from the concentration of the well to the concentration at the start of the variable lateral doping material zone is located between the lateral well and the variable lateral doping material zone.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: February 1, 2011
    Assignee: Infineon Technology Austria AG
    Inventors: Elmar Falck, Josef Bauer, Gerhard Schmidt
  • Patent number: 7872331
    Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: January 18, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Hidenori Mikami, Naoki Matsumoto
  • Patent number: 7872297
    Abstract: The present invention relates to a flash memory device and its fabrication method. The device comprises a structure for improving a scaling-down characteristic/performance and increasing memory capacity of the MOS-based flash memory device. A new device structure according to the present invention is based on a recessed channel capable of implementing highly-integrated/high-performance and 2-bit/cell. The proposed device suppresses the short channel effect, reduces the cell area, and enables 2-bit/cell by forming the charge storage node as a spacer inside the recessed channel. Moreover, if selectively removing the dielectric films around the recessed silicon surface, the sides as well as the surface of the recessed channel is exposed. A spacer can be used as a storage node, thereby improving the channel controllability of the control electrode and the on-off characteristic of a device. The proposed structure also resolves the threshold voltage problem and improves the write/erase speeds.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: January 18, 2011
    Assignee: SNU R&DB Foundation
    Inventor: Jong-Ho Lee
  • Patent number: 7825017
    Abstract: A silicon carbide semiconductor device provided as a semiconductor chip includes a substrate, a drift layer on the substrate, an insulation film on the drift layer, a semiconductor element formed in a cell region of the drift layer, a surface electrode formed on the drift layer and electrically coupled to the semiconductor element through an opening of the insulation film, and a passivation film formed above the drift layer around the periphery of the cell region to cover an outer edge of the surface electrode. The passivation film has an opening through which the surface electrode is exposed outside. A surface of the passivation film is made uneven to increase a length from an inner edge of the opening of the passivation film to a chip edge measured along the surface of the passivation film.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: November 2, 2010
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeo Yamamoto, Takeshi Endo, Eiichi Okuno, Masaki Konishi
  • Publication number: 20100264427
    Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.
    Type: Application
    Filed: July 1, 2010
    Publication date: October 21, 2010
    Applicant: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20100244179
    Abstract: A method and structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.
    Type: Application
    Filed: March 26, 2009
    Publication date: September 30, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Steven H. VOLDMAN
  • Patent number: 7800196
    Abstract: An exemplary edge termination structure maintains the breakdown voltage of the semiconductor device after it has been sawed off the wafer and packaged by creating an electric field stop layer at a periphery of the semiconductor device. The electric field stop layer has a dopant concentration higher than that of the layer in which an edge termination is implemented, such as a drift layer or a channel layer. The electric field stop layer may be created by selectively masking the peripheries of the device during the device processing, i.e., mesa etch, to protect and preserve the highly doped material at the peripheries of the device.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: September 21, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventors: John Victor D. Veliadis, Ty R. McNutt
  • Patent number: 7791176
    Abstract: A power semiconductor component and method for producing it. The component has a semiconductor base body with a first doping and a pn junction formed by a contact region having a second doping with a doping profile in the base body. The second contact region is arranged at a second surface of the base body and extends into the base body. The base body has a trench-type cutout with an edge area and a base area, wherein the base area is formed as a second partial area of the second surface, and wherein the second contact region extends from the base area via the edge area as far as a first partial area. Furthermore, the pn junction has a curvature adjacent to the edge area.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: September 7, 2010
    Assignee: SEMIKRON Elektronik GmbH & Co. KG
    Inventor: Bernhard König
  • Publication number: 20100213568
    Abstract: The present invention discloses a MEMS device with guard ring, and a method for making the MEMS device. The MEMS device comprises a bond pad and a sidewall surrounding and connecting with the bond pad, characterized in that the sidewall forms a guard ring by an etch-resistive material.
    Type: Application
    Filed: February 24, 2009
    Publication date: August 26, 2010
    Inventors: Hsin Hui Hsu, Sheng Ta Lee, Chuan Wei Wang
  • Patent number: 7759769
    Abstract: A semiconductor structure of a high side driver includes an ion-doped junction. The ion-doped junction includes a substrate and a deep well. The deep well is formed in the substrate and has a first concave structure. The ion-doped junction includes a semiconductor region connected to the first concave structure of the deep well and having substantially the same ion-doping concentration as the substrate.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: July 20, 2010
    Assignee: System General Corp.
    Inventors: Chiu-Chih Chiang, Chih-Feng Huang
  • Patent number: 7714407
    Abstract: A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a part of the dielectric layer above the drift region, the electrical conductor being connected or connectable to the high voltage terminal end. The drift region has plural trenches positioned below the electrical conductor. The trenches extend laterally across at least a part of the drift region in the direction transverse the direction between the high and low voltage terminal ends of the semiconductor layer, each trench containing a dielectric material. The trenches improve the distribution of electric field in the device in the presence of the electrical conductor.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: May 11, 2010
    Assignee: Cambridge Semiconductor Limited
    Inventors: Florin Udrea, Cerdin Lee
  • Publication number: 20100078755
    Abstract: An exemplary edge termination structure maintains the breakdown voltage of the semiconductor device after it has been sawed off the wafer and packaged by creating an electric field stop layer at a periphery of the semiconductor device. The electric field stop layer has a dopant concentration higher than that of the layer in which an edge termination is implemented, such as a drift layer or a channel layer. The electric field stop layer may be created by selectively masking the peripheries of the device during the device processing, i.e., mesa etch, to protect and preserve the highly doped material at the peripheries of the device.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: John Victor Veliadis, Ty R. McNutt
  • Patent number: 7652307
    Abstract: In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: January 26, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Kiyofumi Nakaya, Shigeaki Okawa
  • Patent number: 7635892
    Abstract: A semiconductor device has a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a recess defined in the second main surface by side surfaces and a bottom surface, a semiconductor region provided in the bottom surface of the recess of the semiconductor substrate, semiconductor regions provided in the surface of a peripheral region on the second main surface side, and insulating films provided on the side surfaces of the recess to electrically insulate the semiconductor regions.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: December 22, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norifumi Tokuda, Shigeru Kusunoki
  • Patent number: 7598586
    Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity; and a semiconductor layer provided on the semiconductor substrate and having a super junction structure including drift layers of the first conductivity and RESURF layers of a second conductivity different from the first conductivity, the drift layers and the RESURF layers being laterally arranged in alternate relation parallel to the semiconductor substrate, the RESURF layers being each provided alongside an interior side wall of a trench penetrating through the semiconductor layer, the drift layers each having an isolation region present between the RESURF layer and the semiconductor substrate to prevent the RESURF layer from contacting the semiconductor substrate.
    Type: Grant
    Filed: December 24, 2004
    Date of Patent: October 6, 2009
    Assignee: ROHM Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 7589393
    Abstract: A semiconductor structure of a high side driver includes an ion-doped junction. The ion-doped junction includes a substrate, a first deep well and a second deep well, a first heavy ion-doped region and a second heavy ion-doped region. The first deep well and second deep well are formed in the substrate, which are separated but partially linked with each other, and the first deep well and the second deep well have the same ion-doped type. The first heavy ion-doped region is formed in the first deep well for connecting to a first high voltage, and the first heavy ion-doped region has the same ion-doped type as the first deep well. The second heavy ion-doped region is formed in the second deep well for connecting to a second high voltage, and the second heavy ion-doped region has the same ion-doped type as the first deep well.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: September 15, 2009
    Assignee: System General Corporation
    Inventors: Chiu-Chih Chiang, Chih-Feng Huang
  • Patent number: 7560787
    Abstract: In accordance with an embodiment of the invention, a semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. A first silicon region of a first conductivity type extends to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. At least one termination trench is formed in the termination. The termination trench extends into the second silicon region, and is laterally spaced from the first silicon region. An insulating layer lines the sidewalls and bottom of the termination trench. A conductive electrode at least partially fills the termination trench.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: July 14, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 7538407
    Abstract: A semiconductor apparatus (100) comprises a low potential reference circuit region (1) and a high potential reference circuit region (2), and the high potential reference circuit region (2) is surrounded by a high withstand voltage separating region (3). By a trench (4) formed in the outer periphery of the high withstand voltage separating region (3), the low potential reference circuit region (1) and high potential reference circuit region (2) are separated from each other. Further, the trench (4) is filled up with an insulating material, and insulates the low potential reference circuit region (1) and high potential reference circuit region (2). The high withstand voltage separating region (3) is partitioned by the trench (4), high withstand voltage NMOS (5) or high withstand voltage PMOS (6) is provided in the partitioned position.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: May 26, 2009
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masato Taki, Hideki Tojima
  • Patent number: 7511319
    Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET)(100) incorporates a stepped drift region including a shallow trench insulator (STI)(112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: March 31, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ronghua Zhu, Amitava Bose, Vishnu K. Khemka, Todd C. Roggenbauer
  • Publication number: 20090008723
    Abstract: A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A first semiconductor zone of a first conduction type is arranged in the inner region and in the edge region. A second semiconductor zone of a second conduction type is arranged in the inner region and adjacent to the first semiconductor zone. A trench is arranged in the edge region and has first and second sidewalls and a bottom, and extends into the semiconductor body. A doped first sidewall zone of the second conduction type is adjacent to the first sidewall of the trench. A doped second sidewall zone of the second conduction type is adjacent to the second sidewall of the trench. A doped bottom zone of the second conduction type is adjacent to the bottom of the trench. Doping concentrations of the sidewall zones are lower than a doping concentration of the bottom zone.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 8, 2009
    Applicant: Infineon Technologies Austria AG
    Inventor: Gerhard Schmidt
  • Patent number: 7439595
    Abstract: A first SiO2 thin film, a tungsten gate electrode, and a second SiO2 thin film are selectively formed on a first n+-type GaN contact semiconductor layer in that order and in a multilayer film structure having the three layers, a stripe-shaped opening is formed. Via the opening, an undoped GaN channel semiconductor layer and the second n+-type GaN contact semiconductor layer are formed so that both the layers are regrown by, for example, metal organic chemical vapor deposition. A source electrode and a drain electrode are formed so as to contact the corresponding second and first n+-type GaN contact semiconductor layers. The regrown undoped GaN channel semiconductor layer and the regrown second n+-type GaN contact semiconductor layer are horizontally grown portions and hence, the contact area of the electrode can be made larger than the area of the opening.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: October 21, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tetsuzo Ueda
  • Publication number: 20080197442
    Abstract: A semiconductor component comprises a semiconductor body comprising a first component electrode arranged on one of the surfaces of the semiconductor body, a second component electrode arranged on one of the surfaces of the semiconductor body, and a component control electrode arranged on one of the surfaces of the semiconductor body. In this case, active semiconductor element cells are arranged in a first active cell array of the semiconductor body, the semiconductor element cells comprising a first cell electrode, a second cell electrode and a cell control electrode and also a drift path between the cell electrodes. At least the component control electrode is arranged on a partial region of the semiconductor body and a second active cell array is additionally situated in the partial region of the semiconductor body below the component control electrode.
    Type: Application
    Filed: February 18, 2008
    Publication date: August 21, 2008
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Franz Hirler, Olivier Haeberlen, Walter Rieger
  • Patent number: 7391094
    Abstract: A semiconductor structure includes a substrate having a surface and being made of a material that provides atypical surface properties to the surface, a bonding layer on the surface of the substrate, and a further layer molecularly bonded to the bonding layer. A method for fabricating such a semiconductor structure includes providing a substrate having a surface and being made of a material that provides atypical surface properties to the surface, providing a bonding layer on the surface of the substrate, smoothing the bonding layer to provide a surface that is capable of molecular bonding, and molecularly bonding a further layer to the bonding layer to form the structure. The atypical surface properties preferably include at least one of a roughness of more than 0.5 nm rms, or a roughness of at least 0.4 nm rms that is difficult to polish, or a chemical composition that is incompatible with molecular bonding.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: June 24, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Olivier Rayssac, Muriel Martinez, Sephorah Bisson, Lionel Portigliatti
  • Publication number: 20080111207
    Abstract: A high-voltage semiconductor device includes a semiconductor layer having a plurality of pillars of a first conductivity type defined by a plurality of trenches which extend from a top surface of the semiconductor layer toward a bottom surface thereof. A charge compensation layer of a second conductivity type is disposed over at least sidewalls of each trench to a predetermined thickness to form a groove in each trench. A charge compensation plug of the first conductivity type substantially fills each groove.
    Type: Application
    Filed: November 13, 2007
    Publication date: May 15, 2008
    Inventors: Jae-gil Lee, Chang-wook Kim, Ho-cheol Jang, Chong-man Yun
  • Patent number: 7361945
    Abstract: Disclosed herein are a method of manufacturing a semiconductor device, which can prevent a stepped gate from leaning and increase the channel length of the device, thus contributing to an increase in the degree of integration of the device, as well as a semiconductor device manufactured thereby. The method comprises the steps of: forming in a silicon substrate a isolation film defining an active region; selectively etching each of both sides of the active region to form a first recess and a first protrusion surrounded by the first recess and located at the central portion of the active region; selectively etching the bottom of the first recess and either side of the first protrusion to form a second recess and a second central protrusion surrounded by the second recess; and forming a gate on a portion of the active region extending from each of both edges of the second central protrusion to a portion of the second recess of the active region.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: April 22, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyun Jung Kim
  • Patent number: 7348256
    Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: March 25, 2008
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Jr., Volker Dudek, Michael Graf
  • Patent number: 7335944
    Abstract: A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: February 26, 2008
    Assignee: Power Integrations, Inc.
    Inventors: Sujit Banerjee, Donald Ray Disney
  • Patent number: 7304363
    Abstract: A technique of spreading current flowing in a semiconductor device comprising an electrode, a drift region adjacent to the electrode, a junction termination extension implant region in the drift region, and a current spreader adjacent to the junction termination extension implant region and the electrode. The current spreader is adapted to reduce current densities and electrostatic fields (preferably simultaneously) in an area connecting the electrode with the drift region. Moreover, the current spreader is adapted to spread current flowing from the electrode into the drift region. The semiconductor device further comprises an ohmic metal contact connected to the electrode and an implant pocket in the drift region, wherein the implant pocket is adapted for terminating electrostatic field lines in the semiconductor device. Preferably, the current spreader comprises an ohmic metal and the electrode comprises any of an anode and a cathode.
    Type: Grant
    Filed: November 26, 2004
    Date of Patent: December 4, 2007
    Assignee: United States of America as represented by the Secretary of the Army
    Inventor: Pankaj B. Shah
  • Patent number: 7279757
    Abstract: A double-sided extended drain field effect transistor that includes a gate terminal overlying a channel region in a substrate. The substrate includes a drain region of a first carrier type that is laterally separated from the channel region by a first RESURF region of the first carrier type, and a source region of the first carrier type that is laterally separated from the channel region by a second RESURF region of the first carrier type. Regions of the first carrier type may also be disposed laterally adjacent to the source and drain regions on the opposite lateral side as compared to the RESURF regions. This configuration improves the reverse bias breakdown voltage of the transistor.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: October 9, 2007
    Assignee: AMI Semiconductor, Inc.
    Inventors: Greg Scott, J. Marcos Laraia
  • Patent number: 7268339
    Abstract: A method is provided for forming a semiconductor-detection device that provides internal gain. The method includes forming a plurality of bottom trenches in a bottom surface of an n-doped semiconductor wafer; and forming a second plurality of top trenches in a top surface of the semiconductor wafer. The bottom surface and the top surface are opposed surfaces. Each of the bottom trenches is substantially parallel to and substantially juxtaposed to an associated one of the top trenches. The method further includes doping the semiconductor wafer with at least one p-type dopant to form a p-region that defines at least one n-well within the p-region, wherein a p-n junction is formed substantially at an interface of the n-well and the p-region; and removing a portion of the bottom surface to form a remaining-bottom surface, wherein a portion of the n-well forms a portion of the remaining-bottom surface.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: September 11, 2007
    Assignee: Radiation Monitoring Devices, Inc.
    Inventors: Richard Farrell, Kofi Vanderpuye
  • Patent number: 7211861
    Abstract: An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the inside device region and divided in segments by insulated trench-shaped gates to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, an inner region defined in and insulated from the dummy base region, and a connection part to electrically connect the inner region to the emitter electrode.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: May 1, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Teramae, Shigeru Hasegawa, Hideaki Ninomiya, Masahiro Tanaka
  • Patent number: 7180152
    Abstract: A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the arsenic is not intentionally driven. Device junction are then diffused into the epitaxially grown layer.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: February 20, 2007
    Assignee: International Rectifier Corporation
    Inventor: Thomas Herman
  • Patent number: 7170133
    Abstract: A transistor and a method of fabricating the same: The transistor includes an isolation layer disposed in a semiconductor substrate to define an active region. A pair of source/drain regions is disposed in the active region, spaced apart from each other. A channel region is interposed between the pair of the source/drain regions. The active region has a mesa disposed across the channel region. The mesa extends to the source/drain regions. A gate electrode is disposed to cross the active region along the direction across the mesa.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: January 30, 2007
    Assignee: Samsung Electronics Co.
    Inventors: Young-Chul Jang, Won-Seok Cho, Soon-Moon Jung
  • Patent number: 7145214
    Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: December 5, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Patent number: 7141856
    Abstract: Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction will also typically include a horizontal step region at the interface between the upper region and the lower region. Also disclosed are a series of methods of manufacturing semiconductor devices incorporating semiconductor fins having this dual construction and incorporating various combinations of insulating materials such as silicon dioxide and/or silicon nitride for forming shallow trench isolation (STI) structures between adjacent semiconductor fins.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: November 28, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deok Hyung Lee, Byeong Chan Lee, In Soo Jung, Yong Hoon Son, Siyoung Choi, Taek Jung Kim
  • Patent number: 7118942
    Abstract: A method of mass-producing a solid state device comprises providing an atomically smooth, solid state material layer no more than 40 Angstroms thick. This layer is uniformly and defect-freely bonded onto a substrate to provide an acceptable device yield.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: October 10, 2006
    Inventor: Chou H. Li
  • Patent number: 7105927
    Abstract: Disclosed herein is a dummy pattern structure of a semiconductor device. The dummy pattern structure may include daughter dummy patterns respectively formed at places corresponding to vertexes of polygons in regions where metal wirings are not formed in an interlayer insulating film where metal wirings are formed, thus being arranged in the whole region while constituting a polygon shape, and mother dummy patterns respectively formed at places corresponding to the middles of the polygon, which is formed by the daughter dummy patterns. Generation of metal residues in a region where metal wirings are not formed when the metal wirings are formed by means of a damascene process are prevented. Also, a delamination phenomenon that interlayer insulating films are fallen apart can be prevented.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: September 12, 2006
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Se Young Lee
  • Patent number: 7102201
    Abstract: Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least one of the first and second source/drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET's).
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, III