With Physical Configuration Of Semiconductor Surface To Reduce Electric Field (e.g., Reverse Bevels, Double Bevels, Stepped Mesas, Etc.) Patents (Class 257/496)
  • Patent number: 5637908
    Abstract: An increase in breakdown voltage of a semiconductor device upon which a layer of high resistance material, such as SIPOS, has been formed is achieved by controllably modifying the physical composition of the high resistance layer, for example by patterning a plurality of generally wedge-shaped apertures into the layer, so that the electric field in the underlying substrate is made more uniform across the surface of the device. This increase in uniformity in the radial direction effectively spreads out or reduces the field away from its normal peak region near the corner of the drain/substrate PN junction. In most versions of this device, an additional advantage--decreased leakage current--is realized.
    Type: Grant
    Filed: September 28, 1994
    Date of Patent: June 10, 1997
    Assignee: Harris Corporation
    Inventors: Rex E. Lowther, James D. Beason
  • Patent number: 5633521
    Abstract: The present invention provides a MOSFET semiconductor device having a higher breakdown voltage. The MOSFET semiconductor device includes a p-type substrate having an n-type drain region, an n.sup.- -type drain region located adjacent to the n-type drain region, an n.sup.+ -type drain layer located within the n-type drain region and at a surface of the p-type substrate, a p-type top layer located adjacent to the n.sup.- -type drain region and at a surface of the p-type substrate, an n.sup.+ -type source region and a p.sup.+ -type back gate, and a layout pattern constituted of the above mentioned regions and layers includes straight portions and curved portions. The MOSFET semiconductor device is characterized by that the n-type drain region is formed so that the n-type drain region overlaps the p-type top layer in the straight portions of the layout pattern and does not overlap the p-type top layer in the curved portions of the layout pattern.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: May 27, 1997
    Assignee: NEC Corporation
    Inventor: Yukimasa Koishikawa
  • Patent number: 5614753
    Abstract: A semiconductor device is produced through electrolytic etching process. The device comprises a P-type silicon substrate. An N-type epitaxial layer is formed on the silicon substrate. P-type regions are defined in the N-type epitaxial layer. N-type regions are defined in some of the P-type regions. A first wiring layer connects to predetermined ones of the P-type regions. A second wiring layer connects to predetermined ones of the N-type regions. The semiconductor device has a given part which has such a possibility that a predetermined magnitude of leakage current flows therethrough between the first and second wiring layers when subjected to the electrolytic etching process. The semiconductor device further has a circuit which is electrically connected to one of the first and second wiring layers. The circuit is capable of removing the possibility of the leakage current flow through the given part when opened.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: March 25, 1997
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Susumu Uchikoshi, Shigeyuki Kiyota, Yasukazu Iwasaki, Takatoshi Noguchi, Makoto Uchiyama
  • Patent number: 5532899
    Abstract: A voltage protection arrangement (10) comprises a semiconductor substrate (12) having at least two electrical conductors (16,18,20) adjacent an edge of the substrate. An aperture (22) extends from the edge towards a point between the two electrical conductors. The aperture (22) reduces conductance between the two electrical conductors (16,18) in a region adjacent the edge of the substrate (12), such that if an excess voltage occurs between the two conductors (16,18), a reduced current flows in the region.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: July 2, 1996
    Assignee: Motorola, Inc.
    Inventor: Jean-Claude Tarbouriech
  • Patent number: 5506421
    Abstract: The power metal oxide semiconductor field effect transistor (MOSFET) has a drain region, a channel region, and a source region formed of silicon carbide. The drain region has a substrate of silicon carbide of a first conductivity type and a drain-drift region of silicon carbide adjacent the substrate having the same conductivity type. The channel region is adjacent the drain-drift region and has the opposite conductivity type from the drain-drift region. The source region is adjacent the channel region and has the same conductivity type as the drain-drift region. The MOSFET also has a gate region having a gate electrode formed on a first portion of the source region, a first portion of the channel region, and a first portion of the drain region. A source electrode is formed on a second portion of the source region and a second portion of the channel region. Also, a drain electrode is formed on a second portion of the drain region.
    Type: Grant
    Filed: November 24, 1992
    Date of Patent: April 9, 1996
    Assignee: Cree Research, Inc.
    Inventor: John W. Palmour
  • Patent number: 5449932
    Abstract: A field effect transistor having a gate electrode in a recess includes a gate electrode and a source electrode in the same recess and a drain electrode outside the recess. Therefore, the gate-to-drain breakdown voltage is increased without increasing the source resistance.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: September 12, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takayuki Fujii
  • Patent number: 5446301
    Abstract: A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.
    Type: Grant
    Filed: July 13, 1994
    Date of Patent: August 29, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koji Eguchi, Natsuo Ajika, Kazuyuki Sugahara
  • Patent number: 5399899
    Abstract: A semiconductor device with a semiconductor body (1) is provided with a first and a second bipolar transistor (T1, T2, respectively) in a cascode configuration, in which the semiconductor body (1) comprises, in that order, a collector region (10) and a base region (11) of the first transistor (T1), a region (12) which forms both an emitter region of the first transistor (T1) and a collector region of the second transistor (T2), a space charge region (13), and a base region (14) and emitter region (15) of the second transistor (T2), while the regions form pn junctions with one another which extend parallel to a main surface (2) of the semiconductor body (1). The base region (14) and the emitter region (15) of the second transistor (T2) adjoin a main surface (3) of the semiconductor body (1).
    Type: Grant
    Filed: December 27, 1993
    Date of Patent: March 21, 1995
    Assignee: U.S. Philips Corporation
    Inventors: Ronald Dekker, Henricus G. R. Maas, Dirk J. Gravesteijn, Martinus P. J. G. Versleijen
  • Patent number: 5389815
    Abstract: A high speed soft recovery diode having a large breakdown voltage is disclosed. Anode P layers (3) are selectively formed in a top portion of an N.sup.- body (2). A P.sup.- layer (4a) is disposed in the top portion of the N.sup.- body (2) so as to be spacewise complementary to the anode P layers (3). In the N.sup.- body (2), P regions (5) are selectively formed below the P.sup.- layer (4a). On the N.sup.- body (2), an anode electrode (6) is disposed in contact with both the P.sup.- layer (4a) and the anode P layers (3). A cathode electrode (7) is disposed under the N.sup.- body (2) through a cathode layer (1). When the diode is reverse-biased, a depletion layer does not have a sharply curved configuration due to the P regions (5). Hence, concentration of electric field is avoided and a breakdown voltage would not deteriorate. During forward-bias state of the diode, injection of excessive holes from the anode P layers (3) into the N.sup.- body (2) is prevented, thereby reducing a recovery current.
    Type: Grant
    Filed: April 20, 1993
    Date of Patent: February 14, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideki Takahashi
  • Patent number: 5381029
    Abstract: A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: January 10, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koji Eguchi, Natsuo Ajika, Kazuyuki Sugahara
  • Patent number: 5343069
    Abstract: An electronic switch, in particularly a transistor, has at least one barrier layer extending between regions of different doping concentrations within a semiconductor and is characterized in that the barrier layer has at least one voltage limiting zone (Z) having a radius of curvature (R) less than or at most equal to the diffusion depth (x.sub.JB) of the diffused junction.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: August 30, 1994
    Assignee: Robert Bosch GmbH
    Inventors: Christian Pluntke, Alfred Goerlach
  • Patent number: 5313092
    Abstract: A semiconductor device of vertical arrangement includes an anode region formed of a first semiconductor substrate and a second semiconductor substrate joined with the first semiconductor substrate. The first semiconductor substrate forms a high-resistance layer with a predetermined impurity density, and the second semiconductor substrate forms a low-resistance layer whose impurity density is higher than that of the high-resistance layer. A PN junction is formed inside the first semiconductor substrate. The periphery of the first semiconductor substrate including the PN junction is configured in an inverted mesa structure and coated with an insulation material. With this arrangement, the semiconductor device has a high withstand voltage and enables an employment of a large diameter wafer.
    Type: Grant
    Filed: March 3, 1992
    Date of Patent: May 17, 1994
    Assignee: Nippon Soken, Inc.
    Inventors: Kazuhiro Tsuruta, Mitutaka Katada, Seiji Fujino, Masami Yamaoka
  • Patent number: 5281839
    Abstract: A semiconductor device having a channel region having a first and a second portion. The first and second portions of the channel region are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.
    Type: Grant
    Filed: April 23, 1993
    Date of Patent: January 25, 1994
    Assignee: Motorola, Inc.
    Inventors: Bertrand F. Cambou, Robert B. Davies
  • Patent number: 5243197
    Abstract: The efficiency of semiconductor cathodes based on avalanche breakdown is enhanced by using ".delta.-doping" structures. The quantization effects introduced thereby decrease the effective work function. A typical cathode structure has an n-type semiconductor region and a first p-type semiconductor region, with the n-type region having a thickness of at most 4 nanometers.
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: September 7, 1993
    Assignee: U.S. Philips Corp.
    Inventors: Gerardus G. P. Van Gorkom, Aart A. Van Gorkum, Gerjan F. A. Van De Walle, Petrus A. M. Van Der Heide, Arthur M. E. Hoeberechts
  • Patent number: 5233215
    Abstract: A silicon carbide power MOSFET device includes a first silicon carbide layer, epitaxially formed on the silicon carbide substrate of opposite conductivity type. A second silicon carbide layer of the same conductivity type as the substrate is formed on the first silicon carbide layer. A power field effect transistor is formed in the device region of the substrate and in the first and second silicon carbide layers thereover. At least one termination trench is formed in the termination region of the silicon carbide substrate, extending through the first and second silicon carbide layers thereover. The termination trench defines one or more isolated mesas in the termination region which act as floating field rings. The termination trenches are preferably insulator lined and filled with conductive material to form floating field plates. The outermost trench may be a deep trench which extends through the first and second silicon carbide layers and through the drift region of the silicon carbide substrate.
    Type: Grant
    Filed: June 8, 1992
    Date of Patent: August 3, 1993
    Assignee: North Carolina State University at Raleigh
    Inventor: Bantval J. Baliga
  • Patent number: 5166769
    Abstract: A process for forming a semiconductor device begins by diffusing an N layer having a relatively high concentration into a P wafer having a relatively low concentration. Next, the wafer is etched to yield a plurality of mesa semiconductor structures, each having a P-N junction intersecting a sidewall of the mesa structure. Then, a layer of oxide is grown on the sidewalls of the mesas, which oxide layer passivates the device. The oxidizing step curves the P-N junction toward the P layer in the vicinity of the oxide layer. Then, the P-N junction is diffused deeper into the P layer with a diffusion front which tends to curve the P-N junction back toward the N layer in the vicinity of the oxide layer. This diffusion is carried out to such an extent as to compensate for the curvature caused by the oxidizing step and thereby substantially flatten the P-N junction. A plurality of successive oxidation/diffusion steps can be undertaken to further flatten the junction adjacent the mesa sidewall.
    Type: Grant
    Filed: May 11, 1992
    Date of Patent: November 24, 1992
    Assignee: General Instrument Corporation
    Inventors: Willem G. Einthoven, Linda J. Down