High Power Or High Voltage Device Extends Completely Through Semiconductor Substrate (e.g., Backside Collector Contact) Patents (Class 257/502)
  • Patent number: 10720368
    Abstract: A semiconductor device includes: an insulating substrate having an upper surface on which a semiconductor element is mounted; a base plate joined to a lower surface of the insulating substrate; a case member that surrounds the insulating substrate and that is in contact with a surface of the base plate to which the insulating substrate is joined; a sealing resin provided in a region surrounded by the base plate and the case member; a cover member facing a surface of the sealing resin and fixed to the case member; and a holding plate, a lower surface of the holding plate and a portion of a side surface of the holding plate being in close contact with the surface of the sealing resin, an upper surface of the holding plate being fixed to and protruding from a surface of the cover member facing the surface of the sealing resin.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: July 21, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Harada, Kozo Harada, Yasumichi Hatanaka, Takashi Nishimura, Masaki Taya
  • Patent number: 10658502
    Abstract: III-N transistor including a vertically-oriented lightly-doped III-N drift region between an overlying III-N 2DEG channel and an underlying heavily-doped III-N drain. In some embodiments, the III-N transistors are disposed over a silicon substrate. In some embodiments, lateral epitaxial overgrowth is employed to form III-N islands self-aligned with the vertically-oriented drift region. A gate electrode disposed over a portion of a III-N island may modulate a 2DEG within a channel region of the III-N island disposed above the III-N drift region. Charge carriers in the 2DEG channel may be swept into the drift region toward the drain. Topside contacts to each of the gate, source, and drain may be pitch scaled independently of a length of the drift region.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic
  • Patent number: 10431558
    Abstract: An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include a back-bias metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the back-bias metallization. The integrated RF circuit structure may further include a handle substrate on a front-side dielectric layer on the active device.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Sinan Goktepeli
  • Patent number: 10374129
    Abstract: An improved high temperature resistant backside metallization for compound semiconductors comprises a front-side metal layer formed on a compound semiconductor substrate; at least one via hole penetrating the compound semiconductor substrate, a top of an inner surface of the via hole is defined by the front-side metal layer; at least one seed metal layer, at least one backside metal layer and at least one diffusion barrier layer sequentially formed on a bottom surface of the compound semiconductor substrate and the inner surface of the via hole, the seed metal layer and the front-side metal layer are electrically connected through the via hole; a die attachment metal layer formed on a bottom surface of the diffusion barrier layer other than the via hole and an adjacent area near the via hole. The diffusion barrier layer prevents the backside metal layer from diffusing into the die attachment metal layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 6, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Shu Chen Chen, Huang-Wen Wang, Walter Tony Wohlmuth
  • Patent number: 10297530
    Abstract: A press member which has a given length for pressing a semiconductor stack unit. The press member includes supported portions with which supporting members are placed in contact and which are arranged in a lengthwise direction of the press member, a spring which is curved in a convex shape and bulges away from contacts of the supporting members with the supported portions, and load-exerted portions which are arranged outside the supported portions in the lengthwise direction of the press member and capable of being subjected to mechanical load to elastically deform the spring, thereby shifting the supported portions. At least one of the load-exerted portions has a cut-out formed by cutting away a portion of the plate, thereby avoiding a physical interference of the press member with peripheral members and ensuring a desired degree of stroke and durability of the press member.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: May 21, 2019
    Assignee: DENSO CORPORATION
    Inventor: Keisuke Mizushiri
  • Patent number: 9892998
    Abstract: The present disclosure discloses a package module of a power conversion circuit and a manufacturing method thereof. The package module of the power conversion circuit is surface-mountable on a system board. The package module of the power conversion circuit includes: a substrate, a power device die, a molding layer and a plurality of pins. The substrate has a metal layer, an insulating substrate layer and a thermal conductive layer. The insulating substrate layer is disposed between the metal layer and the thermal conductive layer. The power device die is coupled to the metal layer. Devices on the metal layer of the substrate are embedded in the molding layer. The plurality of pins is electrically coupled to the metal layer and embedded in the molding layer, at least a contact surface of each of the pins which is electrically coupled to the system board is exposed, and the contact surface is parallel and/or perpendicular to the thermal conductive layer.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: February 13, 2018
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Kai Lu, Zhenqing Zhao, Shouyu Hong, Tao Wang, Le Liang
  • Patent number: 9685504
    Abstract: A semiconductor device includes a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing lifetime and/or mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: June 20, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Haertl, Frank Hille, Francisco Javier Santos Rodriguez, Daniel Schloegl, Andre Rainer Stegner, Christoph Weiss
  • Patent number: 9583588
    Abstract: A method includes epitaxially growing a gallium nitride (GaN) layer over a silicon substrate. The method further includes epitaxially growing a donor-supply layer over the GaN layer. The method further includes forming a source and a drain on the donor-supply layer. The method further includes forming a gate structure between the source and the drain on the donor-supply layer. The method further includes plasma etching a portion of a drift region of the donor-supply layer to a depth of less than 60% of a donor-supply layer thickness. The method further includes depositing a dielectric layer over the donor-supply layer.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ju Yu, Chih-Wen Hsiung, Fu-Wei Yao, Chun-Wei Hsu, King-Yuen Wong, Jiun-Lei Jerry Yu, Fu-Chih Yang
  • Patent number: 9466719
    Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: October 11, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Paul A. Nygaard, Stuart B. Molin, Michael A. Stuber, Max Aubain
  • Patent number: 9443971
    Abstract: A semiconductor device includes a diffusion barrier layer, a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region in contact with the diffusion barrier layer, the contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing the lifetime and/or the mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: September 13, 2016
    Assignee: Infineon Technologies AG
    Inventors: Andreas Haertl, Frank Hille, Francisco Javier Santos Rodriguez, Daniel Schloegl, Andre Rainer Stegner, Christoph Weiss
  • Patent number: 9236380
    Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: January 12, 2016
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Pierre Morin, Qing Liu, Nicolas Loubet
  • Patent number: 9018769
    Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: April 28, 2015
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 9006809
    Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Fei Xie, Wen Cheng Tien, Ya Ping Chen, Li Bin Man, Kuo Jung Chen, Yu Liu, Tian Yi Zhang, Sisi Xie
  • Patent number: 9000495
    Abstract: According to one embodiment, in a semiconductor apparatus, a semiconductor substrate has a first surface and a second surface opposite to the first surface. A semiconductor device is formed in a rectangular region enclosed by a plurality of dicing lines of the semiconductor substrate. The semiconductor device includes a first electrode provided on the first surface and a second electrode provided on the second surface so as to pass a current between the first electrode and the second electrode. A penetration electrode is formed in a region not enclosed by the dicing lines of the semiconductor substrate. One end of the penetration electrode extends on the first surface. The other end of the penetration electrode is electrically connected to the second electrode.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Daisuke Yamashita
  • Patent number: 8987880
    Abstract: In various embodiments, a chip module may include a first chip; and a leadframe with a first leadframe area and a second leadframe area, wherein the first leadframe area is electrically insulated from the second leadframe area; wherein the first chip is arranged at least partially on the first leadframe area and at least partially on the second leadframe area.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Josef Hoeglauer, Ralf Otremba, Xaver Schloegel
  • Patent number: 8928145
    Abstract: A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Cyril Cabral, Jr., Kenneth P. Rodbell, Robert L. Wisnieff
  • Patent number: 8921945
    Abstract: The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 ?m. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: December 30, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Ralf Lerner
  • Patent number: 8900895
    Abstract: A method of manufacturing an LED package including steps: providing an electrode, the electrode including a first electrode, a second electrode, a channel defined between the first electrode and the second electrode, the first electrode and the second electrode arranged with intervals mutually, a cavity arranged on the first electrode, and the cavity communicating with the channel; arranging an LED chip electrically connecting with the first electrode and the second electrode and arranged inside the cavity; providing a shield covering the first electrode and the second electrode; injecting a transparent insulating material to the cavity via the channel, and the first electrode, the second electrode, and the shield being interconnected by the transparent insulating material; solidifying the transparent insulating material to obtain the LED package.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Hou-Te Lin, Ming-Ta Tsai
  • Patent number: 8876312
    Abstract: In one embodiment, a light-emitting device having a substrate, a casing, a plurality of light source dies, a plurality of spectral converters and a plurality of optical structures is disclosed. The spectral converters may be configured to spectrally adjust a portion of the light output of the light source die into a first and second converted spectral output that is substantially different from one another. In another embodiment, a system for illumination having a plurality of lighting assemblies has been disclosed. Each of the lighting assemblies comprises a light source die and a spectral converter. The spectral converter is configured to spectrally adjust the light output of the light source die so that the plurality of lighting assemblies are configured to emit substantially different spectral output. In yet another embodiment, a lighting apparatus having a primary spectral converter and a secondary spectral converter is disclosed.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: November 4, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Kheng Leng Tan, Ju Chin Poh, Keat Chuan Ng, Chuan Hoe Chan, Kwok Yuen Ng, Kum Soon Wong
  • Patent number: 8872276
    Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Gordon M. Grivna
  • Patent number: 8860172
    Abstract: An n well region and an n?region surrounding the n well region are provided in the surface layer of a p?silicon substrate. The n?region includes breakdown voltage regions in which high voltage MOSFETs are disposed. The n well region includes a logic circuit region in which a logic circuit is disposed. A p? opening portion is provided between a drain region of each high voltage MOSFET and the logic circuit region. An n buffer region used as load resistances is provided between a second pick-up region and the drain region. The p?opening portion is provided between the n buffer region and logic circuit region. By so doing, it is possible to realize a reduction in the area of chips, and provide a high voltage semiconductor device having a level shift circuit with a high switching response speed.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: October 14, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Masaharu Yamaji
  • Patent number: 8846526
    Abstract: A substrate (3) in which a through-hole (2) is filled with a filler (4) is prepared, and a structure (6), at least a part of the surface of which has an insulating property, is formed on the surface of the substrate (3). A plated layer (7) is formed on the substrate (3) having the structure (6) formed thereon, and the filler (4) and the structure (6) are removed. Thus, a through-hole substrate (8) is formed, in which the plated layer (7) having an opening (9) communicating with the through-hole (2) is provided on at least one surface of a substrate (1).
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: September 30, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takayuki Teshima
  • Patent number: 8796816
    Abstract: A semiconductor module is provided which is capable of lowering surges caused when switching elements are switched on and off. The module has a plurality of lead frames, switching elements, electronic components, and a sealing member. The switching elements are electrically connected to the lead frames respectively. Part of the lead frames, the switching elements, and the electronic components are sealed by the sealing member. The electronic components are mounted on primary surfaces of the lead frames respectively.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: August 5, 2014
    Assignee: Denso Corporation
    Inventors: Yuji Hayashi, Yuuichi Handa
  • Patent number: 8748949
    Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: June 10, 2014
    Inventors: Chien-Hung Liu, Cheng-Te Chou
  • Patent number: 8749019
    Abstract: A region-divided substrate includes: a substrate having a first surface and a second surface opposite to the first surface and having a plurality of partial regions, which are divided by a plurality of trenches, wherein each trench penetrates the substrate from the first surface to the second surface; a conductive layer having an electrical conductivity higher than the substrate and disposed on a sidewall of one of the plurality of partial regions from the first surface to the second surface; and an insulator embedded in each trench.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: June 10, 2014
    Assignee: DENSO CORPORATION
    Inventors: Tetsuo Fujii, Keisuke Gotoh, Masaya Tanaka
  • Patent number: 8742477
    Abstract: An integrated circuit structure can include a silicon interposer. The silicon interposer can include a first elliptical TSV and a keep out zone (KOZ) for stress effects upon active devices surrounding the first elliptical TSV. A size of the KOZ can be determined by a transverse diameter and a conjugate diameter of the first elliptical TSV.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: June 3, 2014
    Assignee: Xilinx, Inc.
    Inventor: Bahareh Banijamali
  • Patent number: 8741707
    Abstract: A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: June 3, 2014
    Assignee: Avogy, Inc.
    Inventors: Donald R. Disney, Isik C. Kizilyalli, Linda Romano, Andrew Edwards, Hui Nie
  • Patent number: 8742563
    Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: June 3, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Thorsten Meyer, Harry Hedler, Markus Brunnbauer
  • Patent number: 8722528
    Abstract: Standoff structures that can be used on the die backside of semiconductor devices and methods for making the same are described. The devices contain a silicon substrate with an integrated circuit on the front side of the substrate and a backmetal layer on the backside of the substrate. Standoff structures made of Cu of Ni are formed on the backmetal layer and are embedded in a Sn-containing layer that covers the backmetal layer and the standoff structures. The standoff structures can be isolated from each other so that they are not connected and can also be configured to substantially mirror indentations in the leadframe that is attached to the Sn-containing layer. Other embodiments are described.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 13, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Michael Gruenhagen, Thomas P. Welch, Eric J. Woolsey
  • Patent number: 8704329
    Abstract: SOI devices for plasma display panel driver chip, include a substrate, a buried oxide layer and an n-type SOI layer in a bottom-up order, where the SOI layer is integrated with an HV-NMOS device, an HV-PMOS device, a Field-PMOS device, an LIGBT device, a CMOS device, an NPN device, a PNP device and an HV-PNP device; the SOI layer includes an n+ doped region within the SOI layer at an interface between the n-type SOI layer and the buried oxide layer; and the n+ doped region has a higher doping concentration than the n-type SOI layer.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: April 22, 2014
    Assignee: University of Electronic Science and Technology of China
    Inventors: Ming Qiao, Bo Luo, Xi Hu, Jun Ye, Bo Zhang, Zhaoji Li
  • Patent number: 8697569
    Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: April 15, 2014
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 8692266
    Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: April 8, 2014
    Assignee: Optromax Electronics Co., Ltd
    Inventor: Kuo-Tso Chen
  • Patent number: 8686533
    Abstract: Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Chun Wang, Tzu-Hsuan Hsu
  • Patent number: 8686469
    Abstract: A semiconductor device includes a semiconductor substrate having a diode active region and an edge termination region adjacent to each other, a first region of a first conductivity type in the diode active region, a second region of a second conductivity type, a third region of the first conductivity type in the edge termination region, and a fourth region of the second conductivity type. The first region and the third region share a drift region of the first conductivity type. The first region and the third region share a fifth region of the first conductivity type. The drift region in the third region is greater in number of crystal defects per unit volume than the drift region in the first region in order that the drift region in the third region is shorter in carrier lifetime than the drift region in the first region.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: April 1, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 8674729
    Abstract: A high voltage semiconductor device is provided and includes an n?-type region encompassed by a p? well region and is provided on a p?-type silicon substrate. A drain n+-region is connected to a drain electrode. A p base region is formed so as to be separate from and encompass the drain n+-region. A source n+-region is formed in the p base region. Further, a p?-region is provided that passes through the n?-type region to the silicon substrate. The n?-type region is divided, by the p?-region, into a drift n?-type region having the drain n+-region and a floating n?-type region having a floating electric potential.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: March 18, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Masaharu Yamaji
  • Patent number: 8618557
    Abstract: A wide-band-gap reverse-blocking MOS-type semiconductor device includes a SiC n?-type drift layer; a p+-type substrate on the first major surface side of the drift layer; a trench extending through a p+-type substrate into the drift layer; a titanium electrode in the trench bottom that forms a Schottky junction with the SiC n?-type drift layer; an active section including a MOS-gate structure on the second major surface side of the drift layer facing to the area, in which the Schottky junctions are formed; a breakdown withstanding section surrounding the active section; and a trench isolation layer surrounding the breakdown withstanding section, the trench isolation layer extending from the second major surface of the drift layer into p+-type substrate and including insulator film buried therein. The device facilitates making a high current flow with a low ON-voltage and exhibits a very reliable reverse blocking capability.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: December 31, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Koh Yoshikawa
  • Patent number: 8614480
    Abstract: A power MOSFET is formed in a semiconductor device with a parallel combination of a shunt resistor and a diode-connected MOSFET between a gate input node of the semiconductor device and a gate of the power MOSFET. A gate of the diode-connected MOSFET is connected to the gate of the power MOSFET. Source and drain nodes of the diode-connected MOSFET are connected to a source node of the power MOSFET through diodes. The drain node of the diode-connected MOSFET is connected to the gate input node of the semiconductor device. The source node of the diode-connected MOSFET is connected to the gate of the power MOSFET. The power MOSFET and the diode-connected MOSFET are integrated into the substrate of the semiconductor device so that the diode-connected MOSFET source and drain nodes are electrically isolated from the power MOSFET source node through a pn junction.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: December 24, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Jun Wang, Shuming Xu, Jacek Korec
  • Patent number: 8610237
    Abstract: A semiconductor apparatus includes a semiconductor chip, a lead frame that has a first surface having the semiconductor chip mounted thereover and a second surface opposite to the first surface, a bonding wire that couples the semiconductor chip and the lead frame, and a high dielectric constant layer that is disposed over a surface of the lead frame opposite to a surface having the semiconductor chip mounted thereover and that has a relative permittivity of 5 or more. The lead frame includes a source electrode lead coupled to the source of a semiconductor device formed over the semiconductor chip and a source-wire junction at which the source electrode lead and the bonding wire are coupled together. The high dielectric layer is disposed in a region including at least a position corresponding to the source-wire junction over the second surface of the lead frame.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Naoki Sakura
  • Patent number: 8564101
    Abstract: A semiconductor apparatus having a through-hole interconnection in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. A via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has another insulating layer formed in the via hole and a conductive layer formed thereon. The insulating layer formed in the via hole is formed such as to substantially planarize an inner surface of the via hole.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: October 22, 2013
    Assignees: Sony Corporation, Fujikura Ltd.
    Inventors: Yoshimichi Harada, Masami Suzuki, Yoshihiro Nabe, Yuji Takaoka, Tatsuo Suemasu, Hideyuki Wada, Masanobu Saruta
  • Patent number: 8546874
    Abstract: A semiconductor device includes a drift layer and a body region that forms a p-n junction with the drift layer. A contactor region is in the body region, and a shunt channel region extends through the body region from the contactor region to the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse bias the p-n junction between the drift region and the body region.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: October 1, 2013
    Assignee: Cree, Inc.
    Inventors: Allen Hefner, Sei-Hyung Ryu, Anant Agarwal
  • Patent number: 8530299
    Abstract: An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Gordon M. Grivna
  • Patent number: 8497206
    Abstract: A method of processing copper backside metal layer for semiconductor chips is disclosed. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by either electroless plating or sputtering. Then, the copper backside metal layer is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the copper backside metal layer through backside via holes, but also prevents metal peeling from semiconductor's substrate after subsequent fabrication processes, which is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes. The use of Pd as seed layer is particularly useful for the copper backside metal layer, because the Pd layer also acts as a diffusion barrier to prevent Cu atoms entering the semiconductor wafer.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: July 30, 2013
    Assignee: WIN Semiconductor Corp.
    Inventors: Chang-Hwang Hua, Wen Chu
  • Patent number: 8455973
    Abstract: A region divided substrate includes a substrate, a plurality of trenches, a conductive layer, and an insulating member. The substrate has a first surface and a second surface opposed to each other. The trenches penetrate the substrate from the first surface to the second surface and divide the substrate into a plurality of partial regions. The conductive layer is disposed on a sidewall of each of the trenches from a portion adjacent to the first surface to a portion adjacent to the second surface. The conductive layer has an electric conductivity higher than an electric conductivity of the substrate. The insulating member fills each of the trenches through the conductive layer.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: June 4, 2013
    Assignee: DENSO CORPORATION
    Inventors: Tetsuo Fujii, Masaya Tanaka, Keisuke Gotoh
  • Patent number: 8400778
    Abstract: A multi-phase voltage regulator is disclosed where each phase is comprised of an array of high and low side transistors that are integrated onto a single substrate. Further, a system of mounting the voltage regulator onto a flip chip and lead frame is disclosed wherein the source and drain lines form an interdigital pattern.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: March 19, 2013
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Michael R. Hsing, Anthonius Bakker
  • Patent number: 8314473
    Abstract: Standoff structures that can be used on the die backside of semiconductor devices and methods for making the same are described. The devices contain a silicon substrate with an integrated circuit on the front side of the substrate and a backmetal layer on the backside of the substrate. Standoff structures made of Cu of Ni are formed on the backmetal layer and are embedded in a Sn-containing layer that covers the backmetal layer and the standoff structures. The standoff structures can be isolated from each other so that they are not connected and can also be configured to substantially mirror indentations in the leadframe that is attached to the Sn-containing layer. Other embodiments are described.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: November 20, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Michael Gruenhagen, Thomas P. Welch, Eric J. Woolsey
  • Patent number: 8309993
    Abstract: A pixel of an image sensor includes a polysilicon layer, and an active region which needs to be electrically coupled with the polysilicon layer, wherein the polysilicon layer extends over a portion of the active region, such that the polysilicon layer and the active region are partially overlapped, and the polysilicon layer and the active region are coupled through a buried contact structure.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: November 13, 2012
    Assignee: Intellectual Ventures II LLC
    Inventors: Woon-Il Choi, Hyung-Sik Kim, Ui-Sik Kim
  • Patent number: 8298906
    Abstract: A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to RIE lag.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Francis Roger White
  • Patent number: 8269304
    Abstract: A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 18, 2012
    Assignee: Trinno Technology Co., Ltd.
    Inventors: Kwang-Hoon Oh, Byoung-Ho Choo, Soo-Seong Kim, Chong-Man Yun
  • Patent number: 8227888
    Abstract: A semiconductor component including a first integrated circuit in a substrate which is adapted to produce electrical signals with a high-frequency signal component, wherein the substrate is such that the high-frequency signal component can propagate on a substrate surface and/or in the substrate interior, a second integrated circuit in the same substrate which is such that its function can be compromised by high-frequency signals, and a countersignal circuit in the same substrate which is adapted to deliver an electrical countersignal which at least at a selected location of the substrate surface and/or the substrate interior attenuates or eliminates the high-frequency electrical signal component emanating from the first integrated circuit, wherein the countersignal circuit includes a receiver which is adapted to produce an electrical signal dependent on the instantaneous field strength of the high-frequency signal component, and a shielding transistor provided in the substrate and having a control electrode
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: July 24, 2012
    Assignee: IHP GmbH—Innovations for High Performance Microelectronics
    Inventors: Gunther Lippert, Gerald Lippert
  • Patent number: RE45449
    Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Armin Willmeroth