Abstract: Isolation regions for a semiconductor layer of a semiconductor-on-insulator substrate are fabricated by forming a patterned implantation mask on the semiconductor layer. The patterned implantation mask includes mask sidewalls. An implantation masking film is formed on the sidewalls of the patterned implantation mask. Ions are implanted into the semiconductor layer, using the patterned implantation layer and the implantation masking film as a mask, to thereby form a doped region in the semiconductor layer. Sidewall spacers are formed on the implantation masking film, opposite the patterned implantation mask. The doped region between the sidewall spacers is etched to thereby define a trench in the semiconductor layer between the sidewall spacers and a doped edge layer in the semiconductor layer which extends from the trench to the implantation masking film. Insulating material is then formed in the trench.

Abstract: A semiconductor device of SOI structure exhibits a excellent heat-radiating characteristic while assuring breakdown-voltage and element-isolating performance. A buried silicon oxide film having a thickness required by the breakdown-voltage of a semiconductor element is buried between a SOI layer and a silicon substrate. A SOI layer is divided into island silicon regions by a groove for electrical-isolation use, and the groove is filled with dielectric such as an oxide film and polycrystalline silicon. In an island silicon region, a LDMOS transistor having high breakdown voltage may be formed as the semiconductor element, and potential distribution is created in accordance with a voltage application to the semiconductor element. The buried silicon oxide film at a region where low electric potential is distributed, for example a region below a grounded well region of the LDMOS transistor, is made thin.

Abstract: Insulating trenches (2) in the silicon layer of an SOI substrate that extend onto the insulating layer of the SOI substrate define silicon islands (3). At least one of the silicon islands (3) is an interconnect segment (3a) by a diffusion zone that is arranged at the walls of the surrounding trench (2) and that is formed by drive-out from an occupation layer introduced into the trench. The interconnect segment (3a) is suitable as an underpass for crossing interconnects (6a,6b) or as an additional metallization level.

Abstract: A method is described for fabricating a complementary, vertical bipolar sconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ silicon island by epitaxially growing an N-type silicon layer on the N+ silicon island. Then, a P region is created in the N-type silicon layer. An N+ region created in the P region completes the NPN junction device. Similarly, a PNP junction device is formed by epitaxially growing a P-type silicon layer on the P+ silicon island. Then, an N region is created in the P-type silicon layer. A P+ region created in the N region completes the PNP junction device.

Abstract: A semiconductor-on-insulator structure includes a single crystal semiconductor substrate, an insulating layer on the single crystal semiconductor substrate, a recrystallized single crystal semiconductor layer on the insulating layer and having a subgrain, i.e., quasi grain boundary and a highly doped region including the quasi grain boundary and having a higher dopant impurity concentration than other parts of the single crystal semiconductor layer. Thus, a non-uniformity in the resistance is suppressed without reducing the piezoresistance effect of the structure.

Abstract: A semiconductor device comprising at least two thin film transistors on a substrate having an insulating surface thereon, provided that the thin film transistors are isolated by oxidizing the outer periphery of the active layer of each of the thin film transistors to the bottom to provide an oxide insulating film.

Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

Abstract: Pin-holes or thin sections in the implanted dielectric layer of a SIMOX device are patched by forming a reverse biasable PN junction within the depth range of or proximate to the dielectric layer. A charge depletion zone forms about the PN junction when the Latter is reverse-biased and reinforces or patches weak spots in the implanted dielectric layer such as pin-holes and thin-sections.

Abstract: A semiconductor device comprising at least two thin film transistors on a substrate having an insulating surface thereon, provided that the thin film transistors are isolated by oxidizing the outer periphery of the active layer of each of the thin film transistors to the bottom to provide an oxide insulating film.

Abstract: A method for forming a semiconductor structure having a layer of low minority carrier lifetime and a layer of high minority carrier lifetime comprises the steps of forming a silicon dioxide layer on a layer of low minority carrier lifetime silicon of a silicon-on-sapphire handle wafer and another layer of silicon dioxide on a layer of high minority carrier lifetime silicon of a bulk silicon device wafer. The silicon dioxide layers are placed in contact and annealed to form a bonded structure having an annealed layer of silicon dioxide. The layer of bulk silicon is then thinned. The thinned layer of bulk silicon and the annealed silicon dioxide layer are patterned by photolithography to form mesas of high minority carrier lifetime silicon and to expose regions of low minority carrier lifetime silicon on the bonded structure.

Abstract: A semiconductor device comprises a semiconductor layer including a source region, a drain region and a channel region provided on an insulating film. A gate insulating film separates the semiconductor layer from a gate electrode. A thickness of the channel region is smaller than a thickness of the source or drain region, and a level of an interface between the channel region and the insulating film is different from a level of an interface of the source or drain region and the insulating film. All the surfaces of the channel region, source region and drain region which face the gate electrode are on the same level.

Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.

Abstract: A semiconductor device comprises a complementary MOS transistor integrated circuit formed in a semiconductor single crystal silicon disposed on an electrically insulating layer. A thickness of the single crystal silicon in a region in which an N-type MOS transistor is formed is made thicker than the thickness in a region in which a P-type MOS transistor is formed. By this structure, the bottoms of the source region and the drain region of the N-type transistor are separated from the electrically insulating layer by a predetermined distance. The separation of the source region and the drain region from the electrically insulating layer is effective to prevent a parasitic channel from forming, thereby reducing leakage current and making the semiconductor device more efficient.

Abstract: A dielectric isolated high voltage semiconductor device having an arrangement for extending a depletion layer of a main junction beyond an insulating layer containing an island to a semiconductor supporter by applying the same reverse biasing voltage to the supporter and the islands. That is, in the structure, an electrode is provided at the back surface of the supporter and connected to a main electrode of the selected island. The above-mentioned main junction is the pn junction to which the reverse biasing voltage for securing the withstand voltage of the semiconductor device is applied.

Abstract: A device isolation area structure in a semiconductor device is composed of two layers of a first device isolation film formed by selectively oxidizing a surface of a silicon substrate, and a second device isolation region formed in a single crystal silicon film covering the first device isolation film. A guard band region may be formed within the semiconductor substrate and immediately below the first device isolation film so as to be in contact with the first device isolation film. The device isolation area structure is suitable to high integration of the semiconductor device and provides less possibilities of occurrence of crystal defects.

Abstract: A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit includes one or more transistors fabricated silicon-on-insulator; a silicon substrate region outside the transistor(s) having a parasitic capacitance to be cancelled; a bootstrap terminal connected to the region outside the transistor(s); and a unity gain buffer responsive to the output of the transistor(s) and having its output connected to the bootstrap terminals for providing a voltage to the region outside the transistor(s) which follows the voltage developed on the parasitic capacitance and nullifies the parasitic capacitance.

Abstract: A semiconductor vacuum device including a semiconductor substrate 3, an insulator film 2 formed on the substrate 3, and a single crystal semiconductor film 1 formed on the insulator film 2. The single crystal semiconductor film 1 has a first and a second tapered edge opposite to one another but spaced apart over a gap formed in the insulator film 2. The first tapered edge acts 6 as a cathode and the second tapered edge acts as a gate 7, the substrate 1 acting as an anode into which said electrons emitted from the cathode above.

Abstract: A process for making metallized vias in diamond substrates is disclosed. The process involves laser-drilling a plurality of holes in a CVD diamond substrate and depositing tungsten, or a similar refractory metal, in the holes by low pressure CVD to provide substantially void-free metallized vias. Diamond substrates having metallized vias are also disclosed. The structures are useful for making multichip modules for high clock rate computers.

Abstract: A semiconductor device comprises a first electrode buried in one main face of a substrate and surrounded by a first insulator, a field oxide film covering the surface of the first electrode, a semiconductor layer connected with the first electrode, a second insulator covering the surface of the semiconductor layer, a second electrode connected with the semiconductor layer, a gate electrode connected with the semiconductor layer between the second insulator and the field oxide film, and an outgoing electrode connected with the first electrode.

Abstract: A thin film transistor having a larger ON-OFF current ratio is provided, in which a first insulating film having a first and second contact holes is formed on a substrate so as to cover a source and drain regions formed therein and a semiconductor film is formed on the first insulating film so as to be connected through the holes respectively to the source and drain regions. A second insulating film is formed on the semiconductor film and a gate electrode is formed thereon so as not be overlapped with the holes. In the offset region between each end of the gate electrode and the corresponding one of the holes, the insulation between the semiconductor film and the source and drain regions is provided by the first insulating film. This semiconductor film is weakly inverted by a drain voltage in the offset region, resulting in obtaining a leak current suppression action. The semiconductor film is preferable to be a polysilicon film.

Abstract: A high speed and highly functional MOSFET having a thin channel formed in a single crystalline layer is controlled by voltages applied to both an upper gate electrode and a buried gate layer that sandwich the channel therebetween.

Abstract: The substrate in a SOI structure is formed of a material with high heat conductivity, a U groove reaches substrate, the buried material inside the U groove is formed of a material with high heat conductivity, and the buried material is brought into contact with the substrate. With this arrangement, the drop in heat radiation effect can be improved while maintaining the enhancement of the resistance to the soft errors and the reduction of the parasitic capacitance on the bottom surface of the semiconductor element, so that the heat radiation effect can be made to approach the heat radiation effect of a semiconductor device having an insulated isolation region of the conventional U-groove structure. Further, in this case the speed and power product can be made better than the speed and power product of a semiconductor device having an insulated isolation region of the conventional U-groove structure.

Abstract: A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).

Abstract: A dielectric isolated substrate wherein a connecting polycrystalline silicon layer has smooth and flat surface on which a single crystal support is bonded and has a densified crystal structure, or is obtained by further heat treatment at 800.degree. C. or higher after deposition, or has no orientation as to growth direction of polycrystalline silicon, or a buffering layer is formed between a polycrystalline silicon layer and a single crystal support, is excellent in bonding between the single crystal support and the polycrystalline silicon layer by preventing voids at the bonded surface, while enhancing reliability.