With Metallic Conductor Within Isolating Dielectric Or Between Semiconductor And Isolating Dielectric (e.g., Metal Shield Layer Or Internal Connection Layer) Patents (Class 257/508)
  • Patent number: 10643927
    Abstract: Through-substrate vias (TSVs) extend through a high resistivity semiconductor substrate laterally spaced and isolated from an active device formed over the substrate by deep trench isolation (DTI) structures. The deep trench isolation structures may extend partially or entirely through the substrate, and may include an air gap. The deep trench isolation structures entirely surround the active device and the TSVs.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Shank, Ian McCallum-Cook, John Hall
  • Patent number: 10607979
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Patent number: 10497654
    Abstract: A semiconductor device includes an annular seal ring formed in a seal ring region surrounding a circuit forming region. The seal ring includes a BOX layer, an n-type semiconductor layer, and an annular electrode portion comprised of multiple layers of wirings. The electrode portion is electrically connected with the n-type semiconductor layer through a plug electrode.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 3, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Uchida, Yasutaka Nakashiba
  • Patent number: 10366956
    Abstract: A semiconductor device includes an integrated circuit, at least one outer seal ring, and at least one inner seal ring. The outer seal ring surrounds the integrated circuit. The outer seal ring includes a plurality of metal layers in a stacked configuration, and the metal layers are closed loops. The inner seal ring is disposed between the outer seal ring and the integrated circuit and separated from the outer seal ring. The inner seal ring has at least one gap extending from a region encircled by the inner seal ring to a region outside the inner seal ring.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen, Ho-Chun Liou
  • Patent number: 10361152
    Abstract: A semiconductor structure comprises a first conductive material-containing layer. The first conductive material-containing layer comprises a dielectric material, at least two conductive structures in the dielectric material, and an air-gap region in the dielectric material between the at least two conductive structures. The semiconductor structure also comprises a capping layer over the at least two conductive structures and the air-gap region. The semiconductor structure further comprises a second conductive material-containing layer over the capping layer. The second conductive material-containing layer comprises a via plug electrically connected to one of the at least two conductive structures. The via plug is separated from the air-gap region by at least a first predetermined distance. The semiconductor structure additionally comprises a conductive pad over the second conductive material-containing layer. The conductive pad is offset from the air-gap region by at least a second predetermined distance.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 10325867
    Abstract: A semiconductor device includes a high resistivity substrate, a transistor formed on the high resistivity substrate, and a deep trench device isolation region formed in the high resistivity substrate to surround the transistor. Particularly, the high resistivity substrate has a first conductive type, and a deep well region having a second conductive type is formed in the high resistivity substrate. Further, a low concentration well region having the first conductive type is formed on the deep well region, and the transistor is formed on the low concentration well region.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: June 18, 2019
    Assignee: DB Hitek Co., Ltd
    Inventor: Yong Soo Cho
  • Patent number: 10276518
    Abstract: A semiconductor arrangement in fan out packaging has a molding compound adjacent a side of a semiconductor die. A magnetic structure is disposed above the molding compound, above the semiconductor die, and around a transmission line coupled to an integrated circuit of the semiconductor die. The magnetic structure has a top magnetic portion, a bottom magnetic portion, a first side magnetic portion, and a second side magnetic portion. The first side magnetic portion and the second side magnetic portion are coupled to the top magnetic portion and to the bottom magnetic portion. The first side magnetic portion and the second side magnetic portion have tapered sidewalls.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Shiang Liao, Huan-Neng Chen
  • Patent number: 10224411
    Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Shekar Mallikarjunaswamy, Francois Hebert
  • Patent number: 10217740
    Abstract: A semiconductor device includes a high resistivity substrate, a first deep well region having a first conductive type and formed in the high resistivity substrate, a second deep well region having a second conductive type and formed on the first deep well region, a first well region having the first conductive type and formed on the second deep well region, and a transistor formed on the first well region.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: February 26, 2019
    Assignee: DB Hitek Co., Ltd
    Inventor: Yong Soo Cho
  • Patent number: 10170435
    Abstract: A method for forming a seal ring structure provides a semiconductor substrate having a first doping region formed over a top portion thereof. The method forms a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers has a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions, and then performs an etching process to a first doping region of the substrate. The method then removes the first doping region not covered by the patterned photoresist layers and forms a plurality of patterned first doping regions. The method then removes the patterned photoresist layers and forms an isolation region between and adjacent to the patterned first doping regions. Finally, the method forms a plurality of interconnect elements over the semiconductor substrate.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 1, 2019
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Chiyuan Lu, Chien-Chih Lin, Cheng-Chou Hung, Yu-Hua Huang
  • Patent number: 10164681
    Abstract: A semiconductor die comprises a first active device, at least one of a second active device and a passive component, and electromagnetic shielding configured to at least partially electromagnetically isolate the first active device from the at least one of the second active device and the passive component. The electromagnetic shielding includes one of a grounded metal layer and via stack, and a grounded metal layer disposed one of above and below the first active device.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 25, 2018
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Ambarish Roy, Nuttapong Srirattana
  • Patent number: 10062642
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: August 28, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Igarashi, Takuo Funaya
  • Patent number: 10062640
    Abstract: Semiconductor devices may include an internal circuit, a sealing region surrounding the internal circuit, and a decoupling capacitor region in the sealing region. The decoupling capacitor region may include decoupling capacitors. Each of the decoupling capacitors may include a first capacitor metal wiring pattern connected to a high power supply line, a second capacitor metal wiring pattern spaced apart from the first capacitor metal wiring pattern and connected to a low power supply line, and a dielectric pattern between the first capacitor metal wiring pattern and the second capacitor metal wiring pattern.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-yong Park, Jeong-hoon Ahn
  • Patent number: 10061967
    Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include first redistribution layers and second redistribution layers electrically connected to the connection pads and formed of one or more layers, at least one of the first redistribution layers is disposed between a plurality of insulating layers of the first connection member, and at least one of the second redistribution layers includes sensor patterns recognizing a fingerprint.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 28, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Ho Baek, Jung Hyun Cho, Byoung Chan Kim
  • Patent number: 10032860
    Abstract: A semiconductor device and a fabrication method are provided. The semiconductor device is fabricated by providing a substrate with a device area surrounded by a seal ring area, forming a buried deep-well layer in the substrate of the seal ring area, forming a first well region and a second well region in the substrate above the buried deep-well layer with the first well region surrounding the device area and the second well region surrounding the first well region, forming a heavily doped region in the substrate above the buried deep-well layer and between the first well region and the second well region, and forming a seal ring structure connecting to the heavily doped region. The buried deep-well layer, the first well region, and the second well region all have a first doping type while the heavily doped region and the substrate have a second doping type.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: July 24, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Jizhe Zhong, Zhihua Wu
  • Patent number: 9984979
    Abstract: The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Hyun Park, Han Kim, Kang Heon Hur, Young Gwan Ko, Jung Ho Shim
  • Patent number: 9929114
    Abstract: A bonding pad structure is provided. The structure includes a dielectric layer on a substrate. A bonding pad is disposed on the dielectric layer and a first metal pattern layer is embedded in the dielectric layer and directly below the bonding pad. The first metal pattern layer includes a first body portion and first island portions. The first body portion has first openings in a central region of the first body portion and second openings arranged along a peripheral region of the first body portion and surrounding the first openings. The first island portions are correspondingly disposed in the second openings and spaced apart from the first body portion. First interconnect structures are disposed in the dielectric layer and correspond to the first island portions, such that the bonding pad is electrically connected to the first island portions.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: March 27, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chi-Li Tu, Hung-Wei Chen, Shi-Hsiang Lu, Ching-Wen Wang
  • Patent number: 9929181
    Abstract: According to various embodiments, an electronic device may include a carrier including at least a first region and a second region being laterally adjacent to each other; an electrically insulating structure arranged in the first region of the carrier, wherein the second region of the carrier is free of the electrically insulating structure; a first electronic component arranged in the first region of the carrier over the electrically insulating structure; a second electronic component arranged in the second region of the carrier; wherein the electrically insulating structure includes one or more hollow chambers, wherein the sidewalls of the one or more hollow chambers are covered with an electrically insulating material.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 27, 2018
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Thoralf Kautzsch, Alessia Scire, Steffen Bieselt, Franz Hirler, Anton Mauder, Wolfgang Scholz, Hans-Joachim Schulze, Francisco Javier Santos Rodriguez
  • Patent number: 9922940
    Abstract: A semiconductor device includes a substrate, and interconnects provided above the substrate. The device further includes a first insulator that is provided on the interconnects and on air gaps provided between the interconnects, surrounds the interconnects from lateral sides of the interconnects, and is formed of a first insulating material. The device further includes a second insulator that surrounds an interconnect region including the interconnects and the air gaps from the lateral sides of the interconnects through the first insulator, includes no portion provided between the interconnects, and is formed of a second insulating material different from the first insulating material.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: March 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Watanabe, Takeshi Arakawa
  • Patent number: 9911627
    Abstract: A method for processing a 3D semiconductor device, the method including: processing a first layer comprising first transistors, forming a first power distribution grid to provide power to the first transistors, processing a second layer overlying the first transistors and including second transistors, where the second layer includes a through layer via with diameter of less than 150 nm, forming a second power distribution grid overlaying the second transistors, where the first power distribution grid includes first power conductors and the second power distribution grid includes second power conductors, and where the second power conductors are substantially wider or thicker than the first power conductors, and where the device includes a plurality of vias to connect the second power distribution grid to the first power distribution grid.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: March 6, 2018
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 9892921
    Abstract: Various embodiments provide semiconductor devices and methods for forming the same. A base including a substrate and an interlayer dielectric layer is provided. The base has a first region and a second region that have an overlapped third region. A mask layer having a stacked structure is formed on the interlayer dielectric layer at the overlapped third region. Using the mask layer as an etching mask, the interlayer dielectric layer at the first region at both sides of the mask layer is etched, to expose the substrate and form a first contact via at the first region. Using the mask layer as an etching mask, the interlayer dielectric layer at the second region at both sides of the mask layer is etched, to form a second contact via at the second region. A conductive layer is formed to fill the first contact via and the second contact via.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: February 13, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiyang He, Chenglong Zhang
  • Patent number: 9881878
    Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: January 30, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Tomoyuki Yamada, Fumio Ushida, Shigetoshi Takeda, Tomoharu Awaya, Koji Banno, Takayoshi Minami
  • Patent number: 9865500
    Abstract: A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 9824954
    Abstract: An integrated circuit device comprises N stacked first integrated circuit chips each of which includes a first circuit and N stacked second integrated circuit chips each of which includes a second circuit. The N stacked second integrated circuit chips are stacked on the N stacked first integrated circuit chips. A first and second integrated circuit chips at symmetric positions with respect to a reference surface are paired. Each of the first and second integrated circuit chips include connection terminals for connecting the first circuit of the first integrated circuit chip and the second circuit of the second integrated circuit chip in the pair, and through electrodes each penetrating an inside of the chip. The connection terminals and through electrodes are arranged to be symmetric with respect to the reference surface.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: November 21, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takayuki Kamiya
  • Patent number: 9728538
    Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 8, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 9698237
    Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: July 4, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Shekar Mallikarjunaswamy, Francois Hebert
  • Patent number: 9691685
    Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: June 27, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-Ha Lee, Hyung-Jun Jeon, Jum-Yong Park, Byung-Lyul Park, Ji-Soon Park, Jin-Ho An, Jin-Ho Chun
  • Patent number: 9679896
    Abstract: A moisture blocking structure includes an active fin disposed on a sealing region of a substrate, the substrate including a chip region and the sealing region surrounding a periphery of the chip region, the active fin continuously surrounding the chip region and having a winding line shape in a plan view. A gate structure covers the active fin and surrounds the periphery of the chip region. A conductive structure is disposed on the gate structure, the conductive structure surrounding the periphery of the chip region.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: June 13, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Soo Yoon, Min-Kwon Choi, Yang-Soo Son, Hyun-Jo Kim, Han-Ii Yu
  • Patent number: 9613878
    Abstract: According to various embodiments, a carrier may be provided, the carrier including: a hollow chamber spaced apart from a surface of the carrier; a trench structure extending from the surface of the carrier to the hollow chamber and laterally surrounding a first region of the carrier, the trench structure including one or more trenches extending from the surface of the carrier to the hollow chamber, and one or more support structures intersecting the one or more trenches and connecting the first region of the carrier with a second region of the carrier outside the trench structure, wherein the one or more support structures including an electrically insulating material.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: April 4, 2017
    Assignee: Infineon Technologies Dresden GmbH
    Inventor: Steffen Bieselt
  • Patent number: 9601564
    Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: March 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Xu Cheng, Daniel J. Blomberg, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9583442
    Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 28, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Su Chen Fan, Sukwon Hong, William J. Taylor, Jr.
  • Patent number: 9570378
    Abstract: A semiconductor device includes a substrate including a circuit region, a dummy region, and a dummy clearance section surrounding the circuit region, and a plurality of dummy patterns formed in the dummy region, the plurality of dummy patterns comprising a first dummy pattern and a second dummy pattern, a distance between the first dummy pattern and the circuit region being less than a distance between the second dummy pattern and the circuit region, and a dummy pattern being absent between the first dummy pattern and the circuit region. The first dummy pattern includes an area which is greater than an area of the second dummy pattern.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: February 14, 2017
    Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.
    Inventor: Yorio Takada
  • Patent number: 9502359
    Abstract: Embodiments of shielding apparatuses are disclosed herein. In some embodiments, a shielding apparatus may include first and second conductive regions and a plurality of vias disposed between the first and second conductive regions. The first and second conductive regions and the plurality of vias may surround an integrated circuit (IC) component and individual vias of the plurality of vias are spaced relative to one another to shield incoming or outgoing electromagnetic interference (EMI). Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: November 22, 2016
    Assignee: INTEL CORPORATION
    Inventors: Nicholas P. Cowley, Ruchir Saraswat
  • Patent number: 9490286
    Abstract: A photoelectric conversion device according to the present invention has a plurality of photoreceiving portions provided in a substrate, an interlayer film overlying the photoreceiving portion, a large refractive index region which is provided so as to correspond to the photoreceiving portion and has a higher refractive index than the interlayer film, and a layer which is provided in between the photoreceiving portion and the large refractive index region, and has a lower etching rate than the interlayer film, wherein the layer of the lower etching rate is formed so as to cover at least the whole surface of the photoreceiving portion. In addition, the layer of the lower etching rate has a refractive index in between the refractive indices of the large refractive index region and the substrate. Such a configuration can provide the photoelectric conversion device which inhibits the lowering of the sensitivity and the variation of the sensitivity among picture elements.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: November 8, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Sakae Hashimoto
  • Patent number: 9460967
    Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: October 4, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusaku Asano, Kazuhito Higuchi, Taizo Tomioka, Tomohiro Iguchi
  • Patent number: 9455221
    Abstract: The invention relates to a field of semiconductor manufacturing technology, more particularly, to a method for preparing three-dimensional integrated inductor-capacitor structure, which can realize the inductor-capacitor of three-dimensional structure, and form three-dimensional spiral inductor centering on the magnetic cores of single direction around through the preparation of the interconnected top metal conducting wires and bottom metal conducting wires, which can gain capacitance and inductance at the same time in a relatively small space, and reduce the production costs, and also greatly improves the inductance magnetic flux in order to increase the inductance value and reduce eddy current, and improve the quality factor Q value and the performance of inductance coil.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: September 27, 2016
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shaoning Mei, Shaofu Ju, Jifeng Zhu
  • Patent number: 9443764
    Abstract: A method and structure for eliminating through silicon via poor reveal is disclosed. In one embodiment, the method includes obtaining a wafer having a front side, a back side and partially etched and metalized through silicon vias each extending from a portion of the front side through a portion of the back side, terminating before reaching an end surface of the back side. A region of the back side of the wafer is patterned and etched to expose and reveal a portion of each of the plurality of through silicon vias. A metal layer is deposited on the back side of the wafer to form a back side metallization. The metal layer covers all of the back side including the etched region of the back side and the exposed portions of each of the through silicon vias.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: September 13, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Jeffrey C. Maling, Anthony K. Stamper, Zeljka Topic-Beganovic, Daniel S. Vanslette
  • Patent number: 9437829
    Abstract: An organic light emitting display device and a method of manufacturing the same are proposed. The organic light emitting display device includes: a first film formed of an organic material, and having first and second surfaces facing each other and a third surface perpendicular to the first and second surfaces; a second film formed on the first film to cover the second and third surfaces of the first film; an organic light emitting unit disposed on the second film; a third film disposed on the second film to cover the organic light emitting unit; and a fourth film disposed on the third film, formed of an organic material, and having fourth and fifth surfaces facing each other, wherein the fifth surface faces the third film.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: September 6, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae-Woong Kim, Hyun-Woo Koo, Hyung-Sik Kim
  • Patent number: 9412758
    Abstract: A disclosed embodiment is a semiconductor on insulator (SOI) structure comprising a buried oxide layer over a bulk semiconductor layer, and a device layer over the buried oxide layer. At least one transistor is fabricated in the device layer, wherein a source/drain junction of the transistor does not contact the buried oxide layer, thereby causing the source/drain junction to have a source/drain junction capacitance. The SOI structure also comprises at least one trench extending through the device layer and contacting a top surface of the buried oxide layer, thereby electrically isolating the at least one transistor. In one embodiment the at least one trench is formed after fabrication of the at least one transistor and is filled with only dielectric. In one embodiment, one or more wells may be formed in the device layer. In one embodiment the bulk semiconductor layer has a high resistivity of typically about 1000 ohms-centimeter or greater.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: August 9, 2016
    Assignee: Newport Fab, LLC
    Inventors: Robert L. Zwingman, Marco Racanelli
  • Patent number: 9406634
    Abstract: A package includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis, wherein the first work piece is rigid, and an entirety of the metal trace is on the first work piece. The package further includes a second work piece with a plurality of elongated bumps, wherein at least one of the plurality of elongated metal bumps has a second axis and at least another of the plurality of elongated metal bumps has a third axis, wherein the second and the third axes are not the same and the second axis is at a non-zero angle from the first axis, wherein the plurality of elongated bumps are electrically connected to the metal trace.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuh Chern Shieh, Han-Ping Pu, Yu-Feng Chen, Tin-Hao Kuo
  • Patent number: 9385278
    Abstract: Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: July 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Xiaolong Fang, Lifang Xu, Tingkai Li, Thomas Gehrke
  • Patent number: 9312335
    Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 12, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Shekar Mallikarjunaswamy, François Hébert
  • Patent number: 9281281
    Abstract: Embodiments of shielding apparatuses are disclosed herein. In some embodiments, a shielding apparatus may include first and second conductive regions and a plurality of vias disposed between the first and second conductive regions. The first and second conductive regions and the plurality of vias may surround an integrated circuit (IC) component and individual vias of the plurality of vias are spaced relative to one another to shield incoming or outgoing electromagnetic interference (EMI). Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: March 8, 2016
    Assignee: INTEL CORPORATION
    Inventors: Nicholas P. Cowley, Ruchir Saraswat
  • Patent number: 9252213
    Abstract: Integrated circuits with a buried N layer and methods for fabricating such integrated circuits are provided. The method includes forming a buried N layer overlying a substrate, and forming a monocrystalline layer overlying the buried N layer. After forming the monocrystalline layer, a well tap trench is formed, where the well tap trench penetrates the electronics area and the buried N layer and extends into the substrate. A well tap is formed in the well tap trench.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: February 2, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zhang Guowei, Purakh Raj Verma
  • Patent number: 9245790
    Abstract: Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate. A through-semiconductor via is formed in the semiconductor substrate, and an interlayer dielectric layer is formed that overlies the through-semiconductor via and the plurality of semiconductor devices. A first interconnect via is embedded within the interlayer dielectric layer, and a second interconnect via is embedded within the interlayer dielectric layer. The first interconnect via and the second interconnect via are in electrical communication with the through-semiconductor via at spaced locations from each other on the through-semiconductor via.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Sarasvathi Thangaraju, Chun Yu Wong
  • Patent number: 9245800
    Abstract: To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: January 26, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masazumi Matsuura
  • Patent number: 9159777
    Abstract: In various embodiments, a die arrangement may be provided. The die arrangement may include a die, at least one bond pad, at least one redistribution trace electrically connecting the die with the at least one bond, and at least one inductor enclosing the at least one bond pad and the at least one redistribution trace.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: October 13, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Georg Meyer-Berg
  • Patent number: 9159730
    Abstract: A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: October 13, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Ik Kim, Ho-In Ryu, Nak-Jin Son, Yoo-Sang Hwang
  • Patent number: 9142668
    Abstract: A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 22, 2015
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant Agarwal, Vipindas Pala, John Palmour
  • Patent number: 9093462
    Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: July 28, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Vidhya Ramachandran, Brian M. Henderson, Shiqun Gu, Chiew-Guan Tan, Jung Pill Kim, Taehyun Kim