Abstract: A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field oxide layer. In a further embodiment, the polysilicon layer comprises a bottom conductor layer in the antifuse. In another embodiment, a refractory metal silicide layer is formed between the polysilicon layer and the antifuse. In yet a further embodiment, the refractory metal silicide layer comprises the bottom conductor layer in the antifuse.

Abstract: This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second poly-silicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate.

Abstract: An improved anti-fuse structure is formed on a silicon substrate of a first conductivity type. The anti-fuse has a first conductive layer formed on a surface of substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer. The second conductive layer has a portion extending beyond the dielectric layer above the surface of the substrate. A third conductive layer is contacted to this portion of the second dielectric layer. The anti-fuse further includes a well region having a graded doping profile formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted. The well region has a second conductivity type that is opposite the first conductivity type.

Abstract: A thin-film transistor (TFT) which has a crystalline silicon active layer of excellent reliability and characteristics, and a method of fabricating such a TFT inexpensively are provided. In a TFT which has at least two low density impurity regions and a source/drain adjacent to a channel-forming region, catalyst elements which cause amorphous silicon to crystallize are included in the source/drain, and the density of said catalyst elements in the interface between the channel-forming region and the low-density impurity regions is less than that in the source/drain.

Abstract: The invention relates to an erasable non-volatile memory in which a diode is formed at each point of intersection between the x-selection lines (Ki) and y-selection lines (Rj), of which diode the anode and cathode are conductively connected to the x- and y-selection lines. The diodes are formed in hydrogenated amorphous silicon or silicon compounds such as amorphous Si−xGex. Writing takes place by means of a current pulse through selected diodes. The current in the forward direction becomes much lower, for example a few hundred times lower, than in diodes which are not selected, probably owing to degradation in the semiconductor material. The diodes may be returned to their original state again (i.e. be erased) through heating, for example at a temperature of 200° C. during 100 minutes. Preferably, the diodes are formed by Schottky diodes because the characteristic in the reverse direction does not (substantially) change in this type of diode.

Abstract: The present invention provides antifuses that enhance the efficiency of a field programmable gate array and that decrease chip size. The antifuses comprise a plurality of first conductive layers formed on a substrate, an antifuse layer formed on a plurality of the first conductive layers, and a second conductive layer formed on the antifuse layer. A method of fabricating the antifuses comprises the steps of forming a plurality of first conductive layers on predetermined portions of a substrate, forming an insulating layer over the surface of the substrate, selectively etching the insulating layer to form a via hole that is connected with a plurality of the first conductive layers, forming an antifuse layer on a predetermined portion of the insulating layer, including the via hole, and forming a second conductive layer on a predetermined portion of the insulating layer, including the antifuse layer.

Abstract: A dielectric-based anti-fuse cell and cell array, that include a doped polysilicon contact plug, with a low resistance in the programmed state, a low capacitance, and a small cell area. The dielectric-based anti-fuse cell includes a first insulating layer, typically SiO2, on the surface of a semiconductor substrate. A first doped polysilicon (poly 1) layer is on the upper surface of the first insulating layer and a second insulating layer is over the poly 1 layer. A doped polysilicon contact plug extends through the second insulating layer and into the poly 1 layer. A dielectric layer, typically either an ONO or NO dielectric composite layer, covers the upper surface of the doped polysilicon contact plug. A second doped polysilicon (poly 2) layer is disposed on the dielectric layer. A process for manufacturing the anti-fuse cell and array includes first providing a semiconductor substrate and forming a first insulating layer on its surface. Next a poly 1 layer (e.g.

Abstract: The anti-fuse circuit includes three sub-blocks: a multiplexer having inputs of control signals and addresses and yielding the activation of a programming signal and program addresses; a programming voltage generator consisting of an oscillator and a charge pump; and an anti-fuse unit circuits for the program/read of anti-fuse states. For an anti-fuse program at the special test mode, a program address generation circuit having inputs of control signals and addresses activates the programming voltage generator and makes a special or program address for selection of anti-fuse. In the normal mode, the program address generation circuit and an internal power generator remain at an inactive state. In anti-fuse unit circuit, the program address and the programming voltage signal from the programming voltage generator serve to switch the terminal of the anti-fuse up to a programming voltage level when the anti-fuse is selected for programming of anti-fuse elements.

Abstract: For use with a sub-micron semiconductor process, a trench isolation process enables the formation of a wider isolation oxide around the shallow trench isolation (STI) opening. The wider oxide width minimizes the recessing of oxide along the trench sidewalls during subsequent cleaning and etching steps. In a method for forming STI regions on a silicon substrate having a buffer oxide thereon and a nitride layer on top of the buffer oxide, a mask layer is defined on the nitride layer patterning isolation regions in unmasked areas of the nitride layer. Isolation regions of sufficient depth are etched through in unmasked areas of the nitride layer, the buffer oxide and into the silicon substrate. Performing a lateral etch (a nitride shaving) of the nitride layer under the mask layer undercuts a portion of the nitride layer under the mask layer. After the lateral etch, the mask layer is removed.

Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: An improved antifuse which employs the base-emitter junction of a silicided single polysilicon bipolar transistor. The distance between the base metal and emitter metal is shortened and results from self aligning process steps rather than lithographic steps, resulting in a lower and better controlled programming voltage, programming energy and ON state resistance. Typically the conductive filament formed in the new antifuse is about 0.65 microns long and is formed by a voltage pulse having a relatively slow rise time (e.g. 150 microseconds), resulting in improved properties which provide advantages in circuit design and in manufacturing circuits using the new antifuse.

Abstract: A microcrystal silicon film is formed on a substrate by using a silicide gas, a hydrogen gas, and a source gas that enables introduction of a metal element for accelerating crystallization of silicon in a capacitance-coupling plasma CVD apparatus. The action of the metal element provides a high film forming rate. Therefore, a technique for forming a microcrystal silicon film with high quality and high film forming rate can be provided.

Abstract: Systems and methods are described for semiconductor wafer pretreatment. A method of increasing the selectivity of silicon deposition with regard to an underlying oxide layer during deposition of a silicon containing material by broadening a selective temperature of formation window for said silicon containing material by decreasing a lower temperature endpoint includes: providing a semiconductor wafer with the underlying oxide layer in a processing chamber; then pumping water from then processing chamber; and then depositing the silicon containing material on the semiconductor wafer. A step of seeding the semiconductor wafer can be conducted by exposing the semiconducotor wafer to a germanium containing gas. A chlorine containing precursor and/or hydrogen can be introduced into the processing chamber to increase the selectivity of the silicon containing material to the underlying oxide. The selective HSG temperature of formation window is widened.

Abstract: A device structure provides improved efficiency of light emission from a light emitting element made of silicon while rendering such emission electrically controllable. Silicon in the light emitting element comprises fine microcrystals, which are miniaturized sufficiently to cause a quantum size effect. The microcrystals may be 10 nanometers (nm) or less in grain size. A dielectric film of 5 nm thick or less is formed containing therein such microcrystals. The microcrystal structure section is disposed between p- and n-type semiconductor layers. These layers are brought into electrical contact with the microcrystal structure only, while causing the remaining portions to be electrically insulative by a dielectric film or the like. Elementary particles of the opposite polarities, e.g. electrons and holes, are injected by tunnel effect into the microcrystals resulting in emission of light rays with increased efficiency.

Abstract: An electrode structure for use in a chalcogenide memory is disclosed. The electrode has a substantially frusto-conical shape, and is preferably formed by undercut etching a polysilicon layer beneath an oxide pattern. With this structure, improved current densities through the chalcogenide material can be achieved.

Abstract: A method of manufacturing a semiconductor includes the steps of: forming a first semiconductor film on a substrate having an insulating surface; applying an energy to the first semiconductor film to crystallize the first semiconductor film; patterning the first semiconductor film to form a region that forms a seed crystal; etching the seed crystal to selectively leave a predetermined crystal face in the seed crystal; covering the seed crystal to form a second semiconductor film; and applying an energy to the second semiconductor film to conduct a crystal growth from the seed crystal in the second semiconductor film.

Abstract: To provide a semiconductor device having a function equivalent to that of IGFET, an activation layer is formed by a crystal silicon film crystallized by using a catalyst element helping promote crystallization and a heating treatment is carried out in an atmosphere including a halogen element by which the catalyst element is removed, the activation layer processed by such steps is constituted by a peculiar crystal structure and according to the crystal structure, a rate of incommensurate bonds in respect of all of bonds at grain boundaries is 5% or less (preferably, 3% or less).

Abstract: An improved anti-fuse structure is formed on a silicon substrate of a first conductivity type. The anti-fuse has a first conductive layer formed on a surface of the substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer. The second conductive layer has a portion extending beyond the dielectric layer above the surface of the substrate. A third conductive layer is contacted to this portion of the second dielectric layer. The anti-fuse further includes a well region having a graded doping profile formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted. The well region has a second conductivity type that is opposite the first conductivity type.

Abstract: An integrated circuit and fabrication method for an antifuse structure that includes a shallow trench oxide isolation region disposed in a silicon substrate, the oxide in the trench having a top surface recessed below the surface of the substrate to form sharp corners at each side of the trench. The substrate includes diffusion regions adjacent to the sharp corners, electrical insulation layers over the diffusion regions, and an electrical conductor is disposed over the recessed oxide in the trench. When voltage is applied on the electrical conductor, a high field point is produced at the sharp corners causing the electrical insulation layer at the corners to break down and create a short circuit between the electrical conductor and the diffusions, thus providing a fuse function.

Abstract: The present application discloses a metal-to-metal antifuse with an amorphous carbon dielectric which provides a very high resistance off state and can be programmed at voltages compatible with deep submicron devices. Furthermore, the programmed filament achieves low resistance with low programming current while maintaining a high level of stability.

Abstract: A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.

Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 .mu.m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

Abstract: A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film 103 disposed on a quartz substrate 101. A crystal silicon film 105 is obtained by this heat treatment. Then, a oxide film 106 is formed by wet oxidation. At this time, the nickel element is gettered to the oxide film 106 by an action of fluorite. Then, the oxide film 106 is removed. Thereby, a crystal silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm.sup.2 /Vs and an S value smaller than 100 mV/dec. can be obtained.

Abstract: The present invention is an antifuse structure comprising an insulation layer between a top conductor and a bottom conductor. The insulation layer has a via. A resistive layer is adjacent the via and a plug is adjacent the resistive layer. The plug is in the via and is also adjacent the top conductor.The present invention also provides a method for fabricating the antifuse on a base. A bottom conductor is deposited on the base. An insulation layer are deposited adjacent the bottom conductor. An antifuse via is etched into the insulation layer. A resistive layer is deposited in the antifuse via. A plug is deposited. The plug extends into the antifuse via. A top conductor is deposited and patterned adjacent the plug.

Abstract: Semiconductor devices such as thin-film transistors formed by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

Abstract: In those thin-film transistors (TFTs) employing as its active layer a silicon film crystallized using a metal element, the objective is to eliminate bad affection of such metal element to the TFT characteristics. To this end, in a TFT having as its active layer a crystalline silicon film that was crystallized using nickel (Ni), those regions corresponding to the source/drain thereof are doped with phosphorus; thereafter, thermal processing is performed. During this process, nickel residing in a channel formation region is "gettered" into previously phosphorus-doped regions. With such an arrangement, it becomes possible to reduce the Ni concentration in certain regions in which lightly-doped impurity regions will be formed later, which in turn enables suppression of affection to TFT characteristics.

Abstract: A method of forming an Si film by a bias sputtering process comprises the steps of generating plasma between a target electrode holding a target material provided in a vacuum container and a substrate electrode holding a deposited film forming substrate, provided opposingly to the target electrode, by the use of a high-frequency energy to cause the target material to undergo sputtering, and applying a bias voltage to at least one of the target electrode and the substrate electrode to form an Si film comprised of atoms deposited by sputtering on the substrate, wherein;a mixed-gas environment comprising a mixture of an inert gas and a hydrogen gas is formed in the vacuum container, and the target material is subjected to sputtering while controlling H.sub.2 O gas, CO gas and CO.sub.2 gas in the mixed-gas environment to have a partial pressure of 1.0.times.10.sup.-8 Torr or less each, to form an epitaxial film on the substrate while maintaining a substrate temperature in the range of from 400.degree. C. to 700.

Abstract: An anti-fuse structure and method for forming such structure. In one embodiment, the anti-fuse structure of the present invention includes a dielectric layer which is deposited over a metal layer. The semiconductor substrate is then masked and etched so as to form openings in the dielectric layer. Metal is deposited over the semiconductor substrate and is polished so as to remove the metal which overlies the dielectric layer so as to form a plug which extends through the dielectric layer and which electrically connects to the metal layer. An amorphous silicon block is then deposited, masked and etched so as to form an amorphous silicon block over the plug. A metal layer is then deposited, masked and etched so as to form an interconnect. The amorphous silicon block lies between the metal layer and the interconnect so as to prevent the flow of electrical current until such time as the anti-fuse is activated.

Abstract: An electronic circuit device includes first and second conductors and a high-resistance member arranged therebetween. The high-resistance member consists of a material which changes from a high resistivity state to a low resistivity state in accordance with a voltage applied between the first and second conductors.

Abstract: An antifuse comprises an antifuse material disposed between a lower conductive electrode and an upper conductive electrode. The antifuse material comprises a layer of amorphous silicon disposed between two layers of silicon nitride. A thin layer of silicon dioxide is disposed between the layer of amorphous silicon and one of the silicon nitride layers.

Abstract: An amorphous-silicone-based antifuse structure has been invented for VLSI (Very Large Scale Integration circuits) FPGA's (Fields Programmable Gate Array) applications. The structure comprises from top to bottom a first Al layer/a first i-a-SiC:H layer/an i-a-SiH layer/a second i-a-SiC:H layer/a second Al layer, which is basically a MIM (Metal/Insulator/Metal) structure. The MIM structure offers such major advantages as simple for preparation and low in cost. Due to use of the Al layer as an electrode metal and use of a PECVD system for the preparation of the amorphous silicon materials, the antifuse structure is compatible with that of general VLSI devices. In addition, due to a difference in the thickness of barrier enhancement layers in the first and the second i-a-SiC:H layer, a programmed voltage can be adjusted easily and applied in many fields. This structure has a very low on-resistance as the antifuse structure breakdown. The anitifuse has a high resistance (i.e.

Abstract: Disclosed is an apparatus and method for manufacturing antifuse structures on topographically varying silicon substrates. The antifuse structures are intelligently formed over topographically lower silicon substrate regions such that subsequent via hole etching processes do not over-etch underlying antifuse structures. Also discloses an apparatus and method for designing dummy metallization and polysilicon features in close proximity to antifuse structures such that subsequently deposited dielectric materials are induced to form thicker dielectric layers over antifuse structures. Advantageously, subsequent via hole etching does not substantially remove antifuse structure materials with may cause detrimental ionic contamination or antifuse infant mortality. In this manner, standard via hole etching techniques may be implemented for all inter-layer via holes without concern the concern of over-etching sensitive underlying devices.

Abstract: A metal-to-metal antifuse disposed between two aluminum metallization layers in a CMOS integrated circuit or similar structure includes an antifuse material layer having a substantially aluminum-free conductive link. The substantially aluminum-free link is formed by forming a first barrier metal layer out of TiN having a first thickness, a second barrier metal layer out of TiN having a second thickness which may be less than said first thickness, the first and second barrier metal layers separating the antifuse material layer from first and second electrodes. The antifuse is programmed by applying a voltage potential capable of programming the antifuse across the electrodes with the more positive side of the potential applied to the electrode adjacent the barrier metal layer having the least thickness.

Abstract: Regions 106 which can be regarded as being monocrystalline are formed locally by irradiating with laser light, and at least the channel-forming region 112 is constructed using these regions. With thin-film transistors which have such a construction it is possible to obtain characteristics which are similar to those which employ monocrystals. Further, by connecting in parallel a plurality of such thin-film transistors it is possible to obtain characteristics which are effectively equivalent to those of a monocrystalline thin-film transistor in which the channel width has been increased.

Abstract: A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse.

Abstract: A method of fabricating an antifuse structure for field programmable gate array (FPGA) applications is described. First, a field oxide layer for isolation is grown on the semiconductor silicon substrate. Then, a bottom electrode, a thin dielectric layer and a first top electrode layer are sequentially deposited on the surface of the field oxide layer. Next, a photoresist layer is coated on the surface of the first top electrode layer. Then, the first top electrode layer is patterned to form a top electrode stud. Next, a layer of silicon dioxide (SiO.sub.2) is deposited by Liquid Phase Deposition (LPD) to improve the overall profile of the antifuse structure. Thereafter, the photoresist pattern is removed. Next, a second top electrode layer is deposited overlaying the LPD-SiO.sub.2 layer and the top electrode stud. The top electrode that consists of the second top electrode layer and the top electrode stud is completed. The antifuse structure of FPGAs is accomplished.

Abstract: A programmable semiconductor element having an antifuse structure is disclosed. A first insulation film is formed on a silicon substrate. First and second conductors are formed on the first insulation film. The first and second conductors are spaced apart at a contact hole region. A second insulation film is formed on the first insulation film and the first and second conductors. The second insulation film includes a contact hole at a portion corresponding to the contact hole region. The second insulation film includes a recess adjacent to the contact hole. A conductor link is formed in the recess in the second insulation film. A third insulation film is formed over the conductor link.

Abstract: The invention is an improved process for forming isolations of uniform thickness in narrow and wide trenches. The process begins by forming a pad layer on a semiconductor substrate. A first barrier layer is formed on the pad layer. The first barrier layer and pad layer are patterned forming openings, thereby exposing the substrate surface. The substrate is then etched through the openings to form shallow trenches in the substrate. The trenches generally falling into two ranges of width: narrow trenches having widths in the range between 0.3 .mu.m and 1.0 .mu.m; and wide trenches having widths greater than 1.0 .mu.m. A thin oxide film is grown on the sidewalls and bottoms of the trenches. A gap-fill dielectric layer is formed on the thin oxide film. A polysilicon layer is grown on the gap-fill dielectric layer. The polysilicon layer acts as a stop during CMP, providing additional protection of the gap-fill dielectric layer in the wide trenches. A planarizing material layer is formed on the polysilicon layer.

Abstract: An antifuse comprises a lower electrode formed from a metal layer in a microcircuit. A interlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is etched back to create a raised portion of the plug. The upper edges of the plug are rounded. An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon nitride sandwich incorporating a thin silicon dioxide layer above or below the amorphous silicon layer or such a sandwich structure covered by a titanium nitride layer, is disposed above the plug. An upper electrode, preferably comprising a metal layer is disposed over the antifuse layer.

Abstract: A process electrostatic discharge ("ESD") protection device is incorporated on a chip with the antifuses that it is designed to protect and is formed as close in time as possible to the deposition of the antifuse material layer (the layer being protected) so that ESD protection is available at all practical stages of processing. According to a first aspect of the invention, an ESD protection device is formed by exposing edges of an antifuse bottom electrode during the antifuse cell open mask/etch step. It is biased on during processing. A sharp corner of the electrode and a deep aspect ratio provide degrade antifuse performance for the protection cell (resulting in reduced breakdown voltage and increased leakage current) and, as designed, the protection cell will rupture before other cells because it has a lower breakdown voltage. Once the protection cell ruptures, it will continue to conduct and protect other antifuses from ESD damage.

Abstract: A method of integrating a low aspect ratio antifuse into low capacitance interconnect levels which involves fabrication of an antifuse base which is self-aligned to either a lower interconnect level or the antifuse dielectric. The method provides maximum allowable registration tolerance for the antifuse onto its base without incurring any increase in the pitch of the interconnect. The antifuse base is required to minimize the capacitance between the lower and upper interconnect levels. This is accomplished by providing over a lower interconnect pattern, such as, for example, aluminum over titanium tungstide (TiW), a barrier metal, such as, for example, TiW. The barrier metal separates one of the interconnect layers from the amorphous silicon dielectric. The barrier metal also acts as a raised base for the antifuse, providing increased spacing between the upper and lower interconnect patterns, thereby minimizing the capacitance therebetween.

Abstract: A two-terminal fuse-antifuse structure comprises a horizontal B-fuse portion and a vertical A-fuse portion disposed between two metallization layers of an integrated circuit device. The two-terminal fuse-antifuse can be programmed with a relatively high current applied across the two terminals to blow the B-fuse, or with a high voltage applied across the two terminals to program the A-fuse. Such a device, connected between two circuit nodes, initially does not provide an electrical connection between the two circuit nodes. It may then be programmed with a relatively high voltage to blow the A-fuse, causing it to conduct between the two circuit nodes. Then, upon application of a relatively high current between the two circuit nodes, the B-fuse will blow, making the device permanently non-conductive.

Abstract: A one-time non-conductive programmable element which is programmable to conduct current is provided. The programmable element comprises several anti-fuses connected in parallel with each other. According to one embodiment of the present invention, each anti-fuse of the programmable element includes first and second conductive plates and a dielectric layer between the two conductive plates. The first conductive plates of all anti-fuses are connected to each other and the second conductive plates of the anti-fuses are connected to each other to form the programmable element of the present invention. The programmable element provides a larger total surface area of the dielectric layer through several anti-fuses that are connected in parallel with each other.

Abstract: A device having a switch comprises a chromium layer and an adjacent semiconductor layer. The fraction of voids in the chromium layer is less than 10%, preferably less than 2%. The chromium layer in the device comprises traces of neon with a concentration of less than 0.1 at. %. Chromium layers are deposited on a substrate by means of a sputter deposition process. By using neon as the working gas at pressures of less than 1 Pa, preferably in the range from 0.2 Pa to 0.5 Pa, the sputter-deposited chromium layers are substantially free of internal stress and have a density which is approximately equal to that of bulk chromium.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: An antifuse comprises a substantially planar conductive lower electrode covered by a first layer of silicon nitride. A layer of amorphous silicon is disposed over the silicon nitride layer. A first dielectric layer is disposed over the surface of the amorphous silicon layer and has a first aperture therethrough communicating with the amorphous silicon layer. A second layer of silicon nitride is disposed over the first dielectric layer and in the first aperture. A conductive upper electrode, such as a layer of titanium nitride, is disposed over the second layer of silicon nitride. A second dielectric layer is disposed over the surface of the conductive upper electrode and has a second aperture therethrough in alignment with the first aperture communicating with the conductive upper electrode. An overlying metal layer is disposed over the surface of the second dielectric layer and in the second aperture making electrical contact with the conductive upper electrode.

Abstract: A programming circuit programs an anti-fuse having first and second terminals with the programming circuit and the anti-fuse being fabricated in the same integrated circuit. The programming circuit includes a first external terminal of the integrated circuit coupled to the first terminal of the anti-fuse. The first external terminal is adapted to receive a first programming voltage having a predetermined polarity. A second external terminal of the integrated circuit is adapted to receive a second programming voltage having a polarity opposite that of the first programming voltage. A voltage translation circuit is coupled between the second external terminal and the second terminal of the anti-fuse and includes an enable terminal adapted to receive an enable signal. The voltage translation circuit is operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active.

Abstract: An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug including a conductive barrier material such as TiN or TiW to contact the anti-fuse material and overlie the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separaged from the anti-fuse layer by at least one-half the depth of the via hole. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.