Abstract: A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures.A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.

Abstract: An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

Abstract: According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.

Abstract: A method for forming an antifuse interconnect structure, for a one-time fusible link, to be used with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the amorphous silicon layer protected by a thin barrier layer, during the patterning procedure. The protected antifuse layer results in a reproducible thickness, and thus reproducible pulsing voltages, needed for rupturing of the antifuse layer. Planarization of an underlying metal plug, via an insulator refill procedure, offers a smooth surface for the overlying antifuse layer.

Abstract: A stress relaxation layer is inserted between an electrode layer and an antireflection layer to relax a stress imparted from one of the electrode and antireflection layers to the other. A semiconductor device is provided which can suppress separation of the antireflection film during device fabrication processes and dispense with the process of etching and removing the antireflection film.

Abstract: A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.

Abstract: A programmable fuse element disposed between integrated circuit elements that may be selectively joined during the manufacture or programming of an integrated circuit. The fuse element is a normally open fuse that electrically isolates the integrated circuit elements. The fuse element is comprised of a central area of conductive material insulated from the integrated circuit elements by areas of dielectric material. The integrated circuit elements and the fuse element are disposed on a thin oxide layer covering a semiconductor substrate to prevent those elements from shorting to the semiconductor substrate or to each other via the semiconductor substrate. A protective dielectric layer may be deposited over both the fuse element and the integrated circuit elements during the manufacture of the overall integrated circuit. A laser beam is used to burn through the protective layer and melts both the conductive material and the dielectric material that form the fuse element.

Abstract: The present invention relates to a technology of an electrically programmable anti-fuse device. The anti-fuse device comprises a semiconductor substrate provided with a plurality of functional elements; a field oxide layer formed on said semiconductor substrate, for electrically isolating the functional elements from each other; a predetermined pattern of a first electrode formed on said field oxide layer; a first insulating layer having two contact holes isolated from each other only on said first electrode, deposited on said field oxide layer as well as both end portions and center portion of said first electrode; a second insulating layer formed in said contact holes, to serves as an interlayer; and a second electrode formed on said second insulating layer.

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.

Abstract: An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first metal electrode, a first antifuse dielectric layer, preferably silicon nitride, disposed on the lower first electrode and an antifuse layer, preferably amorphous silicon, disposed on the first dielectric layer. An inter-layer dielectric layer is disposed on the antifuse layer and includes an antifuse via formed completely therethrough. A second antifuse dielectric layer, preferably silicon nitride, is disposed over the amorphous silicon layer in the antifuse via, and an upper second metal electrode is disposed over the second dielectric layer in the antifuse via.

Abstract: An antifuse functions as a resistive element in an SRAM cell. The antifuse layer, typically amorphous silicon, is formed to a thickness commensurate with the resistance required for proper functioning of the SRAM cell. The antifuse load SRAM cell of the present invention advantageously reduces chip area and simplifies the fabrication process. Specifically, the formation of the amorphous silicon layer is an easily controlled parameter which is therefore easily reproducible. Moreover, antifuse processing is compatible with standard CMOS processing.

Abstract: According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers. According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage.

Abstract: A device having a switch comprises a chromium layer and an adjacent semiconductor layer. The fraction of voids in the chromium layer is less than 10%, preferably less than 2%. The chromium layer in the device comprises traces of neon with a concentration of less than 0.1 at. %.Chromium layers are deposited on a substrate by means of a sputter deposition process. By using neon as the working gas at pressures of less than 1 Pa, preferably in the range from 0.2 Pa to 0.5 Pa, the sputter-deposited chromium layers are substantially free of internal stress and have a density which is approximately equal to that of bulk chromium.

Abstract: A metal-to-metal antifuse disposed between two aluminum metallization layers in a CMOS integrated circuit or similar structure includes an antifuse material layer having an aluminum-free conductive link. The aluminum-free link is formed by forming a first barrier metal layer out of TiN having a first thickness, a second barrier metal layer out of TiN having a second thickness which may be less than said first thickness, the first and second barrier metal layers separating the antifuse material layer from first and second electrodes. The antifuse is programmed by applying a voltage potential capable of programming the antifuse across the electrodes with the more positive side of the potential applied to the electrode adjacent the barrier metal layer having the least thickness.

Abstract: Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

Abstract: A field programmable gate array has a programmable interconnect structure comprising metal signal conductors and metal-to-metal PECVD amorphous silicon antifuses. The metal-to-metal PECVD amorphous silicon antifuses have an unprogrammed resistance of at least 550 megaohms and a programmed resistance of under 200 ohms.

Abstract: An improved antifuse design has been achieved by providing a structure comprising pair of alternating layers of silicon nitride and amorphous silicon sandwiched between two dual damascene connectors. Said structure provides the advantage, over the prior art, that all electrically active surfaces of the fuse structure are planar, so no potential failure spots resulting from surface unevenness can be formed. A process for manufacturing said fuse structure is also provided and involves fewer masking steps than related structures of the prior art.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: A method of forming an antifuse device. According to the preferred method of the present invention, a first metal layer comprising a first bulk conductive layer and the top capping layer is formed. Next, the capping layer is etched into a first patterned capping layer. An antifuse layer is then formed over the patterned capping layer and over the first bulk conductive layer. Next, a second metal layer comprising a bottom barrier layer and a second bulk conductive layer is formed on the antifuse layer. The second metal layer and the antifuse layer are then etched to form a metal post on the capping layer. The first bulk conductive layer is then etched in alignment with the patterned capping layer to form a first metal interconnect.

Abstract: The present invention provides for an antifuse in an integrated circuit, which has a stacked antifuse structure on a first interconnection line. The stacked structure has a first programming layer of amorphous silicon on the first interconnection line, a very thin insulating layer of silicon dioxide on the first programming layer, and a second programming layer of amorphous silicon on the very thin oxide layer. A second interconnection line on the second programming layer completes the antifuse which has a low leakage current between the first and second interconnection lines.

Abstract: An integrated circuit and method for using same is constructed on a semiconductor substrate (15) with a structure (24) in the substrate (15) having an electrical value desired to be trimable and with a conducting layer (33) on the substrate (15) insulated (30) from the structure (14) except at one location (26), which is electrically connected to a first part of the structure (24). An oxide layer (48) separates one portion of the structure (24) from a part of the conductor (33). The second oxide layer (48) has a predetermined breakdown voltage such that when a voltage, V.sub.TRIM, larger than the second predetermined breakdown voltage is applied between the conductor (33) and the structure (24), the second oxide layer (48) breaks down, shorting the first and second parts (46, 50) of the structure (24) to trim its value.

Abstract: An antifuse element for a semiconductor device, comprising a bottom electrode made from a conductive material containing a refractory metal and a top electrode made from a conductive material containing a fusible metal. The fusible metal is Al, Al alloy, Cu or Ag. The Al alloy contains at least Si, Cu, Sc, Pd, Ti, Ta or Nb. The refractory metal is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo or W. Silicides are most preferable as the refractory metal. The semiconductor device is programmed by making the top electrode negative or positive and by applying a breakdown voltage between the bottom and top electrodes so as to break down an antifuse material layer, thereby obtaining a filament. The filament is made from the fusible metal from the top electrode and the refractory metal from the bottom electrode. Thus, the filament has a low resistance, and a good EM resistance.

Abstract: In an antifuse and metal interconnect structure in an integrated circuit a substrate has an insulating layer disposed on an upper surface, a first multilayer metal interconnect layer disposed on the insulating layer, and having a first portion forming a lower antifuse electrode and a second portion forming a lower metal interconnect electrode wherein the first portion includes an upper barrier metal layer. An inter-metal dielectric layer is disposed on the lower antifuse and metal interconnect electrodes wherein the inter-metal dielectric layer includes an antifuse via formed therethrough and communicating with said lower antifuse electrode, and a metal interconnect via former therethrough communicating with the lower metal interconnect electrode, An antifuse material layer is disposed in the antifuse via, and a second multilayer metal interconnect layer is disposed on the antifuse material layer and in the upper metal interconnect electrode via and on the lower metal interconnect electrode.

Abstract: The present invention provides for a method of forming an antifuse in an integrated circuit having a first insulating layer on a semiconductor substrate.

Abstract: An improved antifuse design has been achieved by using a structure including a region of heavily doped N type silicon coated with a layer of ONO (oxide-nitride-oxide). Top contact to the ONO is made through a layer of tungsten silicide sandwiched between two layers of N type polysilicon. A cost effective method for manufacturing said antifuse structure is described.

Abstract: A device and a method for interrupting the continuity of a conductor and linking a pair of conductors are disclosed. The device is a three-terminal fuse having first and second terminals initially connected by a conductor and a third terminal separated from the conductor at a breakpoint of the conductor by an insulator. By applying a voltage across the third terminal or control terminal and the conductor, a transient conductive link is formed between the conductor and the control terminal. If sufficient current is provided through the transient link, heating of the link causes the metal of the conductor to melt and boil away, thus interrupting the continuity of the conductor.

Abstract: A programmable semiconductor memory is disclosed which can be fabricated with an MOS process of low complexity and which takes up little space. The memory comprises a MOS field-effect transistor having an antifuse region between the gate electrode and the drain region. Prior to application of a programming voltage, the antifuse region electrically isolates the gate electrode and the drain region from each other. On application of the programming voltage to the gate electrode, which is greater than the supply voltage applied between the drain and the source, the antifuse region changes to a low-impedance state.

Abstract: Antifuse elements for a semiconductor device comprise a bottom electrode, a top electrode, and an antifuse material layer. The bottom electrode is formed of a conductive material having an amorphous structure. The conductive material contains such elements as W, Ti, or a compound thereof. Since there is no grain boundary on the surface of the bottom electrode having an amorphous structure, any sharp protrusions are diminished to promote the smoothness. The antifuse material film is mounted on the surface of the bottom electrode. The bottom electrode contains such elements having an excellent EM resistance as W, Mo. These elements are also to be contained in a filament which is formed after programming.

Abstract: A process electrostatic discharge ("ESD") protection device is incorporated on a chip with the antifuses that it is designed to protect and is formed as close in time as possible to the deposition of the antifuse material layer (the layer being protected) so that ESD protection is available at all practical stages of processing. According to a first aspect of the invention, an ESD protection device is formed by exposing edges of an antifuse bottom electrode during the antifuse cell open mask/etch step. It is biased on during processing. A sharp corner of the electrode and a deep aspect ratio provide degrade antifuse performance for the protection cell (resulting in reduced breakdown voltage and increased leakage current) and, as designed, the protection cell will rupture before other cells because it has a lower breakdown voltage. Once the protection cell ruptures, it will continue to conduct and protect other antifuses from ESD damage.

Abstract: A programmable device uses anti-fuse elements. The device has a wiring layer on an insulator film on a semiconductor substrate, and it is programmed by connected condition of this wiring. The wiring is separated, such as a first wiring line and a second wiring line on the same plane, beforehand so has been disconnected at separated nodes. A thin insulator film is formed on the disconnection nodes at least, and a further floating electrode, consisting of an aluminum alloy, is formed on the thin insulator film, so that an anti-fuse element is formed straddling the first and the second wiring. When it is programmed, in order to change the disconnected anti-fuse element into a conductive state, a destructive electric potential difference is impressed between the first and the second wiring lines through the thin insulator film. As a result, the thin insulator film is broken, so that the first and the second wiring lines are connected with the floating electrode.

Abstract: Method and apparatus for interconnecting integrated circuits (ICs) are described. The invented lattice preferably is formed in a plural-layer structure whereby each required interconnect signal has one or more dedicated layers of a planar, thin-film conductor that is coextensive with the substrate. Thousands of such horizontal layers are vertically stacked in the structure, each being shielded by voltage or ground planes and each being insulated by layers of insulative dielectric material. A regular array of vertical pillars is provided in the substrate, each pillar effectively providing an inner conductor either electrically connected with a conductive layer or electrically insulated therefrom by an insulative region. The columns extend from the top of the substrate on which the ICs are mounted through to the bottom surface of the bottom layer.

Abstract: According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers, According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage.

Abstract: An antifuse comprises first and second electrodes separated by an antifuse material having a thickness selected to impart a desired target programming voltage to the antifuse. The antifuse material comprises a solid material stable at temperatures below about 600.degree. C., having a defect density less than about 100 defects/cm.sup.2, a breakdown field less than about 10 megavolts/cm, a dielectric constant lower than about 4.0, a resistivity of greater than about 10.sup.4 ohm-cm. The antifuse material may comprise organic materials such as polyimides compatible with high-temperature processes including cured polyamic acids, pre-imidazed polymers, photo-sensitive polyimides, and other polimides such as pyralin, probimide, PIQ, etc. The antifuse materials of the present invention also include fluorinated polymers having very low dielectric constants, such as teflon, paralines, polyphenylquinoxaline, benzocyclobutene polymers, and perfluoropolymers.

Abstract: A novel antifuse structure includes a novel antifuse material layer comprises a first dielectric layer, a first polysilicon layer (which may optionally be lightly doped) disposed over the first dielectric layer, and a second dielectric layer disposed over the first polysilicon layer. The dielectric layers may be formed of silicon nitride, silicon dioxide, silicon oxynitride and combinations of the foregoing. Additional layers may also be included to form D/P/D/P/D, D/P/D/a-Si/D sandwiches, and the like. The polysilicon layer provides the ability to control the breakdown voltage of the antifuse through control of the doping level while maintaining a relatively large thickness of the antifuse material layer resulting in low capacitance for the antifuse. The antifuse material layer is compatible with high temperature processes (500.degree. C.-950.degree. C.) and may be carried out in the range of 400.degree. C.-950.degree. C. making it compatible with a wide range of processes.

Abstract: An antifuse according to the present invention includes a lower electrode formed from a first metal interconnect layer in an integrated circuit or the like. The lower electrode is disposed on an insulating surface. An inter-metal dielectric including an antifuse aperture disposed there lies over the inter-metal dielectric layer. The antifuse aperture extends through the inter-metal dielectric layer and also extends completely through the lower electrode. An antifuse material is disposed in the antifuse aperture. An upper electrode formed from a first metal interconnect layer is disposed over the antifuse material.

Abstract: A method for fabricating a metal-to-metal antifuse comprises the steps of (1) forming and defining a first metal interconnect layer; (2) forming an interlayer dielectric layer; (3) forming an antifuse via in the interlayer dielectric layer to expose the first metal interconnect layer; (4) depositing a via metal layer into a portion of the volume defining the antifuse via; (5) forming a planarizing layer of an insulating material in the antifuse via sufficient to fill a remaining portion of the volume defining the antifuse via; (6) etching the planarizing layer to expose an upper surface of the via metal layer and an upper surface of the interlayer dielectric layer so as to form a substantially planar surface comprising the upper surface of the interlayer dielectric layer, the planarizing layer, and the upper surface of the via metal layer; (7) forming an antifuse material layer over the substantially planar surface; (8) forming a metal capping layer over the antifuse material layer; and (9) defining the antif

Abstract: A system for substrate scale integration by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor substrate so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.

Abstract: An additional column (or row) track is provided in an antifuse based interconnect array containing circuit structures identical to the circuit structures in the remaining columns of the array, except that antifuse vias are filled with contact or via plugs. These plug antifuse substitutes are addressable in the same manner and by the same circuitry as the antifuses on the integrated circuit. The programmed antifuse is addressed, a test voltage is placed on the V.sub.pp input pin on the integrated circuit, and the current drawn by the antifuse is measured. The plug antifuse substitute is addressed, the test voltage is placed on the V.sub.pp input pin on the integrated circuit, and the current drawn by the plug antifuse substitute is measured.

Abstract: A method and resulting antifuse structure in an integrated circuit include a first metal interconnection layer on a first insulating layer over the substrate of the integrated circuit, a second insulating layer over the first metal interconnection layer. The second insulating layer has a via therein and a programming layer is located in the via. Such programming layer includes a first region on the first metal interconnection layer which is removed from sides of the second insulating layer in the via, and a second region on the sides of the second insulating layer via. The first region has substantially a first thickness, the second region has substantially a second thickness which is greater than the first thickness. Upon programming the antifuse structure, a conducting link forms in the first region of the programming layer.

Abstract: A method and system for programming vROM programmable memories using antifuses fabricated from undoped amorphous silicon as a high resistance link or layer between two metal layers. Whenever a programming voltage higher than a normal operating voltage is applied across the link between the two metal layers, the resistance of the link is reduced by transforming the insulating amorphous silicon into conducting polysilicon. This causes a closed or conductive link to be formed between the two metal layers. In the programming of the vROM, current is actively pumped to the link; and a current measurement or check is made prior to the application of the programming voltage to determine whether the link already has been programmed. Immediately following the application of the programming voltage, the current through the link again is checked to determine proper programming of the link.

Abstract: An antifuse element provided on a semiconductor device comprises a bottom electrode, an antifuse material layer, and a top electrode. At least the uppermost portion of the bottom electrode is made of metallic silicide in which the metal composition ratio is set to greater than the stoichiometry composition ratio. The metallic silicide is obtained by silicidizing the metal at a temperature of 400.degree.-700.degree. C. The crystal orientation of the thus formed metallic silicide is at random, and therefore the surface of the bottom electrode made of metallic silicide becomes flatter and smoother. The metal component of the metallic silicide is effectively used in the forming of the filament when a breakdown voltage is applied to the selected electrodes for an electrical connection.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first metal electrode, a first antifuse dielectric layer, preferably silicon nitride, disposed on the lower first electrode and an antifuse layer, preferably amorphous silicon, disposed on the first dielectric layer. An inter-layer dielectric layer is disposed on the antifuse layer and includes an antifuse via formed completely therethrough. A second antifuse dielectric layer, preferably silicon nitride, is disposed over the amorphous silicon layer in the antifuse via, and an upper second metal electrode is disposed over the second dielectric layer in the antifuse via.

Abstract: An antifuse comprises a lower electrode and an upper electrode separated by an interlayer dielectric. An antifuse cell opening is disposed in the interlayer dielectric. The antifuse cell opening comprises at least two steps, wherein a first portion thereof has a first area and a second portion thereof disposed above the first portion has a second area larger than said first area. Additional portions may be provided above the second portion having successively larger areas if the thickness of the interlayer dielectric warrants their inclusion.

Abstract: The antifuse structure of the present invention includes a bottom planarized electrode, an ILD disposed over the bottom electrode, an antifuse cell opening in and through the ILD exposing the bottom electrode, a first barrier metal layer disposed by means of collimated sputter deposition in the antifuse cell opening to form a layer of uniform thickness existing only within the antifuse cell opening in order to protect the antifuse material layer from diffusion from the bottom electrode and to form an effective bottom electrode of reduced area, hence reducing the capacitance of the device, an antifuse material layer disposed in the antifuse cell opening and over the first barrier metal layer, a second barrier metal layer disposed over the antifuse material layer and optionally formed by collimated sputter deposition, and a top electrode disposed over the second barrier metal layer.

Abstract: The antifuse structure of the present invention includes a bottom planarized electrode, an ILD disposed over the bottom electrode, an antifuse cell opening in and through the ILD exposing the bottom electrode, a first barrier metal layer disposed in the antifuse cell opening to protect the antifuse material layer from diffusion from the bottom electrode and to form an effective bottom electrode of reduced area, hence reducing the capacitance of the device, an antifuse material layer disposed in the antifuse cell opening and over the first barrier metal layer, a second barrier metal layer disposed over the antifuse material layer, and a top electrode disposed over the second barrier metal layer.

Abstract: An additional column (or row) track is provided in an antifuse based interconnect array containing circuit structures identical to the circuit structures in the remaining columns of the array, except that antifuse vias are filled with contact or via plugs. These plug antifuse substitutes are addressable in the same manner and by the same circuitry as the antifuses on the integrated circuit. The programmed antifuse is addressed, a test voltage is placed on the V.sub.pp input pin on the integrated circuit, and the current drawn by the antifuse is measured. The plug antifuse substitute is addressed, the test voltage is placed on the V.sub.pp input pin on the integrated circuit, and the current drawn by the plug antifuse substitute is measured.

Abstract: According to the present invention, planar layers of Nitride (first nitride layer), a-Si (first a-Si layer), Nitride (second Nitride layer) and a-Si (second a-Si layer) are laid down over a first metallization layer. A dielectric layer is then laid down on top of the second a-Si layer. A via is opened in the dielectric layer with an etch gas which attacks a small portion of the second a-Si layer which, in effect, serves as a sacrificial etch-stop layer. A titanium layer is laid down over the via and allowed to thermally react with the remainder of the second a-Si layer to form an electrically conductive titanium silicide region in the area of the via the thickness of the second a-Si layer. The reaction is self-limiting and stops at the second Nitride layer. Subsequently a second metallization layer is disposed over the via.

Abstract: A method of forming an antifuse in an integrated circuit having an insulating layer on a semiconductor substrate is provided. The method comprises forming a first metal interconnection layer on the insulating layer; forming a first barrier metal layer on the first metal interconnection layer; forming an amorphous silicon layer on the first barrier metal layer; forming another barrier metal layer atop the amorphous silicon layer; and forming a second metal interconnection layer on the second barrier metal layer. In at least one of the barrier metal forming steps, the barrier metal is formed by sputtering a barrier metal target which includes a semiconductor dopant, such as dopant.

Abstract: The invention features a circuit wherein a serially connected transistor and anti-fuse element are biased for current to flow in a first direction or the current flows in the first direction during a programming operation and biased for a current to flow in a second direction or current is flowing in the second direction during a normal circuit operation, each as a read operation, wherein the first and second directions are opposite of one another. Thus the invention facilitates the use of a low programming potential while minimizing leakage current.