Abstract: An antifuse element suitable for use in FPGA. When a device is miniaturized to reduce the write voltage in an antifuse element and as the film thickness of the antifuse dielectric film is being reduced, the dielectric breakdown voltage is greatly variable due to the irregularity of the underlying metal. If the dielectric film is formed by a metal oxide having a relatively high specific permitivity without changing its parasitic capacity as compared to the prior art, the film thickness of the dielectric film can be increased in comparison with oxide and nitride films formed according to the prior art. The irregularity of the underlying metal can be reduced by coating it with a metal nitride or TiB film or TiC film. To equalize the dielectric breakdown voltage, another insulation film having a film thickness such that the direct tunnel conduction is dominant is formed below the metal oxide.

Abstract: A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures. A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.

Abstract: A method and structure for an improved antifuse in an integrated circuit having a sacrificial layer under a programming layer which forces a conductive link upon programming to be formed away from corner regions of the via structures. The method includes the unique step of forming an improved aperture or via with sides through an inter dielectric layer where the antifuse is to be located. The improved aperture or via exposes a portion of a metal interconnection line through a portion of sacrificial layer located away from the inter dielectric layer sides. Such improved method of forming the antifuse also provides a superior antifuse structure.

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Abstract: A process electrostatic discharge ("ESD") protection device is incorporated on a chip with the antifuses that it is designed to protect and is formed as close in time as possible to the deposition of the antifuse material layer (the layer being protected) so that ESD protection is available at all practical stages of processing. According to a first aspect of the invention, an ESD protection device is formed by exposing edges of an antifuse bottom electrode during the antifuse cell open mask/etch step, It is biased on during processing. A sharp corner of the electrode and a deep aspect ratio provide degrade antifuse performance for the protection cell (resulting in reduced breakdown voltage and increased leakage current) and, as designed, the protection cell will rupture before other cells because it has a lower breakdown voltage. Once the protection cell ruptures, it will continue to conduct and protect other antifuses from ESD damage.

Abstract: An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug including a conductive barrier material such as TiN or TiW to contact the anti-fuse material and overlie the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separaged from the anti-fuse layer by at least one-half the depth of the via hole. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.

Abstract: An antifuse structure particularly suitable for field programmable gate arrays is presented. In most present day processes the antifuse structure is formed with a refractory metal layer, amorphous silicon layer and refractory metal layer sandwiched between two metal interconnection lines. Unprogrammed resistances of very high values, programmed resistances of very low values, short programming times and desirable programming voltages are among the advantages realized.

Abstract: A programmable interconnect is provided that includes a first plurality of lines, a second plurality of lines, and means for connecting one of the first plurality of lines to one of the second plurality of lines, wherein the means for connecting includes an antifuse and a diode. The diode in this configuration performs the equivalent logical function as an AND gate. Programing the antifuse determines the diode-AND gate function performed. In this manner, a programmable interconnect array in accordance with the present invention, formed using standard fabrication processes, provides an area-efficient implementation of a wide AND functionality.

Abstract: An antifuse for programmable integrated circuit devices is formed above a refractory metal on a thin native oxide layer and comprises an amorphous compound resulting from an PECVD deposition using a combination of silane gas and nitrogen. After formation of the amorphous antifuse layer, the layer is implanted with an atomic species such as argon. The thin oxide layer is formed on the surface of a refractory metal, therefore the process of forming the oxide is slow, the oxide is of even thickness, and the thickness can be controlled precisely. In a preferred embodiment, a second thin oxide layer is formed above the doped amorphous layer. The oxide layers significantly reduce the leakage current of an unprogrammed antifuse. Because of these thin oxide layers and the implantation step, the amorphous layer may be as thin as 200 .ANG..

Abstract: The present invention relates to a high performance, high reliability antifuse using conductive electrodes. The problem of switch-off of the programmed antifuses is solved by reducing the thermal conductivity of the conductive electrodes. This is achieved by using lower thermal conductivity conductors for the electrodes or by using thinner electrodes to increase thermal resistance. According to a first aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing conductive electrode materials having a relatively lower thermal conductivity than prior art electrode materials. According to a second aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing relatively thin electrodes, thus increasing their thermal resistance.

Abstract: An antifuse is provided which includes a first conductive layer, an antifuse layer formed on the first conductive layer, and a second conductive layer formed on the antifuse layer. A portion of the antifuse layer forms a substantially orthogonal angle with the first conductive layer and the second conductive layer. This "corner" formation of the antifuse enhances the electric field at this location during programming, thereby providing a predictable location for the filament, i.e. the conductive path between the first and second conductive layers. This antifuse provides other advantages including: a relatively low programming voltage, good step coverage for the antifuse layer and the upper conductive layer, a low, stable resistance value, and minimal shearing effects on the filament.

Abstract: A method and system for programming vROM programmable memories using antifuses fabricated from undoped amorphous silicon as a high resistance link or layer between two metal layers. Whenever a programming voltage higher than a normal operating voltage is applied across the link between the two metal layers, the resistance of the link is reduced by transforming the insulating amorphous silicon into conducting polysilicon. This causes a closed or conductive link to be formed between the two metal layers. In the programming of the vROM, current is actively pumped to the link; and a current measurement or check is made prior to the application of the programming voltage to determine whether the link already has been programmed. Immediately following the application of the programming voltage, the current through the link again is checked to determine proper programming of the link.

Abstract: An additional column (or row) track is provided in an antifuse based interconnect array containing circuit structures identical to the circuit structures in the remaining columns of the array, except that antifuse vias are filled with contact or via plugs. These plug antifuse substitutes are addressable in the same manner and by the same circuitry as the antifuses on the integrated circuit. The programmed antifuse is addressed, a test voltage is placed on the V.sub.pp input pin on the integrated circuit, and the current drawn by the antifuse is measured. The plug antifuse substitute is addressed, the test voltage is placed on the V.sub.pp input pin on the integrated circuit, and the current drawn by the plug antifuse substitute is measured.

Abstract: A method of forming a metal-to-metal antifuse. An antifuse stack 32 is formed comprising a first metal layer 16, an antifuse dielectric layer, and an etchstop layer. The etchstop layer may, for example, comprise an oxide layer 24 and an amorphous silicon layer 28. An antifuse via 44 is etched through an interlevel dielectric layer 36 to the antifuse stack 32. Next, a portion of the etchstop layer at the bottom of via 44 is removed. Finally, a second layer of metal 48 is deposited to fill antifuse via 44 and etched to form the desired interconnections.

Abstract: A "read-disturb" resistant metal-to-metal antifuse includes a lower electrode comprising a first metal layer in a microcircuit structure. An inter-metal dielectric is disposed over the lower electrode and includes an antifuse aperture disposed therein. A first layer of antifuse material is disposed over exposed surface of the lower electrode in the antifuse aperture. A highly conductive layer is disposed over the first region of antifuse material and a second layer of antifuse material is disposed over the highly conductive layer. An upper electrode comprises a second metal layer disposed over the second layer of antifuse material. The first and second layers of antifuse material may comprise single-layer or multi-layer dielectric materials, amorphous silicon, or combinations of these materials.

Abstract: A method for forming an amorphous silicon programable element which requires less than about one square micron of area. The method includes the steps of forming a bottom conductor, depositing an interlayer dielectric above the bottom conductor, forming a via in the interlayer dielectric, depositing an anti-fuse layer above the bottom conductor within the via, and chemical vapor depositing a conductive plug above the anti-fuse layer and within the via. The method may additionally include the step of chemical vapor depositing a top conductor above the conductive plug.

Abstract: A programmable semiconductor contact structure and method are provided. A semiconductor substrate has a first patterned conductive layer for forming an interconnect. A first insulating layer overlies the first patterned conductive layer. An opening is formed through the insulating layer to the first patterned conductive layer to form the contact via. A buffer layer overlies portions of the first insulating layer and covers the opening. A second conductive layer overlies the buffer layer. A third conductive layer then overlies the integrated circuit. The buffer layer is a material, such as amorphous silicon, which functions as an anti-fuse and can be programmed by application of a relatively high programming voltage.

Abstract: A device (10) for controlling current through a circuit has an antifuse material (18) separating a first conductor (12) and a second conductor (20). An insulating element (14) and another insulating element (16) further separate the first conductor (12) from the second conductor (20). The antifuse material (18) includes a dopant which raises the band gap and seals off paths in grain boundaries of the antifuse material (18) in order to limit leakage current from flowing between the first conductor (12) and the second conductor (20). When an interconnection is desired, a high voltage pulse is applied across the first conductor (12) and the second conductor (20) to initially break down the antifuse material (18). The breakdown of the antifuse material (18) causes a filament (22) to form between the first conductor (12) and the second conductor (20). The filament (22) creates a conduction path connecting the first conductor (12) and the second conductor (20) electrically together.

Abstract: A programmable storage element for redundancy-programing includes a programmable antifuse circuit, which includes a plurality of first resistors and a switching circuit for coupling the first resistors in series in response to a plurality of first control signals and for coupling the first resistors in parallel in response to a plurality of second control signals to permit programing of the first resistors, and a sensing circuit for determining whether or not the first resistors have been programmed. The state of the first resistors is determined by comparing a first voltage drop across the first resistors with a second voltage drop across a second resistor. Each of the first resistors is an unsilicided polysilicon conductor which has an irreversible resistance decrease when a predetermined threshold current is applied for a minimum period of time.

Abstract: An integrated circuit has a plurality of programmable antifuses. Each antifuse can be programmed to connect metals runners on one level with either or both of a pair of runners on a second level.

Abstract: Electrically-programmable low-impedance antifuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The antifuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or metal having a barrier metal underneath. At least one of the two electrodes of each antifuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer.

Abstract: An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first electrode, a first dielectric layer disposed over the lower first electrode, a layer of amorphous silicon disposed above the first dielectric layer, a second dielectric layer disposed above the amorphous silicon layer, and an upper second electrode disposed above the second dielectric layer.

Abstract: A monitor circuit provided in a chip in which a semiconductor integrated circuit is formed. Connection mechanisms and disconnection mechanisms are connected in series in wirings connected to the monitor circuit. Before using the semiconductor integrated circuit, in the state that the connection mechanisms are opened, the monitor circuit is tested without conducting the monitor circuit to the semiconductor integrated circuit. In the case of using the semiconductor integrated circuit, the connection mechanisms are written to close them, so that the monitor circuit is connected to the semiconductor circuit main body and is thus driven. Further, after using the semiconductor integrated circuit, the monitor circuit is separated from the semiconductor integrated circuit by writing the disconnection mechanisms, to be investigated for the characteristic.

Abstract: A method for forming isolation structures in an integrated circuit, and the structures so formed, are disclosed. After definition of active regions of the surface is accomplished by provision of masking layers, recesses are etched into the exposed locations, to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material, are disposed along the sidewalls of the recesses, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon then forms a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface.

Abstract: An antifuse according to the present invention includes a lower electrode formed from a first metal interconnect layer in an integrated circuit or the like. The lower electrode is disposed on an insulating surface. An inter-metal dielectric including an antifuse aperture disposed there lies over the inter-metal dielectric layer. The antifuse aperture extends through the inter-metal dielectric layer and also extends completely through the lower electrode. An antifuse material is disposed in the antifuse aperture. An upper electrode formed from a first metal interconnect layer is disposed over the antifuse material.

Abstract: An antifuse structure particularly suitable for field programmable gate arrays is presented. In most present day processes the antifuse structure is formed with a refractory metal layer, amorphous silicon layer and refractory metal layer sandwiched between two metal interconnection lines. Unprogrammed resistances of very high values, programmed resistances of very low values, short programming times and desirable programming voltages are among the advantages realized.

Abstract: According to the present invention, planar layers of Nitride (first nitride layer), a-Si (first a-Si layer), Nitride (second Nitride layer) and a-Si (second a-Si layer) are laid down over a first metallization layer. A dielectric layer is then laid down on top of the second a-Si layer. A via is opened in the dielectric layer with an etch gas which attacks a small portion of the second a-Si layer which, in effect, serves as a sacrificial etch-stop layer. A titanium layer is laid down over the via and allowed to thermally react with the remainder of the second a-Si layer to form an electrically conductive titanium silicide region in the area of the via the thickness of the second a-Si layer. The reaction is self-limiting and stops at the second Nitride layer. Subsequently a second metallization layer is disposed over the via.

Abstract: An antifuse (42) is formed by forming a layer of titanium tungsten (34) overlying a portion of a first metal layer (28). The titanium tungsten layer (34) is oxidized to form a film of oxide (36) on its surface. Insulating regions (30) are formed adjacent the titanium tungsten layer (34) and overlying the first metal layer (28). A second metal layer (40) is formed overlying the titanium tungsten layer (34). Applying a break down voltage across the first and second metal layers (28), (40) will break down the oxide film (36), thereby causing a connection between the first and second metal layers (28), (40).

Abstract: A metal-to-metal antifuse includes a lower electrode formed from a first metal layer in a semiconductor or other microcircuit structure. A barrier layer is disposed over the first metal layer. A first heavily-doped amorphous silicon layer is disposed over the barrier layer. A thin dielectric antifuse material is disposed over the first amorphous silicon layer. This dielectric can be nearly any dielectric such as nitride or oxide or a combination of these materials such as ONO and should have a breakdown voltage suitable for programming inside the integrated circuit. A second heavily-doped amorphous silicon layer is disposed over the dielectric layer. An upper electrode, comprising a second metal layer including an underlying barrier layer, is disposed over the second amorphous silicon layer. The first and second metal layers may comprise metal interconnect layers in the circuit structure.

Abstract: A method and resulting structure to provide an antifuse wherein the resistance of the programmed fuse and the line resistance and capacitance are materially reduced relative to the prior art and the procedures involved and the resulting structure of the fuse permit the use of materials not available in prior art antifuses. This is accomplished by providing the fuse on vertical sidewalls of the fuse electrode or beneath a sidewall oxide on the fuse electrode. Since the thickness of the electrode can be controlled to an extent not currently achievable by lithographic means, a much smaller area antifuse is provided using sidewall antifuse as opposed to a planar antifuse.

Abstract: A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures.A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.

Abstract: A programmable storage element for redundancy-programming includes a programmable antifuse circuit, which includes a plurality of first resistors and a switching circuit for coupling the first resistors in series in response to a plurality of first control signals and for coupling the first resistors in parallel in response to a plurality of second control signals to permit programming of the first resistors, and a sensing circuit for determining whether or not the first resistors have been programmed. The state of the first resistors is determined by comparing a first voltage drop across the first resistors with a second voltage drop across a second resistor. Each of the first resistors is an unsilicided polysilicon conductor which has an irreversible resistance decrease when a predetermined threshold current is applied for a minimum period of time.

Abstract: An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuses are formed over the intermetal dielectric. The antifuses are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation.

Abstract: An antifuse memory cell having a P.sup.+ polysilicon doping in a region directly under an intrinsic silicon programming layer. The P.sup.+ polysilicon region is surrounded by an N.sup.- polysilicon doped region, and the two regions are sandwiched between layers of silicon dioxide insulation. The interface between the two regions is a P-N junction, in fact, a diode. The diode does not suffer from a diffusion current that increases with increasing levels of N.sup.- doping, therefore the N.sup.- polysilicon can be heavily doped to yield a very conductive bit line interconnect for a memory matrix. The interconnect line widths can be very narrow, and further microminiaturization is aided thereby. The top metalization is aluminum and serves as a word line interconnect in the memory matrix.

Abstract: The invention features a circuit wherein a serially connected transistor and anti-fuse element are biased for current to flow in a first direction or the current flows in the first direction during a programming operation and biased for a current to flow in a second direction or current is flowing in the second direction during a normal circuit operation, such as a read operation, wherein the first and second directions are opposite of one another. Thus the invention facilitates the use of a low programming potential while minimizing leakage current.

Abstract: A method of forming a metal-to-metal antifuse. An antifuse stack 32 is formed comprising a first metal layer 16, an antifuse dielectric layer, and an etchstop layer. The etchstop layer may, for example, comprise an oxide layer 24 and an amorphous silicon layer 28. An antifuse via 44 is etched through an interlevel dielectric layer 36 to the antifuse stack 32. Next, a portion of the etchstop layer at the bottom of via 44 is removed. Finally, a second layer of metal 48 is deposited to fill antifuse via 44 and etched to form the desired interconnections.

Abstract: A method is provided for writing into a semiconductor memory which includes a MOS transistor formed on a semiconductor substrate and an anti-fuse formed of an insulating film and an upper electrode on a drain of the MOS transistor. The method includes the steps of applying a first voltage between the upper electrode of the anti-fuse and a source of the MOS transistor to cause dielectric breakdown of the insulating film of the anti-fuse, with the MOS transistor turned on; and applying a second voltage between the upper electrode of the anti-fuse and the semiconductor substrate so that a larger amount of current flows than the amount of current required for breaking down the insulating film of the anti-fuse.

Abstract: A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consists essentially of a single element semiconductor selected from the group of Si, Ge, C, and .alpha.-Sn, having a crystalline grain size which is smaller than polycrystalline. Dopant atoms in the semiconductor are limited to be less than 10.sup.17 atoms/CM.sup.3 ; and, such a doping range includes zero doping. All dopant atoms are interstitial in the semiconductor crystals and not substitutional.

Abstract: The present invention provides a programmable structure for programmable integrated circuits, such as programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digitlines as well as on the wordlines thereby providing two, one time programmable nodes at each digit/word/digit' intersection. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines, also having one-sided ozone spacers, and further overlying parallel rows' of digitlines' in a programmable read only memory. With a lower level of digitlines passing under a middle level of wordlines and an upper level of digitlines' passing over the middle level of wordlines, a row/column/digit' matrix is formed thereby providing a programmable row/column/row' matrix in a memory array.

Abstract: An antifuse particularly suitable for submicron geometries is presented. The antifuse is formed between a silicon layer, which could be a doped region of the semiconductor substrate, an epitaxial layer or a polysilicon layer, and an upper metal interconnection layer. In contact holes in a silicon dioxide layer insulating the silicon and metal interconnection layers from each other, the antifuses have a thick refractory metal layer having a top surface approximately at the same level as the top surface of the insulating layer. Depending upon the process used to deposit the refractory metal layer, a thin adhesion layer may be located immediately below the refractory metal layer. Between the underlying silicon layer and upper interconnection layer, a thin semiconductor material layer of amorphous silicon may be located either below the refractory metal layer or above it.

Abstract: An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuse are formed over the intermetal dielectric. The antifuse are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation.

Abstract: An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first electrode, a first dielectric layer disposed over the lower first electrode, a layer of amorphous silicon disposed above the first dielectric layer, a second dielectric layer disposed above the amorphous silicon layer, and an upper second electrode disposed above the second dielectric layer.