Abstract: A semiconductor device provided with a wide and shallow first groove and a second groove in the first groove area, having a narrower width than that of the first groove around a predetermined area in a one-conductive area provided in the upper region of a semiconductor substrate as a mesa groove, wherein at least the second groove is covered with an electrical insulator. The upper surface of the electrical insulator is located approximately as high as or lower than the upper surface of the electrical insulating film. Thus, especially in a mesa semiconductor device with a high-voltage resistance, an insulating protective layer having a sufficient thickness can be formed stably over the entire region of a mesa groove. As a result, the variation in high-voltage resistance characteristics can be decreased and the processing yield affected by breakage or cracking in the mesa groove region during subsequent processes caused by the formation of the mesa groove can be improved greatly.

Abstract: The present invention is directed to an improved deep trench structure, for use in junction devices, which addresses junction breakdown voltage instabilities of the prior art. The primary, or metallurgical, junction where avalanche breakdown occurs is moved away from the surface dielectric into the bulk silicon by adding a lightly doped layer adjacent to the deep trench. A preferred embodiment suitable for isolated structures places the doped layer adjacent to the sidewalls of the deep trench. A second preferred embodiment, suitable for non-isolated structures, places the doped layer adjacent to both the floor and the sidewalls of the trench.

Abstract: A trench isolation in a semiconductor substrate is provided. The trench isolation includes a recessed region in the semiconductor substrate. The trench isolation also has a first insulator layer lining the recessed region. The first insulator aligns with the semiconductor substrate at edge of the recessed region. The trench isolation further includes a second insulator layer filling within the recessed region over the first insulator. As a preferred embodiment, the recessed region can have well rounded corners at bottom and abutting top surface of the semiconductor substrate. The first insulator has inwardly increased height after the planarization process. The second insulator layer aligns with the first insulator at inner edge of the first insulator. The second insulator layer can also have a top plain region.

Abstract: A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed at predetermined locations of the semiconductor substrate and oxide films using organic silicon source as material are buried in the grooves as buried oxide films. The present invention is characterized in that the buried oxide films are annealed at a predetermined temperature within the range of 1100 to 1350.degree. C. before or after planarization of the semiconductor substrate such that ring structures of more than 5-fold ring and ring structures of less than 4-fold ring are formed at predetermined rates in the buried oxide films. The above annealing allows stress of the oxide film buried in the grooves to be relaxed. Hence, the generation of dislocation is suppressed.

Abstract: An integrated circuit arrangement having at least two components has in a substrate, an insulation structure (4', 5) between the components which covers at least one side of a trench (3) and is thicker at the bottom of the trench than at the neck of the trench. The components are in this case arranged in different planes on the substrate surface and on the trench bottom. The insulation structure effects vertical insulation between the components.

Abstract: A shallow trench isolated FET LDD structure that has a low probability of short circuiting at the silicon to trench interface or between the source or drain and the gate (because of a titanium silicide bridge) is described. It is based on an isolation trench having a top portion with vertical sides and a lower portion with sloping sides. With the filled trench in place, along with a polysilicon gate and gate oxide, the thinner, lightly doped, N type layer is formed using ion implantation. Spacers are then formed on the gate but, prior to the second ion implant step, a few hundred Angstroms of silicon is selectively removed from the surface. This causes the trench filler material to extend above the wafer surface and the spacers to extend above the gate. A deeper, more strongly N-type, layer is then formed in the usual way, followed by the standard SALICIDE process for making contact to source, gate, and drain.

Abstract: A collector structure in a bipolar transistor on a semiconductor substrate is surrounded by trench isolations. A well region has a first impurity concentration and extends in an upper portion of the semiconductor substrate surrounded by the trench isolations. The well region is a first conductivity type and a burying layer horizontally extends under the well region. The burying layer is positioned shallower than the bottom of the trench isolations. Collector plug electrodes extend in a vertical direction and along inside walls of the trench isolations. The collector plug electrodes are the first conductivity type and have a second impurity concentration higher than the first impurity concentration. The collector plug electrodes have a bottom level which is about the same as the bottom of the trench isolations. A collector diffusion layer extends in a vertical direction and along inside vertical walls of the collector plug electrodes.

Abstract: Ordinary anisotropic etching is performed up to a depth (d1) while anisotropic etching is performed to form an inward taper from the depth (d1) by changing etching conditions such as components in a vapor phase and the temperature of a silicon substrate (1), thereby forming a groove (20). Thereafter silicon is epitaxially grown in the groove (20), thereby forming an epitaxial silicon layer (4). An NMOS transistor is formed on an upper layer part of the epitaxial silicon layer (4). At this time, the taper of the groove (20) is located under a part of an n.sup.+ layer (8) forming the NMOS transistor. Thus, a method of fabricating a semiconductor device capable of performing element isolation with neither halation nor formation of bird's beak in fabrication while minimizing a leakage current flowing across elements is obtained.

Abstract: Disclosed is an integrated circuit having at least two active components, such as transistors, having the following features:a highly conductive substrate is provided which is connected to one pole of a voltage supply source,a semiconductor layer, which is electrically isolated from the substrate and divided into individual sections by lateral isolation regions, is disposed on a main surface of the substrate,placed in each section is at least one active component, e.g., a transistor of any type performance, andlateral deep diffusion regions which are accommodated in the semiconductor layer create a conductive connection between the highly conductive substrate and the corresponding regions of the active components.

Abstract: A method for making a schottky diode structure (10) simultaneously with a polysilicon contact structure (31,33) to a transistor is provided. In a single process step, a polysilicon layer is patterned to expose a single crystal semiconductor region (22a) over one portion of a substrate, while leaving portions the polysilicon layer (31, 33, 29) intact over other portions of the substrate (22b). Multi-layer metal electrodes are deposited and patterned to form a rectifying schottky contact to the exposed single crystal region (22a), and to form an ohmic contact to the exposed polysilicon (31, 33, 29).

Abstract: An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are blocked out of an active region, and only the field region surrounding said active area is implanted, said implanting such that a predetermined layout area of a semiconductor device does not need to be increased to compensate for a BV.sub.bso problem.

Abstract: An etch mask having a narrow spacer layer self-aligned and adjacent to a first portion of an inorganic first layered segment. An inorganic second layered segment comprises a portion of the etch mask and encompasses a perimeter of the first layered segment and is distanced from the first layered segment by a distance equal to a thickness of the narrow spacer layer. A first portion of the second layered segment is adjacent to the narrow spacer layer. A void exists between second portions of the first and the second layered segments. The area of the substrate exposed by the etch mask of the invention, when etched, forms a trench whose width is limited only by the width of the void which is equal to the width of the narrow spacer layer. The narrowness of the narrow isolated trench formed using the etch mask of the invention maximizes die space.

Abstract: In a Hall element, a semiconductor layer is surrounded by a first trench filled with an insulator. A first current supply portion of an n+-type semiconductor is disposed adjacent the semiconductor layer and the first trench. Second current supply portions are also disposed adjacent the semiconductor layer and the first trench and symmetrical with respect to the first current supply portion. Sensor portions of an n+-type semiconductor are disposed adjacent the semiconductor layer and the first trench at about the center between the first and second current supply portions, respectively. A magnetic flux perpendicular to the upper surface of the semiconductor layer can be detected by the foregoing arrangement.

Abstract: A semiconductor device includes an n-type low-resistance region (2) formed on a p-type monocrystalline semiconductor substrate (1), an n-type epitaxial layer (3) formed on the n-type low-resistance region (2), an insulating film (5) formed on the n-type epitaxial layer (3) and having a first opening selectively formed therein, and an n-type polysilicon film (8) having an overhung portion extending from the entire peripheral portion of the opening to the inside of the opening. An n-type polysilicon film (9) is formed downward from the bottom surface of the overhung portion, and a p-type monocrystalline silicon film (6) serving as a base is formed on the surface of the n-type epitaxial layer in the first opening. The base (6) is in contact with the n-type polysilicon films (8, 9), and the n-type emitter (10) is formed immediately below the n-type emitter polysilicon films (8, 9) to have an annular shape.

Abstract: A process for manufacturing isolated semi conductor components in a semi conductor wafer of the type used in bipolar technology. In this process, polycrystalline silicon is deposited in a recess in a silicon substrate whose walls are insulated by a silicon nitride layer except for an opening formed in this nitride layer at the bottom of said recess. Then, the polycrystalline silicon is re-epitaxied so as to become monocrystalline silicon by thermal heating from the "nucleus" formed by the underlying silicon in said opening.

Abstract: In a semiconductor integrated circuit having a block of static memory cells using CMOS transistors and peripheral components using bipolar transistors, metal interconnections in a layer over the CMOS transistors on the substrate are simplified by using buried layers in the substrate as supply and ground lines for the CMOS transistors. This is accomplished by making buried contacts of a metal such as tungsten in each memory cell to make ohmic connection of the diffused layer of n-MOS transistors and the diffused layer of p-MOS transistors respectively to underlying buried layers of opposite conductivities and applying supply voltage or ground potential to each buried layer from the substrate surface by using additional buried contacts which are made at convenient locations outside the memory block. In the case of n-MOS memory cells using resistors or TFTs as load elements, ground potential is applied to the n-MOS transistors by the same method.

Abstract: A power transistor has a plurality of small emitter-base complexes arranged in an array. These complexes are electrically insulated from the surrounding semiconductor material by separating regions such that for the current supply to the collectors, a joint subcollector layer and thereupon a collector metallization exist outside of the emitter-base complexes and reaching up to the separating regions. The individual emitter-base complexes are electrically connected with each other via strip-shaped base supply lines and strip-shaped emitter supply lines, and also with a base contact surface and an emitter contact surface.

Abstract: A P-type substrate is immersed in a solution of potassium hydroxide (KOH) which etches exposed portions of the substrate to form trenches with sidewalls at an angle of 54.7 degrees with respect to the top surface of the substrate. A vertical boron implant is then conducted which implants boron ions into the angled sidewalls of the trenches. A layer of oxide is then deposited over the substrate surface to fill the trenches approximately flush with the surface of the substrate. NMOS transistors may then be formed in the islands surrounded by the trenches so as to be isolated from other NMOS devices. The boron doping of the sidewalls prevents the inversion of the sidewalls due to any charged contaminants in the deposited oxide. This avoids parasitic leakage currents between the N-type source and drain regions of the NMOS transistors which abut the sidewalls of the trenches.

Abstract: A conductivity modulation type field effect transistor comprises an n.sup.- type low concentration impurity layer of high resistance formed on an n.sup.+ type silicon substrate, a first channel region of a given width formed on the low concentration impurity layer, a pair of p type gates oppositely formed with the first channel region therebetween, an n.sup.- type low concentration impurity layer formed on the first channel region including the p.sup.+ gate, a p channel layer including two channel regions formed on the n.sup.- type low concentration impurity layer, and a pair of n.sup.+ type sources formed on the second channel region with their center aligned with a center of the first gate means, in which, after the formation of the n.sup.

Abstract: A lateral bipolar transistor has an extrinsic base layer on either side of a centrally disposed emitter layer and an intrinsic base and a collector oriented perpendicularly to the extrinsic base and collector layers.

Abstract: A heterojunction bipolar transistor comprises n.sup.+ -type GaAs collector contact region, an n-type GaAs collector region, a p.sup.+ -type GaAs base region, an n-type AlGaAs emitter region, and an n.sup.+ -type InGaAs emitter contact region, all of which are formed on a semiinsulative GaAs substrate. A heterojunction is formed by the base region and the emitter region. The emitter region is formed in mesa shape by dry etching. Around this mesa, B.sup.+ ion-implanted high-resistance region is formed. The base-emitter Junction is isolated from the ion-implanted region. The heterojunction bipolar transistor therefore has little on-voltage changes.

Abstract: An image reversal process for self-aligned implants in which a mask opening and plug in the opening are used to enable one implant in the mask opening, another self-aligned implant in the region surrounding the opening, and a self-aligned electrode to be formed in the opening.

Abstract: Semiconductor devices having a reduced parasitic capacitance while having a maximum acceptable current similar to those of prior devices, and a method of manufacturing thereof are disclosed. The inventive device has a hole at the bottom of which an insulating film separated from the hole walls is located, a semiconductor film being present in the hole, which is connected to the semiconductor substrate adjacent to the insulating film and a conductor film constituting a portion of the hole wall, and extends onto the insulating film so as to cover at least part of the film.

Abstract: This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.

Abstract: A vertical bipolar transistor is constructed with reduced step height by codeposition of a polysilicon base contact member and an epitaxial device layer, thereby placing the base contact below the device surface, and by the use of a doped glass layer as a dopant source for the base contact and as a dopant source to provide a continuous conductive path to the base, and as the dielectric separating the base contact from the emitter contact, and as an etch stop when forming the base implantation aperture.

Abstract: A semiconductor structure having a high precision analog polysilicon capacitor with a self-aligned extrinsic base region of a bipolar transistor is disclosed. The structure is formed by simultaneously forming the dielectric layer of the capacitor with the formation of the base region of the bipolar transistor. A final oxidation step in the formation of the capacitor causes the base region to diffuse to form a self-aligned extrinsic base diffusion region.

Abstract: A bipolar transistor excellent in the high speed performance comprises a buried region of a first conductivity type formed in a semiconductor substrate, said buried region having a high impurity concentration, a collector region of the first conductivity type formed on the buried region, a base region of a second conductivity type formed on the collector region, an emitter region of the first conductivity type formed on the base region, and an outer base region of the second conductivity type formed to surround the base and collector regions in such a manner that an ohmic contact is provided between the base region and said outer base region and a p-n junction is formed between the collector region and said outer base region.