Dielectric In Groove Patents (Class 257/510)
  • Patent number: 11476256
    Abstract: Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 11462639
    Abstract: A method for forming a semiconductor is provided. The method includes etching a trench in a semiconductor substrate, in which the trench surrounds a device region of the semiconductor substrate; forming a conductive feature in the trench; and forming a transistor on the device region of the semiconductor substrate after forming the conductive feature.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Pan, Chia-Ta Hsieh, Po-Wei Liu, Yun-Chi Wu
  • Patent number: 11430823
    Abstract: A semiconductor image sensor device includes a semiconductor substrate, a radiation-sensing region, and a first isolation structure. The radiation-sensing region is in the semiconductor substrate. The first isolation structure is in the semiconductor substrate and adjacent to the radiation-sensing region. The first isolation structure includes a bottom isolation portion in the semiconductor substrate, an upper isolation portion in the semiconductor substrate, and a diffusion barrier layer surrounding a sidewall of the upper isolation portion.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Ting Chiang, Chun-Yuan Chen, Hsiao-Hui Tseng, Sheng-Chan Li, Yu-Jen Wang, Wei Chuang Wu, Shyh-Fann Ting, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 11417763
    Abstract: An integrated circuit includes transistors respectively including channel layers in a substrate, source electrodes and drain electrodes respectively contacting both sides of the channel layers, gate electrodes on the channel layers, and ferroelectrics layers between the channel layers and the gate electrodes. Electrical characteristics of the ferroelectrics layers of at least two of the transistors are different. Accordingly, threshold voltages of the transistors are different from each other.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangwook Kim, Yunseong Lee, Sanghyun Jo, Jinseong Heo
  • Patent number: 11410873
    Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: August 9, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Lan Yu, Tyler Sherwood, Michael Chudzik, Siddarth Krishnan
  • Patent number: 11404008
    Abstract: A display element includes a light-emitting unit of a current drive type, and a drive unit that drives the light-emitting unit, in which the drive unit includes a capacitance unit, a drive transistor that causes a current corresponding to a voltage held by the capacitance unit to flow through the light-emitting unit, and a write transistor that writes a signal voltage to the capacitance unit, the drive transistor and the write transistor are formed in a state of being separated by an element isolation region, on a semiconductor substrate, and a capacitance generated in a portion where the drive transistor and the write transistor face each other through the element isolation region functions as at least a part of the capacitance unit.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: August 2, 2022
    Assignee: Sony Group Corporation
    Inventor: Kei Kimura
  • Patent number: 11348933
    Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Justin B. Dorhout, Nancy M. Lomeli
  • Patent number: 11316020
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a first major surface, a trench extending from the first major surface into the semiconductor substrate and having a base and a side wall extending form the base to the first major surface, and a field plate arranged in the trench and an enclosed cavity in the trench. The enclosed cavity is defined by insulating material and is laterally positioned between a side wall of the field plate and the side wall of the trench.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 26, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Sylvain Leomant, Georg Ehrentraut, Maximilian Roesch
  • Patent number: 11302811
    Abstract: A silicon carbide power device, e.g., a vertical power MOSFET or an IGBT, includes a silicon carbide wafer. A first stressor and a second stressor are arranged in the silicon carbide wafer at a first main side. A first channel region, a first portion of a drift layer and a second channel region are laterally arranged between the first stressor and the second stressor in a second lateral direction parallel to the first main side and perpendicular to the first lateral direction. A stress can be introduced by the first stressor and the second stressor in the first channel region and in the second channel region.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 12, 2022
    Assignee: Hitachi Energy Switzerland AG
    Inventors: Marco Bellini, Lars Knoll, Lukas Kranz
  • Patent number: 11247895
    Abstract: A semiconductor device includes a first region; a second region that is peripheral to the first region; a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed in the first region at the first surface of the substrate; a back end of line (BEOL) stack disposed on the first surface of the semiconductor chip that extends laterally from the MEMS element, in the first region, into the second region; a first cavity formed in the BEOL stack that exposes the sensitive area of the stress-sensitive sensor, wherein the first cavity extends entirely through the BEOL stack over the first region thereby exposing a sensitive area of the stress-sensitive sensor; and at least one stress-decoupling trench laterally spaced from the stress-sensitive sensor and laterally spaced from the first cavity with a portion of the BEOL stack interposed between.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: February 15, 2022
    Inventors: Florian Brandl, Robert Gruenberger, Wolfram Langheinrich
  • Patent number: 11195964
    Abstract: Voltage breakdown devices for solar cells are described. For example, a solar cell includes a semiconductor substrate. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the substrate. A plurality of conductive contacts is coupled to the plurality of alternating N-type and P-type semiconductor regions. A voltage breakdown device is disposed above the substrate. The voltage breakdown device includes one of the plurality of conductive contacts in electrical contact with one of the N-type semiconductor regions and with one of the P-type semiconductor regions of the plurality of alternating N-type and P-type semiconductor regions disposed in or above the substrate.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: December 7, 2021
    Assignee: SunPower Corporation
    Inventor: Peter John Cousins
  • Patent number: 11177130
    Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ekmini Anuja De Silva, Dario Goldfarb, Nelson Felix, Daniel Corliss, Rudy J. Wojtecki
  • Patent number: 11069792
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 20, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Zhuofan Chen, Haiyang Zhang
  • Patent number: 11043481
    Abstract: A method of manufacturing a semiconductor package structure includes: bonding a die to a wafer; forming a dielectric material layer on the wafer to cover a top surface and sidewalls of the die; performing a removal process to remove a portion of the dielectric material layer, so as to at least expose a portion of the top surface of the die, wherein the dielectric material layer comprises a protruding part over the top surface of the die after performing the removal process; and performing a planarization process to planarize top surfaces of the die and the dielectric material layer, and thereby forming a dielectric layer laterally aside the die.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Chen-Hua Yu, Ming-Fa Chen, Wen-Chih Chiou
  • Patent number: 11031388
    Abstract: A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first and second regions; an isolation structure located in the isolation region, where the isolation structure comprises a first isolation ring having a first doping type, and a second isolation ring having a second doping type, where the first isolation ring is configured to absorb first carriers flowing from the first region to the second region, and where the second isolation ring is configured to absorb second carriers flowing from the second region to the first region; and a lateral blocking component in the isolation structure, where the lateral blocking component is configured to block a lateral flow of the first and second carriers, in order to increase a flow path of the first and second carriers in the semiconductor substrate.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 8, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Yicheng Du, Meng Wang, Hui Yu
  • Patent number: 11024663
    Abstract: The present technology relates a solid-state imaging element, an electronic apparatus, and a semiconductor device each of which enables deterioration of electrical characteristics in a well region of a semiconductor element formed in a thinned semiconductor substrate to be restrained. A solid-state imaging element as a first aspect of the present technology is a solid-state imaging element constituted by laminating semiconductor substrates in three or more layers, in which of the laminated semiconductor substrates, at least one sheet of the semiconductor substrate is thinned, and an impurity region whose carrier type is the same as that of the thinned semiconductor substrate is formed between a well region and a thinned surface portion in the thinned semiconductor substrate. The present technology can, for example, be applied to a CMOS image sensor.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 1, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hidenobu Tsugawa, Tomoharu Ogita
  • Patent number: 11011631
    Abstract: A silicon carbide substrate has at least one of a first structure and a second structure. The first structure is such that a first impurity region is in contact with a second impurity region, a third impurity region is separated from a fourth impurity region by a second drift region, and the second impurity region has a width greater than a width of the fourth impurity region in a direction parallel to a first main surface. The second structure is such that the first impurity region is separated from the second impurity region by a first drift region, the third impurity region is in contact with the fourth impurity region, and the fourth impurity region has a width greater than a width of the second impurity region in the direction parallel to the first main surface.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: May 18, 2021
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Kosuke Uchida
  • Patent number: 10978488
    Abstract: A film layer structure, a display substrate and a display device are provided. The film layer structure includes a film base, which has a curved side for adjusting stress distribution of the film layer structure.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: April 13, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xixi Guo
  • Patent number: 10910276
    Abstract: A structure, an STI structure and a related method are disclosed. The structure may include an active region extending from a substrate; a gate extending over the active region; and a source/drain region in the active region, and an STI structure. The STI structure includes a liner and a fill layer on the liner along the opposed longitudinal sides of a lower portion of the active region, and the fill layer along the opposed ends of the active region. The liner may include a tensile stress-inducing liner that imparts a transverse-to-length tensile stress in at least a lower portion of the active region but not lengthwise. The liner can be applied in an n-FET region and/or a p-FET region to improve performance.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: February 2, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yongjun Shi, Xinyuan Dou, Chun Yu Wong, Hongliang Shen, Baofu Zhu
  • Patent number: 10903220
    Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Justin B. Dorhout, Nancy M. Lomeli
  • Patent number: 10896967
    Abstract: An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-sic Yoon, Dong-oh Kim, Je-min Park, Ki-seok Lee
  • Patent number: 10868196
    Abstract: A memory device and a manufacturing method are provided. The memory device includes a substrate, first and second word lines, first and second charge trapping layers, a first drain region and a first source region. The substrate has first and second recesses extending along a first direction. The first and second word lines are respectively disposed in the first and second recesses. The first and second charge trapping layers are respectively disposed in the first and second recesses. The first charge trapping layer is located between the first word line and a sidewall of the first recess. The second charge trapping layer is located between the second word line and a sidewall of the second recess. The first and second drain regions are disposed in the substrate, and respectively extending between the first and the second charge trapping layers along a second direction.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: December 15, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Wen-Yueh Jang
  • Patent number: 10861957
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a capping layer over a fin of a fin field effect transistor (finFET), where the fin is formed of a material comprising germanium. The method also includes forming a dummy dielectric layer over the capping layer. The method also includes forming a dummy gate over the dummy dielectric layer. The method also includes removing the dummy gate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chen, Huicheng Chang, Liang-Yin Chen
  • Patent number: 10854601
    Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sun Ki Min
  • Patent number: 10811303
    Abstract: Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a seam-less film is formed. Some embodiments include optional film doping and film treatment (e.g., ion implantation and annealing).
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 20, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Pramit Manna, Ludovic Godet, Rui Cheng, Erica Chen, Ziqing Duan, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 10790384
    Abstract: A chip includes a semiconductor body coupled to a first and a second load terminal. The semiconductor body includes an active region including a plurality of breakthrough cells, each of the breakthrough cells includes: an insulation structure; a drift region; an anode region, the anode region being electrically connected to the first load terminal and disposed in contact with the first load terminal; a first barrier region arranged in contact with each of the anode region and the insulation structure, where the first barrier region of the plurality of breakthrough cells forms a contiguous semiconductor layer; a second barrier region separating each of the anode region and at least a part of the first barrier region from the drift region; and a doped contact region arranged in contact with the second load terminal, where the drift region is positioned between the second barrier region and the doped contact region.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 29, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Beninger-Bina, Thomas Basler, Matteo Dainese, Hans-Joachim Schulze
  • Patent number: 10755965
    Abstract: A method of forming a semiconductor device. The method may include providing a semiconductor device structure. The semiconductor device structure may include a semiconductor fin; and a mask, disposed over the semiconductor fin, the mask defining a plurality of openings, wherein the semiconductor fin is exposed in the plurality of openings. The method may further include directing angled ions into the plurality of openings, wherein a plurality of trenches are formed in the semiconductor fin, wherein a given trench of the plurality of trenches comprises a reentrant profile.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 25, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Min Gyu Sung
  • Patent number: 10734232
    Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for depositing metal silicide layers on substrates and chamber components. In one embodiment, a method of forming a hardmask includes positioning the substrate having a target layer within a processing chamber, forming a seed layer comprising metal silicide on the target layer and depositing a tungsten-based bulk layer on the seed layer, wherein the metal silicide layer and the tungsten-based bulk layer form the hardmask. In another embodiment, a method of conditioning the components of a plasma processing chamber includes flowing an inert gas comprising argon or helium from a gas applicator into the plasma processing chamber, exposing a substrate support to a plasma within the plasma processing chamber and forming a seasoning layer including metal silicide on an aluminum-based surface of the substrate support.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 4, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Prashant Kumar Kulshreshtha, Jiarui Wang, Kwangduk Douglas Lee, Milind Gadre, Xiaoquan Min, Paul Connors
  • Patent number: 10727316
    Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla
  • Patent number: 10714600
    Abstract: Some embodiments are directed to a bipolar junction transistor (BJT) with a collector region formed within a body of a semiconductor substrate, and an emitter region arranged over an upper surface of the semiconductor substrate. The BJT includes a base region arranged over the upper surface of the semiconductor substrate, which vertically separates the emitter and collector regions. The base region is arranged within, and in contact with, a conductive base layer, which delivers current to the base region. The base region includes a planar bottom surface, which increases contact area between the base region and the semiconductor substrate, thus decreasing resistance at the collector/base junction, over some conventional approaches. The base region can also include substantially vertical sidewalls, which increases contact area between the base region and the conductive base layer, thus improving current delivery to the base region.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lih-Tien Shyu, Yeur-Luen Tu
  • Patent number: 10707348
    Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sug-Hyun Sung, Jung-gun You, Gi-gwan Park, Ki-il Kim
  • Patent number: 10680104
    Abstract: A metal oxide semiconductor (MOS) device includes: a semiconductor layer, an isolation structure, a well, a gate, a source, a drain, a first lightly doped region, and a second lightly doped region. The first lightly doped region is located right below a spacer layer and a portion of a dielectric layer of the gate. In a channel direction, the first lightly doped region is between and contacts the drain and an inversion current channel. The second lightly doped region includes a first part and a second part. The first part is located right below the spacer which is near the source, and the first part is between and contacts the source and the inversion current channel. The second part is located right below the spacer which is near the drain, and the second part is between and contacts the drain and the first lightly doped region.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 9, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 10677855
    Abstract: Structures for measuring RIE lag depth of a semiconductor device, including: a first metal layer; a dielectric cap layer on top of the first metal layer; an electrical ground element formed beneath one or more portions of the dielectric cap layer and within the first metal layer, the electrical ground element being electrically grounded; and a second metal layer on top of the dielectric cap layer, the second metal layer having an array of one or more sub-arrays of metal wires, each sub-array being connected to a respective bond pad and having metal wires of a given width; wherein a distance from a bottom surface of the array of metal wires to a top surface of the dielectric cap layer is indicative of RIE lag depth. The disclosure also relates to methods and systems for measuring RIE lag depth and identifying the existence of an electrical short of a semiconductor device.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 9, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Nicholas V. LiCausi
  • Patent number: 10679903
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 9, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 10672866
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • Patent number: 10658369
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner, wherein the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kun-Hsin Chen, Hsuan-Tung Chu, Tsuo-Wen Lu, Po-Chun Chen
  • Patent number: 10651309
    Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
  • Patent number: 10636911
    Abstract: The present disclosure relates to a fin structure and a method for manufacturing the same. The fin structure includes a substrate and at least one fin block. The fin block is disposed on the substrate. The fin block includes an isolation layer and a top fin layer. The isolation layer is disposed on the substrate. The top fin layer is disposed on the isolation layer. At least a portion of the top fin layer is exposed. The top fin layer is an epitaxial layer. The isolation layer is in contact with the top fin layer.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: April 28, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Teng-Yen Huang
  • Patent number: 10622454
    Abstract: A method of forming a fin-type field effect transistor (FinFET) can comprise forming at least one fin having an active region and a non-active region. Thereafter, a nitride is deposited on the fin. A dummy gate and nitride mask are formed on the fin over the nitride. Oxide spacers are formed on sidewalls of the dummy gate. The nitride is removed from the fin. Thereafter, a source region and a drain region are formed in the active region of the at least one fin. The result is a more reliable finFET without any possible pinch-off problems and fin erosion. Other embodiments are also described herein.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10608000
    Abstract: A semiconductor device includes a shallow trench isolation (STI) in a substrate and a first gate structure on the STI. Preferably, the first gate structure comprises a first horizontal portion on the STI, a vertical portion connected to the first horizontal portion and extended into part of the STI, and a second horizontal portion connected to the vertical portion. The semiconductor device further includes a first spacer on a sidewall of the first gate structure and the STI and a second spacer on another sidewall of the first gate structure and on the second horizontal portion.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yukihiro Nagai
  • Patent number: 10593588
    Abstract: An electronic circuit including a semiconducting or conducting substrate having first and second opposite surfaces and at least first and second non-parallel electrically insulating trenches that extend from the first surface in the substrate, define at least one portion of the substrate and join at a junction, the portion of the substrate including a protrusion that extends to the junction.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: March 17, 2020
    Assignees: Aledia, Commissariat √† l'√Čnergie Atomique et aux √Čnergies Alternatives
    Inventors: Fabienne Goutaudier, Thomas Lacave, Vincent Beix, Stephan Borel, Bertrand Chambion, Brigitte Soulier
  • Patent number: 10580663
    Abstract: A method for forming a microelectromechanical device is shown. The method comprises forming a cavity in a semiconductor substrate material, wherein the semiconductor substrate material comprises an opening for providing access to the cavity through a main surface area of the semiconductor substrate material. In a further step, the method comprises forming a support structure having a support structure material different from the semiconductor substrate material to close the opening at least partially by mechanically connecting the main surface area of the semiconductor substrate material with the bottom of the cavity. Furthermore, the method comprises a step of forming a lamella structure in the main surface area above the cavity such that the lamella structure is held spaced apart from the bottom of the cavity by the support structure.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Thoralf Kautzsch, Steffen Bieselt, Alessia Scire
  • Patent number: 10559490
    Abstract: A device including multiple depth STI regions with sidewall profiles, and method of production thereof Embodiments include a top region having a substantially vertical sidewall profile; and a bottom region having a width greater than or equal to the top region and a sidewall profile.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Elliot John Smith, Nigel Chan, Ming-Cheng Chang
  • Patent number: 10529854
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chih-Wei Su, Je-Min Wen
  • Patent number: 10522362
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventors: Oh-Hyun Kim, Sung-Hwan Ahn, Hae-Jung Park, Tae-Hang Ahn
  • Patent number: 10522390
    Abstract: The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Patent number: 10516045
    Abstract: A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Po-Yu Chen
  • Patent number: 10510826
    Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Chieh Chan, Chung-Hui Chen
  • Patent number: 10483394
    Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
  • Patent number: 10483154
    Abstract: In various aspects, the present disclosure relates to device structures and a method of forming such a device structure. In some illustrative embodiments herein, a device is provided, including a semiconductor substrate having a first trench formed therein, and a first trench isolation structure formed in the first trench. The first trench isolation structure includes first and second insulating liners formed adjacent inner surfaces of the first trench, wherein the first insulating liner is in direct contact with inner surfaces of the first trench and the second insulating liner is formed directly on the first insulating liner, and a first insulating filling material which at least partially fills the first trench. In some aspects, a thickness of the first insulating liner is greater than a thickness of the second insulating liner.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Marcus Wolf, Carsten Peters, Markus Lenski, Loic Gaben