Combined With Pn Junction Isolation (e.g., Isoplanar, Locos) Patents (Class 257/509)
  • Patent number: 11761880
    Abstract: Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: September 19, 2023
    Assignee: KLA Corporation
    Inventors: Pradeep Vukkadala, Haiguang Chen, Jaydeep K. Sinha, Sathish Veeraraghavan
  • Patent number: 11682632
    Abstract: An integrated device that includes a substrate, a circuit region located over the substrate, a design keep out region located over the substrate, and a periphery structure located over the substrate. The design keep out region laterally surrounds the circuit region. The periphery structure includes a first plurality of interconnects that laterally surrounds the design keep out region. The periphery structure is configured to operate as an electrical seal ring and a mechanical crack stop.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: June 20, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Abhijeet Paul, Mishel Matloubian
  • Patent number: 10978596
    Abstract: A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body: and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Mario Barusic, Markus Bina, Matteo Dainese
  • Patent number: 10964814
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Yuan Liao, Chien-Chih Ho, Chi-Hsien Lin, Hua-Chou Tseng, Ho-Hsiang Chen, Ru-Gun Liu, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 10741561
    Abstract: A dynamic random access memory (DRAM) structure is provided, and the DRAM structure includes a substrate, a DRAM, and a guard ring structure. The substrate includes a memory cell region. The DRAM is disposed in the memory cell region. The DRAM includes a capacitor contact coupled to a capacitor structure. The guard ring structure surrounds a border of the memory cell region. The capacitor contact and the guard ring structure originate from the same conductive layer.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 11, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Hao Lin
  • Patent number: 10569380
    Abstract: A receiving unit receives sensor data output from an eddy current sensor for detecting the film thickness of a polishing object to generate film thickness data. A correcting unit corrects the film thickness data in an inside of the edge of the polishing object based on the film thickness data generated by the receiving unit. The correcting unit corrects the film thickness data generated by the receiving unit in the inside of the edge of the polishing object using the film thickness data generated by the receiving unit in an outside of the edge of the polishing object.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 25, 2020
    Assignee: EBARA CORPORATION
    Inventor: Akira Nakamura
  • Patent number: 10453848
    Abstract: A manufacturing method of a dynamic random access memory (DRAM) structure includes following steps. A substrate is provided, wherein the substrate includes a memory cell region and a peripheral circuit region. A DRAM is formed in the memory cell region and includes a capacitor contact coupled to a capacitor structure. A transistor structure with a metal gate structure is formed in the peripheral circuit region. The metal gate structure is formed by a manufacturing process using a dummy gate. The capacitor contact and the dummy gate are formed by the same conductive layer.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: October 22, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Hao Lin
  • Patent number: 10367158
    Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the dielectric layer. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. Metal contacts are formed on the channel material in the openings in the patterned resist layer and over portions of the patterned resist layer to protect sidewalls of the metal contacts to prevent degradation of the metal contacts.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shu-Jen Han, Jianshi Tang
  • Patent number: 10103051
    Abstract: A semiconductor structure includes a first well, a semiconductor element, a second well and a first isolation layer. The semiconductor element is formed on or contacts the first well. The first well is formed on the second well. The first isolation layer is used to reduce a parasitic effect between the first well and the second well. The bottom of the first isolation layer is at least as deep as the bottom of the first well. The first isolation layer substantially forms a first ring structure around the first well. The doping type of the second well is different from the doping type of the first well.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 16, 2018
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Jhao-Yi Lin
  • Patent number: 10002756
    Abstract: A method for fabricating a Fin-FET device includes forming a plurality of discrete fin structures on a substrate with a bottom portion of the sidewall surfaces covered in an isolation layer, and forming a dielectric layer on the isolation layer and the fin structures with an opening formed across the fin structures and exposing a portion of the isolation layer and the fin structures. The method further includes forming a first oxidation layer on the exposed surfaces of the fin structures, and then forming a second oxidation layer between the first oxidation layer and the surfaces of the fin structures through a first annealing process. The method then includes forming a gate dielectric layer on the first oxidation layer, forming a sacrificial adsorption layer on the gate dielectric layer, performing a second annealing process, and then forming a gate electrode layer to fill the opening formed in the dielectric layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 19, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 9997429
    Abstract: The present invention discloses a trench-type heat sink structure applicable to semiconductor devices. An embodiment of the present invention comprises: a first semiconductor substrate; a heat source including at least one heat spot, in which the heat source is on/in the semiconductor substrate or being a part of the semiconductor substrate; at least one first heat conduction layer; at least one first heat conduction structure configured to connect the at least one heat spot with the at least one first heat conduction layer; at least one heat sink trench; and at least one second heat conduction structure configured to connect the at least one first heat conduction layer with the at least one heat sink trench, so as to transmit heat from the heat source to the at least one heat sink trench.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 12, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 9972800
    Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the dielectric layer. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. Metal contacts are formed on the channel material in the openings in the patterned resist layer and over portions of the patterned resist layer to protect sidewalls of the metal contacts to prevent degradation of the metal contacts.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: May 15, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shu-Jen Han, Jianshi Tang
  • Patent number: 9812300
    Abstract: A silicon target for sputtering film formation which enables formation of a high-quality silicon-containing thin film by inhibiting dust generation during sputtering film formation is provided. An n-type silicon target material 10 and a metallic backing plate 20 are attached to each other via a bonding layer 40. A conductive layer 30 made of a material having a smaller work function than that of the silicon target material 10 is provided on a surface of the silicon target material 10 on the bonding layer 40 side. That is, the silicon target material 10 is attached to the metallic backing plate 20 via the conductive layer 30 and the bonding layer 40. In a case of single-crystal silicon, a work function of n-type silicon is generally 4.05 eV. A work function of a material of the conductive layer 30 needs to be smaller than 4.05 eV.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: November 7, 2017
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Hiroki Yoshikawa, Yukio Inazuki, Hideo Kaneko
  • Patent number: 9577204
    Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the dielectric layer. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. Metal contacts are formed on the channel material in the openings in the patterned resist layer and over portions of the patterned resist layer to protect sidewalls of the metal contacts to prevent degradation of the metal contacts.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shu-Jen Han, Jianshi Tang
  • Patent number: 9048110
    Abstract: An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 2, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
  • Patent number: 9000497
    Abstract: A trench MOSFET is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench MOSFET further includes a source, a drain, and a conductive element. The conductive element, like the gate is contained in the trench, and extends between the gate and a bottom of the trench. The conductive element is electrically isolated from the source, the gate, and the drain. When employed in a device such as a DC-DC converter, the trench MOSFET may reduce power losses and electrical and electromagnetic noise.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuo Sato, Tomoaki Uno, Hirokazu Kato, Nobuyoshi Matsuura
  • Patent number: 8928013
    Abstract: An organic electroluminescence device includes a first electrode, a second electrode located on a light extraction side and having a metal film, and an organic compound layer provided between the first electrode and the second electrode and including an emission layer. In addition, a first inorganic protective layer is in direct contact with the second electrode and has a specified thickness.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: January 6, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yojiro Matsuda
  • Patent number: 8912625
    Abstract: Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
  • Patent number: 8853816
    Abstract: An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: October 7, 2014
    Assignee: NXP B.V.
    Inventors: Peter Gerard Steeneken, Roel Daamen, Gerard Koops, Jan Sonsky, Evelyne Gridelet, Coenraad Cornelis Tak
  • Publication number: 20140197491
    Abstract: A semiconductor device and manufacturing method are disclosed which provide increased ESD resistance. By disposing a slit mask when forming a second p-type well layer, impurity concentration of the second p-type well layer is partially reduced. By forming a second n-type offset layer in the second p-type well layer having decreased impurity concentration, it is possible to increase thickness of the second n-type offset layer in this place compared with that heretofore known. By increasing thickness of the second n-type offset layer, a depletion layer does not reach an n-type drain layer at a low voltage when reverse bias is applied to the drain. It thus is possible to prevent thermal destruction caused by localized electrical field concentration. As a result, it is possible to increase ESD resistance. As it is sufficient to replace a photoresist mask, there is no increase in the number of processes.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 17, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu YAMAJI
  • Patent number: 8759935
    Abstract: A power semiconductor device includes an active device region disposed in a semiconductor substrate, an edge termination region disposed in the semiconductor substrate between the active device region and a lateral edge of the semiconductor substrate and a trench disposed in the edge termination region which extends from a first surface of the semiconductor substrate toward a second opposing surface of the semiconductor substrate. The trench has an inner sidewall, an outer sidewall and a bottom. The inner sidewall is spaced further from the lateral edge of the semiconductor substrate than the outer sidewall, and an upper portion of the outer sidewall is doped opposite as the inner sidewall and bottom of the trench to increase the blocking voltage capacity. Other structures can be provided which yield a high blocking voltage capacity such as a second trench or a region of chalcogen dopant atoms disposed in the edge termination region.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Schmidt
  • Publication number: 20140070361
    Abstract: Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 13, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kamel Benaissa, Amitava Chatterjee
  • Patent number: 8664742
    Abstract: An intermediate semiconductor structure that comprises a substrate and at least one undercut structure formed in the substrate is disclosed. The undercut feature may include a vertical opening having a lateral cavity therein, the vertical opening extending below the lateral cavity. The lateral cavity may include faceted sidewalls.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: March 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, H. Montgomery Manning
  • Publication number: 20140042587
    Abstract: Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.
    Type: Application
    Filed: October 15, 2013
    Publication date: February 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, JR., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
  • Patent number: 8614122
    Abstract: When forming sophisticated high-k metal gate electrode structures, a threshold adjusting semiconductor alloy may be formed on the basis of selective epitaxial growth techniques and a hard mask comprising at least two hard mask layers. The hard mask may be patterned on the basis of a plasma-based etch process, thereby providing superior uniformity during the further processing upon depositing the threshold adjusting semiconductor material. In some illustrative embodiments, one hard mask layer is removed prior to actually selectively depositing the threshold adjusting semiconductor material.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: December 24, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Gunda Beernink, Carsten Reichel
  • Patent number: 8610239
    Abstract: A semiconductor device including an isolation layer structure including a doped polysilicon layer pattern doped with first and second impurities of first and second conductivity types at lower and upper portions thereof, the doped polysilicon layer pattern being on an inner wall of a first trench on a substrate including an active region in which the first trench is not formed and a field region including the first trench, and an insulation structure filling a remaining portion of the first trench; a gate structure on the active region; a well region at a portion of the active region adjacent to lower portions of the doped polysilicon layer pattern and being doped with third impurities of the second conductivity type; and a source/drain at a portion of the active region adjacent to upper portions of the doped polysilicon layer pattern and being doped with fourth impurities of the first conductivity type.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Uk Han, Satoru Yamada
  • Publication number: 20130320487
    Abstract: A semiconductor body of a semiconductor device includes a doped layer of a first conductivity type and one or more doped zones of a second conductivity type. The one or more doped zones are formed between the doped layer and the first surface of a semiconductor body. Trench structures extend from one of the first and the second opposing surface into the semiconductor body. The trench structures are arranged between portions of the semiconductor body which are electrically connected to each other. The trench structures may be arranged for mitigating mechanical stress, locally controlling charge carrier mobility, locally controlling a charge carrier recombination rate and/or shaping buried diffusion zones.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 5, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Holger Schulze
  • Publication number: 20130307112
    Abstract: A substrate diode device having an anode and a cathode includes a doped well positioned in a bulk layer of an SOI substrate. A first doped region is positioned in the doped well, the first doped region being for one of the anode or the cathode, the first doped region having a first long axis and a second doped region positioned in the doped well. The second doped region is separate from the first doped region, the second doped region being for the other of the anode or the cathode, the second doped region having a second long axis that is oriented at an orientation angle with respect to the first long axis.
    Type: Application
    Filed: July 22, 2013
    Publication date: November 21, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Thilo Scheiper
  • Publication number: 20130285196
    Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface. A plurality of stacked ESD protection cells are in the semiconductor surface each having a surrounding isolation structure, wherein the ESD protection cells are connected in series by an interconnect and include a first ESD protection cell in series with at least a second ESD protection cell. A plurality of protection pins include a first protection pin across the first ESD protection cell but not across the second ESD protection cell to provide a first voltage rating and a second protection pin across both the first and second ESD protection cell to provide a second voltage rating which is higher than the first voltage rating.
    Type: Application
    Filed: April 26, 2012
    Publication date: October 31, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: MARIANO DISSEGNA, GIANLUCA BOSELLI
  • Publication number: 20130256831
    Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
    Type: Application
    Filed: May 23, 2013
    Publication date: October 3, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 8525291
    Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: September 3, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Tomoyuki Miyoshi, Shinichiro Wada, Yohei Yanagida
  • Patent number: 8519483
    Abstract: The semiconductor device includes a semiconductor substrate of a first type. A layer of semiconductor material of a second type is disposed on the semiconductor substrate. A first well and a second well are disposed on the layer. A third well is disposed on the layer between the first and second wells. A memory cell, including a first and a second plurality of transistors of the second type and a third plurality of transistors of the first type, is formed in the first, second, and third wells. The first plurality of transistors is formed in the first well, the second plurality of transistors is formed in the second well, and the third plurality of transistors is formed in the third well. The layer and the third well are configured to isolate the first and second wells from each other and from the semiconductor substrate.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: August 27, 2013
    Assignee: Xilinx, Inc.
    Inventor: Michael J. Hart
  • Patent number: 8481374
    Abstract: A substrate diode of an SOI device may be formed on the basis of contact regions in an early manufacturing stage, i.e., prior to patterning gate electrode structures of transistors, thereby imparting superior stability to the sensitive diode regions, such as the PN junction. In some illustrative embodiments, only one additional deposition step may be required compared to conventional strategies, thereby providing a very efficient overall process flow.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: July 9, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Thilo Scheiper
  • Publication number: 20130161741
    Abstract: A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions.
    Type: Application
    Filed: August 6, 2012
    Publication date: June 27, 2013
    Applicant: SK HYNIX INC.
    Inventor: Wan Cheul SHIN
  • Patent number: 8470643
    Abstract: Conductive core balls are joined to joint pads formed on an upper substrate. Core balls are joined to joint pads formed on an extending part of an upper-substrate substrate material. The joint pads formed on the extending part of the upper-substrate substrate material are joined to the joint pads formed on an extending part of a lower-substrate substrate material via the core balls. The joint pads formed in an area corresponding to the upper substrate of the upper-substrate substrate material are connected to the joint pads formed in an area corresponding to a lower substrate of the lower-substrate substrate material via the core balls and the conductive core balls. The upper-substrate substrate material is fixed to the lower-substrate substrate material by a mold resin supplied therebetween. The extending parts of the upper-substrate substrate material and the lower-substrate substrate material are removed, and the semiconductor packages are individualized.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: June 25, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Koichi Tanaka
  • Patent number: 8455974
    Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 4, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 8445943
    Abstract: A semiconductor integrated circuit device includes: a plurality of data holding circuits; and a plurality of wells. The plurality of data holding circuits is provided in a substrate of a first conductive type. Each of the plurality of data holding circuits includes a first well of the first conductive type and a second well of a second conductive type different from the first conductive type. The plurality of wells is arranged in two directions for the each of the plurality of data holding circuits.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: May 21, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Furuta
  • Publication number: 20130087828
    Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.
    Type: Application
    Filed: June 21, 2010
    Publication date: April 11, 2013
    Inventors: Makoto Koshimizu, Hideki Niwayama, Kazuyuki Umezu, Hiroki Soeda, Atsushi Tachigami, Takeshi Iijima
  • Patent number: 8394705
    Abstract: Provided is a method of manufacturing a semiconductor device. According to the method, a first buried oxide layer is formed in the semiconductor substrate in a first region, such that a first semiconductor layer is defined on the first buried oxide layer. An active portion is defined by forming a trench in the semiconductor substrate in a second region. A capping semiconductor pattern is formed on a top surface and an upper portion of a sidewall of the active portion. An oxide layer is formed by oxidizing the capping semiconductor pattern and an exposed lower portion of the sidewall of the active portion, such that the oxide layer surrounds a non-oxidized portion of the active portion. The non-oxidized portion of the active portion is a core and one end of the core is connected to a first optical device formed at the first semiconductor.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: March 12, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: In Gyoo Kim, Dae Seo Park, Jun Taek Hong, Gyungock Kim
  • Publication number: 20130049164
    Abstract: Disclosed herein are various methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes. In one example, the method includes performing a first angled ion implantation process to form a first doped region in a bulk layer of an SOI substrate for one of the anode or the diode and, after performing the first angled ion implantation process, performing a second angled ion implantation process to form a second doped region in the bulk layer of the SOI substrate for the other of the anode and the diode, wherein said first and second angled ion implantation process are performed through the same masking layer.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Peter Baars, Thilo Scheiper
  • Patent number: 8372716
    Abstract: In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: February 12, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Peter J. Zdebel
  • Publication number: 20120292639
    Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 22, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Miao-Cheng Liao, Min Hao Hong, Hsiang Hsiang Ko, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 8309423
    Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, Binghua Hu
  • Publication number: 20120280356
    Abstract: A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.
    Type: Application
    Filed: July 19, 2012
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wagdi W. Abadeer, Lilian Kamal, Kiran V. Chatty, Robert J. Gauthier, JR., Jed H. Rankin, Robert R. Robison, William Tonti
  • Patent number: 8299564
    Abstract: Formation of transistors, such as, e.g., PMOS transistors, with diffusion regions having different depths for equalization of performance among transistors of an integrated circuit is described. Shallow-trench isolation structures are formed in a substrate formed at least in part of silicon for providing the transistors with at least substantially equivalent channel widths and lengths. A series of masks and etches is performed to form first recesses and second recesses defined in the silicon having different depths and respectively associated with first and second transistors. The second recesses are deeper than the first recesses. A silicon germanium film is formed in the first recesses and the second recesses. The silicon germanium film in the second recesses is thicker than the silicon germanium film in the first recesses, in order to increase performance of the second transistor so it is closer to the performance of the first transistor.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: October 30, 2012
    Assignee: Xilinx, Inc.
    Inventors: Yun Wu, Bei Zhu, Zhiyuan Wu, Michael J. Hart
  • Patent number: 8283749
    Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 9, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 8260098
    Abstract: An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: September 4, 2012
    Assignee: NXP B.V.
    Inventors: Dusan Golubovic, Gerhard Koops, Tony Vanhoucke, Rob Van Dalen
  • Publication number: 20120187526
    Abstract: At least one exemplary embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several conductivity layers and a buffer layer.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 26, 2012
    Inventors: Jaume Roig-Guitart, Zia Hossain, Peter Moens
  • Publication number: 20120187527
    Abstract: At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.
    Type: Application
    Filed: September 7, 2011
    Publication date: July 26, 2012
    Inventors: Jaume Roig Guitart, Peter Moens, Zia Hossain
  • Publication number: 20120112280
    Abstract: A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey B. Johnson, Shreesh Narasimha, Hasan M. Nayfeh, Viorel Ontalus, Robert R. Robison