Abstract: A lateral bipolar transistor comprising a self-aligned polysilicon base contact, and polysilicon emitter and collector contacts is provided. The self-aligned base contact significantly reduces the base width and therefore the base resistance compared with conventional lateral bipolar transistors, thus improving f.sub.t and f.sub.max. The polysilicon emitter and collector contacts improve the emitter efficiency and current gain, and allows for more flexible contact placement. The process is compatible with conventional double-poly bipolar processes.

Abstract: A semiconductor device in which a bipolar transistor is provided, such as a BiCMOS, and a production process thereof. The device has collector region of a first conductivity type; an intrinsic base region of a second conductivity type provided on the collector region; a graft base provided on the periphery of this intrinsic base region; and an emitter region of the first conductivity type provided by self-alignment with respect to the intrinsic base. A base electrode is provided in the upper portion where the graft base is scheduled to be formed. A trench is provided by self-alignment along the end portion on the outer circumference side of this base electrode. The graft base is provided in contact with the inner circumference of this trench.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterned insulating layer as a mask to form first and second pillarss separated by a trench therein; injecting an impurity using a mask to form a collector under the first and second pillars and in the second pillar; depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base; etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; depositing a second oxide layer and a second polysilicon layer thereon; polishing the s

Abstract: A method of fabricating BiCMOS devices, and the resultant BiCMOS device, are disclosed. According to the present invention, over-etching to the substrate on the deposited polysilicon emitter is prevented by providing additional oxide beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an end-point during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT masking and oxidation steps.

Abstract: There is provided a semiconductor integrated circuit device having bipolar transistors each composed of an emitter region, base region, and collector region arranged vertically on a semiconductor substrate, said collector region having a plane figure, with the square corners thereof cut off. To be concrete, the buried collector region having a high concentration of impurity has its square corners cut off and the base region formed on the major surface of the epitaxial layer formed on said buried collector region has also its square corners cut off. The bipolar transistor having such a plane figure has a reduced parasitic capacity and an increased operating speed. A manufacturing method is also provided capable of producing a highly reliable groove isolation structure with a low dielectric constant.

Abstract: Bipolar transistors and MOS transistors on a single semiconductor substrate involves depositing a single layer of polysilicon on a substrate, including complementary transistors of either or both types, and a method for fabricating same. The devices are made by depositing a single layer of polysilicon on a substrate and etching narrow slots in the form of rings around every bipolar emitter area, which slots are thereafter filled with an insulating oxide. Then, emitters and extrinsic base regions are formed. The emitters are self-aligned to the extrinsic base regions. An optional cladding procedure produces a surface layer of a silicide compound, a low resistance conductor. The resulting structure yields a high-performance device in which the size constraints are at a minimum and contact regions may be made at the top surface of the device.

Abstract: In a bipolar device, selective epitaxial silicon provides an improved intrinsic-extrinsic base link. A trench physically separates an intrinsic and extrinsic base portion. The trench includes sidewalls having a thin oxide layer formed thereon. The bottom of the trench is exposed during processing. A shallow link between the intrinsic-extrinsic regions of a bipolar transistor base is formed by depositing a heavily boron doped layer of silicon on the exposed portion of the trench. During subsequent processing, including rapid thermal anneal, there is some boron out-diffusion which forms a shallow diffused intrinsic-extrinsic base link.

Abstract: A semiconductor device comprising a semiconductor substrate with a base region, a collector region and an emitter region in a lateral arrangement. The base region having a first conductivity type, and the collector and emitter regions having a second conductivity type. A first conductor layer is patterned over the substrate with a base contact portion, a collector contact portion and an emitter contact portion, with the base contact portion, the collector contact portion and the emitter contact portion contacting the base region, the collector region and the emitter region, respectively. A second conductor layer is patterned over a portion of the base region and is electrically coupled to the emitter contact portion, whereby the second conductor layer functions as an electrostatic shield for the base region.

Abstract: A lateral bipolar transistor structure (10) formed in a laterally isolated semiconductor device tub (22) of a first conductivity type is provided. First and second trenches are etched in the device tub and filled with doped polysilicon of a second conductivity type to form an emitter (30) and a collector (32). The portion of the tub (22) between the emitter (30) and collector (32) regions forms a base region. This configuration provides high emitter area and minimal device surface area, as well as emitter (30) and collector (32) regions which are interchangeable, greatly easing layout of integrated circuits using the transistor structure (10).

Abstract: The specification discloses a hetero bipolar transistor which comprises a semiconductor substrate, a first silicon layer serving as a collector, a first silicon-germanium layer serving as a base, a second silicon layer serving as a collector, and a second silicon-germanium layer. A side wall of the second silicon-germanium layer is in contact with side walls of the first silicon layer, the first silicon-germanium layer and the second silicon layer. The second silicon-germanium layer is disposed to surround the first silicon layer, the first silicon-germanium layer, and the second silicon layer, and has an energy band gap substantially the same as that of the first silicon-germanium layer.

Abstract: A lateral bipolar transistor has an extrinsic base layer on either side of a centrally disposed emitter layer and an intrinsic base and a collector oriented perpendicularly to the extrinsic base and collector layers.

Abstract: A bipolar transistor comprising a semiconductor substrate, of a first conductivity type, a retrograde well serving as the collector and having a second conductivity type opposite to the first, a base active region having a first conductivity type, a region serving as an emitter of the second conductivity type, the regions being bordered on either side by insulating regions. According to the invention, the transistor includes at least one second conductivity type zone serving as the collector contact, located in a region of the retrograde well at a distance from the base zone and extending away from said base zone no further than level with the insulating zone. The invention is applicable to making BI-MOS or BI-CMOS circuits.

Abstract: A method of making an improved bipolar transistor and the transistor itself having a double-self-aligned device structure are disclosed. The method and the transistor device provide self-alignment of collector-base and base-emitter junctions to each other, in addition to self-alignment of the base and emitter.

Abstract: A vertical bipolar transistor is constructed with reduced step height by codeposition of a polysilicon base contact member and an epitaxial device layer, thereby placing the base contact below the device surface, and by the use of a doped glass layer as a dopant source for the base contact and as a dopant source to provide a continuous conductive path to the base, and as the dielectric separating the base contact from the emitter contact, and as an etch stop when forming the base implantation aperture.

Abstract: Herein disclosed is an improved bipolar transistor manufacturing method which adopts an EBT (Epitaxial Base Transistor) structure using an SPESG (Selective Poly-and-Epitaxial-Silicon Growth) technique. Specifically, the method of manufacturing a bipolar transistor according to the present invention comprises the steps of: forming an isolation oxide layer to enclose an active region of a single crystal semiconductor substrate and to have a lower surface than that of the substrate of said active region; simultaneously forming a single crystal silicon layer over the substrate surface of said active region and a polycrystal silicon layer to become integral with said single crystal silicon layer over the surface of said isolation oxide layer by simultaneously growing silicon films over the substrate surface of said active region and the surface of said isolation oxide layer; and forming an active region of a semiconductor element in said single crystal silicon layer.

Abstract: A first device region (10) of one conductivity type adjacent one major surface (1a) of a semiconductor body (1) has a relatively highly doped subsidiary region (11) spaced from the one major surface (1a) by a relatively lowly doped subsidiary region (12). A second device region (20) of the opposite conductivity type within the subsidiary region (12) has an intrinsic subsidiary region (21) and an extrinsic subsidiary region (23,24) surrounding the intrinsic subsidiary region (21) forming respective first and second pn junctions (22,25) with the relatively lowly doped subsidiary region (12). A third device region (30) of the one conductivity type is formed within the intrinsic subsidiary region (21) surface (1a).

Abstract: A semiconductor integrated circuit device includes at least two bipolar transistors having a first type structure in which a wiring layer is formed in direct contact with the emitter region thereof and at least one bipolar transistor having a second type structure in which a polysilicon layer is formed on the emitter region thereof. The transistor having the first type structure is used in a circuit which is required to have a high matching degree. The transistor having the second type structure is used in a circuit which is required to have a high performance, low power consumption and high integration density rather than a high matching degree.

Abstract: A bipolar transistor excellent in the high speed performance comprises a buried region of a first conductivity type formed in a semiconductor substrate, said buried region having a high impurity concentration, a collector region of the first conductivity type formed on the buried region, a base region of a second conductivity type formed on the collector region, an emitter region of the first conductivity type formed on the base region, and an outer base region of the second conductivity type formed to surround the base and collector regions in such a manner that an ohmic contact is provided between the base region and said outer base region and a p-n junction is formed between the collector region and said outer base region.

Abstract: A p-type polycrystalline silicon layer (45) serving as the base electrode of an npn transistor and a p-type polycrystalline silicon layer (50) serving as the emitter electrode of a pnp transistor are simultaneously formed by forming a p-type polycrystalline silicon on the entire surface and patterning the same. Similarly, an n-type polycrystalline silicon layer (46) serving as the emitter electrode of the npn transistor and an n-type polycrystalline silicon layer (49) serving as the base electrode of the pnp transistor are simultaneously formed by forming an n-type polycrystalline silicon on the entire surface and patterning the same. Thus, electrodes can be formed without selective impurity implantation and the mask alignment therefor.

Abstract: There is disclosed herein a transistor having a sidewall base contact. The base region of the transistor is in a column of selectively grown epitaxial silicon isolated from adjacent structures in a field of oxide. The sidewall base contact is a layer of doped polysilicon which is embedded in the insulating material surrounding the column of epitaxial silicon. The collector contact is formed of another column of selectively grown epitaxial silicon grown over and in electrical contact with a buried layer underlying the first column of epitaxial silicon. The emitter region is implanted into the top of column doped as the base region. In one embodiment, the base contact is a buried polysilicon layer. In another embodiment, the base contact is epitaxial silicon which is grown over oxide by uncontrolled growth following controlled selective growth.

Abstract: A new composition and method of making same for a doped zinc oxide microsphere and articles made therefrom for use in an electrical surge arrestor which has increased solid content, uniform grain size and is in the form of a gel.