Sides Of Isolated Semiconductor Islands Along Major Crystal Planes (e.g., (111), (100) Planes, Etc.) Patents (Class 257/527)
  • Patent number: 8883565
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Mathias Vaupel, Sebastian Bernrieder, Adolf Koller, Stefan Martens
  • Patent number: 8829617
    Abstract: A method including providing a plurality of fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the plurality of fins and the nitride layer, removing a portion of the plurality of fins to form an opening, and forming a dielectric spacer on a sidewall of the opening. The method may also include filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer, removing the nitride layer to form a gap between the plurality of fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the plurality of fins and the fill material to widen.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian S. Haran, Sanjay Mehta, Shom Ponoth, Ravikumar Ramachandran, Stefan Schmitz, Theodorus E. Standaert
  • Patent number: 8735858
    Abstract: An ionic device includes a layer of an ionic conductor containing first and second species of impurities. The first species of impurity in the layer is mobile in the ionic conductor, and a concentration profile of the first species determines a functional characteristic of the device. The second species of impurity in the layer interacts with the first species within the layer to create a structure that limits mobility of the first species in the layer.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: May 27, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dmitri B. Strukov, Alexandre M. Bratkovski, R. Stanley Williams, Zhiyong Li
  • Patent number: 8559186
    Abstract: An inductor with patterned ground plane is described. In one design, the inductor includes a conductor formed on a first layer and a patterned ground plane formed on a second layer under the conductor. The patterned ground plane has an open center area and a shape matching the shape of the conductor. The patterned ground plane includes multiple shields, e.g., eight shields for eight sides of an octagonal shape conductor. Each shield has multiple slots formed perpendicular to the conductor. Partitioning the patterned ground plane into separate shields and forming slots on each shield help prevent the flow of eddy current on the patterned ground plane, which may improve the Q of the inductor. Multiple interconnects couple the multiple shields to circuit ground, which may be located at the center of the conductor.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: October 15, 2013
    Assignee: QUALCOMM, Incorporated
    Inventor: Zhang Jin
  • Patent number: 8386883
    Abstract: A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells, including at least a first group with at least one cell. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way (the cells can be PCM or another technology).
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michele Franceschini, John Peter Karidis, Luis A Lastras-Montano, Thomas Mittelholzer, Mark N Wegman
  • Patent number: 8299565
    Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lidija Sekaric, Tymon Barwicz, Dureseti Chidambarrao
  • Patent number: 8294213
    Abstract: A semiconductor photodiode device includes a semiconductor substrate, a first buffer layer containing a material different from that of the semiconductor substrate in a portion thereof, a first semiconductor layer formed above the buffer layer and having a lattice constant different from that of the semiconductor substrate, a second buffer layer formed above the first semiconductor layer and containing an element identical with that of the first semiconductor layer in a portion thereof, and a second semiconductor layer formed above the buffer layer in which a portion of the first semiconductor layer is formed of a plurality of island shape portions each surrounded with an insulating film, and the second buffer layer allows adjacent islands of the first semiconductor layer to coalesce with each other and is in contact with the insulating film.
    Type: Grant
    Filed: July 17, 2010
    Date of Patent: October 23, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Miura, Shinichi Saito, Youngkun Lee, Katsuya Oda
  • Patent number: 8164085
    Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: April 24, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yosuke Shimamune, Hiroyuki Ohta, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
  • Patent number: 8159051
    Abstract: In one aspect of the present invention, a semiconductor device may include a first semiconductor layer of a first conductivity type and having a main surface that has a first plane orientation, a second semiconductor layer of the first conductivity type and having a main surface that has a second plane orientation different from the first plane orientation, the second semiconductor layer being directly provided on the first semiconductor layer, a third semiconductor layer having a main surface that has the first plane orientation, and being formed on the first semiconductor layer and on a side face of the second semiconductor layer, a gate electrode formed on the second semiconductor layer via a gate insulating film, first impurity diffusion regions of a second conductivity type, and being formed in the second semiconductor layer so that the gate electrode is located on a region sandwiched in a gate length direction between the first impurity diffusion regions, the first impurity diffusion regions extending t
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: April 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuaki Yasutake
  • Patent number: 8122596
    Abstract: An image is captured or otherwise converted into a signal in an artificial vision system. The signal is transmitted to the retina utilizing an implant. The implant consists of a polymer substrate made of a compliant material such as poly(dimethylsiloxane) or PDMS. The polymer substrate is conformable to the shape of the retina. Electrodes and conductive leads are embedded in the polymer substrate. The conductive leads and the electrodes transmit the signal representing the image to the cells in the retina. The signal representing the image stimulates cells in the retina.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: February 28, 2012
    Assignees: Lawrence Livermore National Security, LLC, Doheny Eye Institute
    Inventors: Peter Krulevitch, Dennis L. Polla, Mariam N. Maghribi, Julie Hamilton, Mark S. Humayun, James D. Weiland
  • Patent number: 7968432
    Abstract: A laser processing apparatus has one laser light source that simultaneously radiates laser beams with two wavelengths. Depth positions of focusing points for laser beams are gradually changed in a wafer. Three sets of modifying region groups, i.e., six layers of modifying region groups, are successively formed. One set of modifying region groups constitutes two layers and is formed at a time. The modifying region groups are separated, adjoined, or overlapped with each other along an estimated cut line of the wafer in a depth direction from a surface thereof.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: June 28, 2011
    Assignee: DENSO CORPORATION
    Inventors: Muneo Tamura, Tetsuo Fujii
  • Patent number: 7960801
    Abstract: A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventor: Dureseti Chidambarrao
  • Patent number: 7898012
    Abstract: A capacitor includes a pair of electrodes and a ferroelectric film sandwiched between the electrodes. The electrodes are provided perpendicular to the direction of the polarization axis of the ferroelectric film.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: March 1, 2011
    Assignee: Fujitsu Limited
    Inventor: Kenji Maruyama
  • Patent number: 7884448
    Abstract: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: February 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Patent number: 7875521
    Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: January 25, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yosuke Shimamune, Hiroyuki Ohta, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
  • Patent number: 7855435
    Abstract: According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: December 21, 2010
    Assignees: Qimonda AG, Altis Semiconductor, SNC
    Inventors: Ulrich Klostermann, Rainer Leuschner
  • Patent number: 7834425
    Abstract: The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Meikei Ieong, Xinlin Wang, Min Yang
  • Patent number: 7810233
    Abstract: An image is captured or otherwise converted into a signal in an artificial vision system. The signal is transmitted to the retina utilizing an implant. The implant consists of a polymer substrate made of a compliant material such as poly(dimethylsiloxane) or PDMS. The polymer substrate is conformable to the shape of the retina. Electrodes and conductive leads are embedded in the polymer substrate. The conductive leads and the electrodes transmit the signal representing the image to the cells in the retina. The signal representing the image stimulates cells in the retina.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: October 12, 2010
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Peter Krulevitch, Dennis L. Polla, Mariam N. Maghribi, Julie Hamilton, Mark S. Humayun, James D. Weiland
  • Patent number: 7675091
    Abstract: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: March 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Soo Park, Kyoo-Chul Cho, Shin-Hyeok Han, Tae-Soo Kang
  • Patent number: 7655511
    Abstract: A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: February 2, 2010
    Assignee: International Business Machines Corporation
    Inventor: Dureseti Chidambarrao
  • Patent number: 7652351
    Abstract: A semiconductor device according to an embodiment of the present invention includes a plurality of chip regions and a plurality of chip rings. The plurality of chip regions include semiconductor integrated circuits each having a multilayered wiring structure using a metal wiring, and are formed into independent chips. The plurality of chip rings has the multilayered wiring structure using the metal wiring, and surround the respective chip regions. The plurality of chip rings are electrically connected to one another.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: January 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyuki Higashi, Noriaki Matsunaga
  • Patent number: 7649243
    Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: January 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 7615849
    Abstract: In a semiconductor device having SiC vertical trench MOSFETs, it is aimed to prevent the generation of large scattering in the channel resistance without largely increasing the average value of channel resistance. A 4H-SiC substrate having a major face thereof that is generally a {0001} face and having an off angle ?. The trench is formed with the standard deviation ? in scattering of the angle formed by a trench side wall face and a substrate major face within a wafer face. By setting the designed value of the angle formed by the trench side wall face and the substrate major face at an any angle ranging from [(60 degrees)+2?] to [(90 degrees)?tan?1 (0.87×tan ?)?2?] in forming the trench in the SiC substrate, a semiconductor device in which the angle formed by the trench side wall face and the substrate major face is 60 degrees or more but not more than [(90 degrees)?tan?1 (0.87×tan ?)] can be obtained.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: November 10, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Shun-Ichi Nakamura, Yoshiyuki Yonezawa, Hiroyuki Fujisawa, Takashi Tsuji
  • Publication number: 20090267196
    Abstract: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
    Type: Application
    Filed: July 9, 2009
    Publication date: October 29, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Patent number: 7566949
    Abstract: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: July 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Patent number: 7518210
    Abstract: Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: April 14, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Sun Yun, Jin-Hyun Shin
  • Patent number: 7479671
    Abstract: A memory cell includes a semiconductor feature and a phase change material. The semiconductor feature defines a groove that divides the semiconductor feature into a first electrode and a second electrode. The phase change material at least partially fills this groove and acts to electrically couple the first and second electrodes. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to at least one of the first and second electrodes. The semiconductor feature comprises silicon and the groove comprises at least one silicon sidewall with a substantially <111> crystal plane orientation.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: January 20, 2009
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Chung Hon Lam, Alejandro Gabriel Schrott
  • Patent number: 7459406
    Abstract: Objects of the present invention is to reduce a number of scanning a linear laser, to shorten the amount of time for laser annealing, and to reduce a manufacturing process, a manufacturing time, and manufacturing cost of a semiconductor device. In this invention, a gas at high temperature is locally blown so as to overlap at an irradiation surface of linear laser light. The linear laser light can be obtained by injecting laser light radiated from a laser oscillator into a lens. The gas at high temperature can be obtained by heating a gas which is compressed using a gas compressor, by a nozzle type heater. The heated has is sprayed so as to overlap with the irradiation surface of the linear laser light.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: December 2, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Yoshiaki Yamamoto
  • Patent number: 7456450
    Abstract: The present invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region comprises a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, at least one n-channel field effect transistor (n-FET) can be formed at the first device region, which comprises a channel that extends along the interior surfaces of the first recess. At least one p-channel field effect transistor (p-FET) can be formed at the second device region, which comprises a channel that extends along the interior surfaces of the second recess.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: November 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Xiangdong Chen, James J. Toomey, Haining S. Yang
  • Patent number: 7342293
    Abstract: The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends between the first STI region and the collection region and undercuts a portion of the active base region with an undercut angle of not more than about 90°. For example, the second STI region may a substantially triangular cross-section with an undercut angle of less than about 90°, or a substantially rectangular cross-section with an undercut angle of about 90°. Such a second STI region can be fabricated using a porous surface section formed in an upper surface of the collector region.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: March 11, 2008
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Wallner, Thomas N. Adam, Stephen W. Bedell, Joel P. De Souza
  • Patent number: 7335910
    Abstract: An object of the present invention is to provide a thin film transistor having a high mobility and having fewer fluctuations in the mobility or threshold voltage characteristics. A non-single-crystal semiconductor thin film having a thickness of less than 50 nm and disposed on an insulating substrate is irradiated with laser light having an inverse-peak-patterned light intensity distribution to grow crystals unidirectionally in a lateral direction. Thus, band-like crystal grains having a dimension in a crystal growth direction, which is longer than a width, are arranged adjacent to each other in a width direction to form a crystal grain array. A source region and a drain region of a TFT are formed so that a current flows in the crystal growth direction in an area including a plurality of crystal grains of this crystal grain array.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: February 26, 2008
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Tomoya Kato, Masakiyo Matsumura, Yoshiaki Nakazaki
  • Patent number: 7208815
    Abstract: In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: April 24, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang, Chenming Hu
  • Patent number: 7208803
    Abstract: A method of forming a raised source/drain proximate a spacer of a gate of a transistor on a substrate, and a semiconductor device of an integrated circuit employing the same. In one embodiment, the method includes orienting the gate substantially along a <100> direction of the substrate. The method also includes providing a semiconductor material adjacent the spacer of the gate to form a raised source/drain layer of the raised source/drain oriented substantially along a <100> direction of the substrate.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: April 24, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Steve Ming Ting
  • Patent number: 7196400
    Abstract: An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semiconductor device using a crystalline semiconductor film with high quality equivalent to a single crystal. A first crystalline semiconductor film and a second crystalline semiconductor film are formed overlying a substrate, which integrally structure a crystalline semiconductor layer. The first and second crystalline semiconductor films are polycrystalline bodies aggregated with a plurality of crystal grains. However, the crystal grains are aligned toward a (101)-plane orientation at a ratio of 30 percent or greater, preferably 80 percent or greater.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: March 27, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara
  • Patent number: 7183598
    Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: February 27, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yang-Tung Fan, Chiou-Shian Peng, Cheng-Yu Chu, Shih-Jane Lin, Yen-Ming Chen, Fu-Jier Fan, Kuo-Wei Lin
  • Patent number: 7170109
    Abstract: A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are laminated in this order. The element isolation structure is composed of a trench, a semiconductor film, and first and second insulating films. The trench extends through the semiconductor layer and extends to the inside of the compound semiconductor layer. The semiconductor film is provided on the surface of the trench, and the first insulating film is provided on the semiconductor film. The second insulting film is provided on the first insulating film and fills the trench.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: January 30, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kohei Sugihara, Kazunobu Ota, Hidekazu Oda, Takahashi Hayashi
  • Patent number: 7138319
    Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Kiang-Kai Han
  • Patent number: 7045880
    Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 16, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Wendell P. Noble, Leonard Forbes, Alan R. Reinberg
  • Patent number: 6995456
    Abstract: Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. The first-type transistors are on first portions of the substrate that have a first type of crystalline orientation and second-type transistors are on second portions of the substrate that have a second type of crystalline orientation. The straining layer is above the first-type transistors and the second-type transistors. Further, the straining layer can be strained above the first-type transistors and relaxed above the second-type transistors.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: February 7, 2006
    Assignee: International Business Machines Corporation
    Inventor: Edward J. Nowak
  • Patent number: 6960821
    Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: November 1, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Wendell P. Noble, Leonard Forbes, Alan R. Reinberg
  • Patent number: 6903368
    Abstract: A thin film made of silicon or another IV-group crystals (crystals and mixed crystals of C, Ge, Sn, and Pb) is twice scanned with a laser beam moving in two lateral directions in which crystal grains grow larger in order to form high-quality polycrystals in exact positions in the thin film, while defects uncontrollable by the prior arts are being reduced significantly, to realize a high-quality TFT device. The laser-scanning directions are defined by the crystallization face orientations.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: June 7, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Shinya Yamaguchi, Mutsuko Hatano, Takeo Shiba
  • Patent number: 6825115
    Abstract: Dopant deactivation, particularly at the Si/silicide interface, is avoided by forming deep source/drain implants after forming silicide layers on the substrate and activating the source/drain regions by laser thermal annealing. Embodiments include forming source/drain extensions, forming metal silicide layers on the substrate surface and gate electrode, forming preamorphized regions under the metal silicide layers in the substrate, ion implanting to form deep source/drain implants overlapping the preamorphized regions and extending deeper into the substrate then the preamorphized regions, and laser thermal annealing to activate the deep source/drain regions.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: November 30, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Qi Xiang, Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery, Bin Yu
  • Publication number: 20040195646
    Abstract: A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation also overlies the insulator layer. In one embodiment, the silicon-on-insulator chip also includes a first transistor of a first conduction type formed on the first silicon island, and a second transistor of a second conduction type formed on the second silicon island. For example, the first crystal orientation can be (110) while the first transistor is a p-channel transistor, and the second crystal orientation can be (100) while the second transistor is an n-channel transistor.
    Type: Application
    Filed: April 4, 2003
    Publication date: October 7, 2004
    Inventors: Yee-Chia Yeo, Fu-Liang Yang
  • Patent number: 6730981
    Abstract: In an element formation region, a surface of an N− epitaxial layer is inclined upward from an end of a field oxide film to a sidewall of an opening. An external base diffusion layer at the surface of the N− epitaxial layer is inclined upward from a side of the field oxide film to the sidewall of the opening, and is exposed at the sidewall of the opening. A portion of the sidewall of the opening exposing the external base diffusion layer is tapered. The depth of a lower end of the external base diffusion layer or the sidewall of the opening is substantially equal to or smaller than that of a bottom of the opening. A decrease in breakdown voltage between an emitter and a base is suppressed, and decrease and variation of current gain hFE is suppressed.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: May 4, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Hidenori Fujii
  • Patent number: 6639280
    Abstract: A laminated substrate is formed by laminating a device formation layer made of single crystalline semiconductor on a supporting substrate made of single crystalline semiconductor via an insulating layer with making one direction of a crystallographic axis of the device formation layer be shifted from a corresponding direction of a crystallographic axis of the supporting substrate. Semiconductor devices are formed in the device formation layer within a plurality of areas divided by scribe lines extending to a direction being parallel to a direction of a crystallographic axis where the supporting substrate is easy to be cleaved. The laminated substrate is split into a plurality of chips by cleaving the supporting substrate along the scribe lines. A semiconductor device can easily be split into chips even if a moving direction of carrier and an extending direction of wiring are shifted from an easy-cleaved direction of a crystallographic axis.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: October 28, 2003
    Assignee: Fujitsu Limited
    Inventors: Shinji Sugatani, Satoshi Sekino
  • Publication number: 20030146489
    Abstract: A semiconductor device provided with an isolation oxide film formed by a trench isolation technique is described. The device prevents the development of crystal defects from the corners of a trench and secures stable operating characteristics. The semiconductor device is provided with an isolation oxide film formed so that boundaries between an active region and the isolation oxide film extend in a direction inclined at an angle in the range of 45°±10° to the cleavage plane of a silicon substrate. The isolation oxide film has a interior wall oxide film of a thickness in the range of 50 Å to 1000 Å coating the side walls and the bottom wall of a trench, and a filling oxide film filling up the trench coated with the interior wall oxide film. The edges of the active region contiguous to the isolation oxide film are rounded properly.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 7, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Satoshi Shimizu
  • Publication number: 20030047734
    Abstract: A bi-layer silicon electrode and its method of fabrication is described. The electrode of the present invention comprises a lower polysilicon film having a random grain microstructure, and an upper polysilicon film having a columnar grain microstructure.
    Type: Application
    Filed: September 7, 2001
    Publication date: March 13, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Li Fu, Shulin Wang, Luo Lee, Steven A. Chen, Errol Sanchez
  • Publication number: 20030006477
    Abstract: Porous dielectric materials having low dielectric constants, ≧30% porosity and a closed cell pore structure are disclosed along with methods of preparing the materials. Such materials are particularly suitable for use in the manufacture of electronic devices.
    Type: Application
    Filed: September 24, 2001
    Publication date: January 9, 2003
    Applicant: Shipley Company, L.L.C.
    Inventors: Michael K. Gallahger, Robert H. Gore, Angelo A. Lamola, Yujian You
  • Patent number: 6486525
    Abstract: An integrated circuit having improved soft error protection and a method improving the soft error protection of an integrated circuit are disclosed. The integrated circuit comprises a substrate 72, a transistor formed in the substrate 72, a first region 74 (e.g. a well) formed in the substrate having a first conductivity type, a second region 84 below the first region 74 having a second conductivity type, and a trench formed in the substrate having a depth at least substantially as deep as the well. The trench 70 is filled with a non-conductive material 71 that forms a frame around the transistor, whereby soft errors due to electron-hole pairs caused by ionizing radiation in the frame are substantially eliminated.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: November 26, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Thomas J. Aton
  • Patent number: 6404027
    Abstract: A high dielectric rare earth oxide of the form Mn2O3 (such as, for example, Gd2O3 or Y2O3) is grown on a clean silicon (100) substrate surface under an oxygen partial pressure less than or equal to 10−7 torr to form an acceptable gate oxide (in terms of dielectric constant (∈˜18) and thickness) that eliminates the tunneling current present in ultra-thin conventional SiO2 dielectrics and avoids the formation of a native oxide layer at the interface between the silicon substrate and the dielectric. Epitaxial films can be grown on vicinal silicon substrates and amorphous films on regular silicon substrates to form the high dielectric gate oxide.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: June 11, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Minghwei Hong, Ahmet Refik Kortan, Jueinai Raynien Kwo, Joseph Petrus Mannaerts