Abstract: A high dielectric rare earth oxide of the form Mn2O3 (such as, for example, Gd2O3 or Y2O3) is grown on a clean silicon (100) substrate surface under an oxygen partial pressure less than or equal to 10−7 torr to form an acceptable gate oxide (in terms of dielectric constant (∈˜18) and thickness) that eliminates the tunneling current present in ultra-thin conventional SiO2 dielectrics and avoids the formation of a native oxide layer at the interface between the silicon substrate and the dielectric. Epitaxial films can be grown on vicinal silicon substrates and amorphous films on regular silicon substrates to form the high dielectric gate oxide.

Abstract: A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on the element forming region and extended over the element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under the gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near the gate electrode on the second impurity region.

Abstract: A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist layer thereon, and then exposing predetermined portions of the photoresist layer to ultraviolet light to establish a desired groove pattern in the photoresist layer. A dry etching process is then used to remove the nitride and/or oxide layers beneath the groove pattern of the photoresist layer to thereby expose portions of the substrate. Next, the wafer is disposed in a wet etching solution such as potassium hydroxide to form grooves in the exposed portions of the silicon substrate. The wafer is oriented and disposed in the bath as appropriate for forming V-shaped grooves, such that after etching, the angled walls of the grooves can be easily exposed to a dopant beam directly above the wafer, without having to tilt the wafer or beam source. Thereby, the walls of the grooves are easily implanted with dopant.

Abstract: A source and drain diffusion layer of a transistor has a junction of a shallow depth and low in parasitic resistance and parasitic capacitance.The transistor includes a gate insulator formed on a principal plane of a semiconductor substrate, a gate electrode formed on the gate insulator, and source and drain diffusion layers of one conductivity type formed on the principal plane of the semiconductor substrate across the gate electrode. A semiconductor thin film layer doped with an impurity of the same conductivity type is selectively deposited on the principal plane of the semiconductor substrate on which the source and drain diffusion layers are formed. A facet face is formed at an end portion of the semiconductor thin film which opposes to a sidewall of the gate electrode. The facet face has an inclination angle between a sidewall face of the gate electrode and the principal plane of the semiconductor substrate.

Abstract: A method is provided for forming a semiconductor device including a semiconductor body having a first surface and a second surface located opposite the first surface, with a plurality of vertical semiconductor components extending between the first and second surfaces. At least one partial structure having a lateral semiconductor component is disposed beneath the first surface. An electrically-insulating vertical wall surrounds the partial structure and extends into the semi-conductor body a predetermined depth from the first surface. The second surface of the semiconductor surface of the semiconductor body includes a recess in the region of the partial structure. The bottom of the recess extends to the vertical wall at the predetermined depth from the first surface. An insulating layer covers the bottom of the recess.