Abstract: A semiconductor device includes an etching protection layer to protect a metal layer in a bonding pad area when a metal fuse is etched.

Abstract: A fuse element is laminated on a resistor and the resistor is formed in a concave shape below a region in which cutting of the fuse element is carried out with a laser. Accordingly, there can be provided a semiconductor device which occupies a small area, causes no damage on the resistor in the cutting of the fuse element, has a small contact resistance occurred between elements, and has stable characteristics, and a method of manufacturing the same.

Abstract: An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.

Abstract: A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

Abstract: A semiconductor device includes a first terminal, a second terminal, and a fuse link that connects between the first terminal and the second terminal. The first terminal and the fuse link have a polysilicon layer doped with an impurity ion and a layer containing a metal element laminated on the polysilicon layer. The second terminal has a polysilicon layer not doped with an impurity ion and a layer containing a metal element laminated on the polysilicon layer, in at least a part of an end side connected to the fuse link.

Abstract: A disclosed method of producing a semiconductor device includes the steps of (A) forming a gate electrode and a trimming fuse on a semiconductor substrate; (B) forming a side wall insulating film covering the gate electrode and the trimming fuse; (C) forming a conductive film on the side wall insulating film and patterning the conductive film to form an etching stop layer and a resistance element; (D) forming a side wall on the sides of the gate electrode; (E) repeating, one or more times, sub-steps of forming an interlayer insulating film and of forming an upper wiring layer, and then forming a passivation film; (F) removing the passivation film and the interlayer insulating film in the trimming opening forming area until the etching stop layer is exposed; and (G) forming the trimming opening by removing the etching stop layer in the trimming opening forming area.

Abstract: A semiconductor device is provided including a first fuse link having a copper-containing metal film, a second fuse link having a polysilicon film, a semiconductor substrate, and a field insulating film formed on the semiconductor substrate. The second fuse link is formed on the field insulating film. An interlayer insulating film is provided between the first fuse link and the second fuse link. The first fuse link is electrically connected to the second fuse link via a first plug formed in the interlayer insulating film.

Abstract: Embodiments of a system with first means for forming a chamber adjacent to a component formed on a substrate and a single orifice between the chamber and a first surface of the first means that is opposite a second surface of the first means adjacent to the substrate and second means for enclosing the chamber on at least a portion of the first surface that encompasses the single orifice are disclosed.

Abstract: Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.

Abstract: A method for manufacturing a fuse box of a semiconductor device includes forming an interlayer dielectric film over a semiconductor substrate including a given lower structure; forming a metal line and a fuse over the interlayer dielectric film; forming a first protective film over the resulting structure; etching the first protective film and the fuse at a given depth by a photo-etching process with a repair mask to form an open region; and forming a second protective film vertical to the fuse.

Abstract: A fuse element utilizing a reaction between two layers by feeding current is manufactured. A fuse element including a first layer formed of an oxide or a nitride and a second layer that becomes high resistant by nitridation or oxidation, in which the first layer and the second layer are in contact with each other, is manufactured. For example, the fuse element is manufactured by using indium tin oxide for the first layer and aluminum for the second layer. By generating joule heat by applying voltage to the first layer and the second layer, oxygen in the indium tin oxide enters the aluminum, which changes the aluminum into aluminum oxide that presents an insulating property. The fuse element can be manufactured by a similar process as that of forming a TFT.

Abstract: A resistor circuit includes first to Mth resistor circuit units. A (2j?1)th resistor circuit unit includes a (2j?1)th first fuse element and a (2j?1)th resistor provided in series between a (2j?1)th node and a 2jth node, and a (2j?1)th second fuse element provided in parallel with the (2j?1)th first fuse element and the (2j?1)th resistor between the (2j?1)th node and the 2jth node. A 2jth resistor circuit unit includes a 2jth first fuse element and a 2jth resistor provided in series between the 2jth node and a (2j+1)th node, and a 2jth second fuse element that is provided in parallel with the 2jth first fuse element and the 2jth resistor between the 2jth node and the (2j+1)th node. The (2j?1)th first fuse element, the (2j?1)th second fuse element, the 2jth first fuse element, and the 2jth second fuse element are disposed in a fuse region. The (2j?1)th resistor is disposed in a first resistor region formed in a first direction with respect to the fuse region.

Abstract: An electrical fuse is formed on a semiconductor substrate and a first dielectric layer is formed over the electrical fuse. At least one opening is formed by lithographic methods and a reactive ion etch in the first dielectric layer down to a top surface of the electrical fuse or down to shallow trench isolation. A second dielectric layer is deposited by a non-conformal deposition. Thickness of the second dielectric layer on the sidewalls of the at least one opening increases with height so that at least one cavity encapsulated by the second dielectric layer is formed in the at least one opening. The at least one cavity provides enhanced thermal isolation of the electrical fuse since the cavity provides superior thermal isolation than a dielectric material.

Abstract: A voltage switchable dielectric material (VSD) material as part of a light-emitting component, including LEDs and OLEDs.

Abstract: The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to the electrically conductive plate is a fuse. The invention also includes methods of forming semiconductor fuse arrangements.

Abstract: A polysilicon resistor fuse has an elongated bow-tie body that is wider at the opposite ends relative to a narrow central portion. The opposite ends of the body of the fuse have high concentrations of N-type dopants to make them low resistance contacts. The upper portion of the central body has a graded concentration of N-type dopants that decreases in a direction from the top surface toward the middle of the body between the opposite surfaces. The lower central portion of the body is lightly doped with P-type dopants. The central N-type region is a resistive region.

Abstract: A semiconductor device includes a protection target element formed on a semiconductor substrate and includes a protection target element electrode, a substrate connecting part including a substrate connecting electrode electrically connected to the semiconductor substrate and a fuse structure provided between the protection target element electrode and the substrate connecting electrode and includes a fuse film configured to be torn by applying a predetermined current thereto. The protection target element electrode, the substrate connecting electrode and the fuse film are formed of an integral conductive film as long as the fuse film is not torn.

Abstract: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.

Abstract: A semiconductor device includes a lower pad layer, an insulating layer and an upper pad layer. The lower pad layer is provided on a semiconductor substrate. The insulating layer is away from a surrounding of the lower pad layer so that a space having a recess on a surface between the lower pad layer and the insulating layer is formed. The upper pad layer covers over the lower pad layer and the space, extends to an upper face of the insulating layer, and has an area larger than that of the lower pad layer.

Abstract: Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.

Abstract: Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Abstract: A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse.

Abstract: A method for forming a fuse in a semiconductor device is disclosed. The method for forming the fuse in the semiconductor device forms an interlayer insulating layer when forming a fuse, and forms neighboring metal lines having different thicknesses using a zigzag-opened mask, thus preventing a neighboring fuse of a fuse to be blown from being damaged. A method for manufacturing the semiconductor device deposits a first interlayer insulating layer on a semiconductor substrate, patterns the first interlayer insulating layer using a zigzag-opened pad type mask such that the first interlayer insulating layer has different step heights where the same step height is arranged at every second step height location, deposits a second interlayer insulating layer, patterns the second interlayer insulating layer, and buries a metal on an entire surface, and planarizes the metal until the second interlayer insulating layer is exposed, thus forming a metal pattern.

Abstract: An electrically alterable circuit (EAC), suitable for use in an integrated circuit, includes a first interconnect, a link element, and a second interconnect. A first set of interconnect vias provides an electrically conductive connection between the first interconnect and a first end of the link element; A second set of interconnect vias provides an electrically conductive connection between the second interconnect and a second end of the link element. The EAC further includes a third interconnect and a one or more fuse vias that provide an electrical connection between the third interconnect and the link element. A conductance of the one or more fuse vias is less than a conductance of the first set of interconnect vias, a conductance of the second set of interconnect vias, or both.

Abstract: The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered. A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.

Abstract: In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.

Abstract: A semiconductor device having a fuse structure that can prevent a bridge between a fuse pattern and a guard ring, and a method of fabricating the same are provided. The fuse pattern formed on a multiple-layered metal interconnect layer is stepped shape increasing a vertical distance between the fuse pattern and the guard ring.

Abstract: An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.

Abstract: A semiconductor device package, and a semiconductor module and an electronic apparatus including the semiconductor device package are provided. The semiconductor device package includes a package substrate, first pads and second pads disposed on a first surface of the package substrate and fuses corresponding to the second pads, the fuses being disposed on a second surface of the package substrate. First and second semiconductor chips including a plurality of chip pads are disposed on the first surface of the package substrate and the first pads are electrically connected to both one of the chip pads of the first semiconductor chip and one of the chip pads of the second semiconductor chip, wherein the second pads are selectively electrically connected to one of the chip pads of the first semiconductor chip or one of the chip pads of the second semiconductor chip.

Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.

Abstract: The invention relates to a semiconductor fuse structure comprising a substrate (1) having a surface, the substrate (1) having a field oxide region (3) at the surface, the fuse structure further comprising a fuse body (FB), the fuse body (FB) comprising polysilicon (PLY), the fuse body (FB) lying over the field oxide region (3) and extending into a current-flow direction (CF), wherein the fuse structure is programmable by means of leading a current through the fuse body (FB), wherein the fuse body (FB) has a tensile strain in the current-flow direction (CF) and a compressive strain in a direction (Z) perpendicular to said surface of the substrate (1). The invention further relates to methods of manufacturing such a semiconductor fuse.

Abstract: The present invention provides a semiconductor device realizing reliable cutting of a fuse without enlarging layout area of a fuse element and the reduced number of wiring layers of a preventing wall that prevents diffusion of fuse copper atoms. A fuse is formed by using a wire in a metal wiring layer as an upper layer in a plurality of metal wiring layers. Wires are disposed just above and just below a fuse each with a gap of at least two wiring layers. In an upper layer, a power wire that transmits power supply voltage is used as a part covering a preventing wall structure just above the fuse.

Abstract: The semiconductor device of the present invention comprises a semiconductor substrate; and a conductive element formed on the semiconductor substrate and capable of being opened when a predetermined current flows, wherein the conductive element turns plurality of times.

Abstract: A unit memory circuit includes a fuse element capable of electrically programming data. A sense amplifier circuit is connected to the fuse element. The sense amplifier circuit senses data of the fuse element. Either of a first interconnect and a second interconnect is selectively formed by changing an interconnect formation mask. The first interconnect is short-circuiting the fuse element and the second interconnect is cutting off a current path when data is read from the fuse element.

Abstract: Devices and methods are disclosed a dielectric interlayer made of materials capable of forming tensile force is formed over a semiconductor substrate, and a fuse metal having stronger tensile force than the first dielectric interlayer is formed over the first dielectric interlayer. Accordingly, formation of fuse residues when blowing a fuse can be prevented. Furthermore, energy and a spot size of a laser applied when blowing a fuse can be reduced. Moreover, damage to neighboring fuses can be prevented, and a fuse made of materials that are difficult to blow the fuse can be cut. Further, since polymer-series materials are used as a dielectric interlayer, the coupling effect between wiring lines can be reduced considerably.

Abstract: An e-fuse structure includes an anode, a cathode, a fuse part connecting the anode and the cathode to each other, and a dielectric contacting the fuse part. The dielectric is configured to apply a stress to the fuse part, where the stress constructively acting on a migration effect of atoms constituting the fuse part. The migration effect is generated by electromigration and thermomirgration.

Abstract: Provided are an electrical fuse, a semiconductor device having the same, and a method of programming and reading the electrical fuse. The electrical fuse includes first and second anodes disposed apart from each other. A cathode is interposed between the first and second anodes. A first fuse link couples the first anode to the cathode, and a second fuse link couples the second anode to the cathode.

Abstract: A semiconductor device has a plurality of fuse element portions each of which including a first fuse interconnect having a fuse to be portion, a second fuse interconnect connected to an internal circuit, a first impurity diffusion layer for electrically connecting the first fuse interconnect and the second fuse interconnect, and a second impurity diffusion layers. The first fuse interconnect, the second fuse interconnect, and the first impurity diffusion layer of each of the plurality of fuse element portions are arranged approximately parallel to one another at a predetermined pitch distance.

Abstract: The present invention provides a manufacturing method for forming an integrated circuit device and to a corresponding integrated circuit device. The manufacturing method for forming an integrated circuit device comprises the steps of: forming a first level on a substrate; forming a second level above the first level; forming a cap layer on the second level which covers a first region of the level and leaves a second region uncovered; and simultaneously etching a first contact hole in the first region and a second contact hole in the second region such that the etching is selective to the cap layer in the second region and proceeds to a greater depth in the first region.

Abstract: An integrated circuit includes a fuse over a substrate. The fuse has a first end, a second end, and a central portion between the first end and the second end. A first dummy pattern is disposed adjacent to each side of the central portion of the fuse.

Abstract: An e-fuse and an e-fuse control circuit are provided. The e-fuse includes a polysilicon layer and a metal silicide layer stacked on the polysilicon layer. The e-fuse operates in an open state when the silicide layer is broken by burning while one portion of the polysilicon layer is exposed.

Abstract: A method of programming a transistor-based fuse structure is provided. The fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate.

Abstract: An antifuse (40, 80, 90?) comprises, first (22?, 24?) and second (26?) conductive regions having spaced-apart curved portions (55, 56), with a first dielectric region (44) therebetween, forming in combination with the curved portions (55, 56) a curved breakdown region (47) adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region (42) is desirably provided adjacent the breakdown region (47) to inhibit heat loss from the breakdown region (47) during programming. Lower programming voltages and currents are observed compared to antifuses (30) using substantially planar dielectric regions (32).

Abstract: Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a ?-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void. The design structure for the fuse is embodied in a machine-readable medium for designing, manufacturing or testing a design of the fuse.

Abstract: A two terminal switching device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes a stimulus circuit in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.

Abstract: By stably separating a melting location of a fuse (3) from conductive layers (5A, 5B), reliable melting of the fuse (3) is enabled. A fuse (3) including a fuse body (3A) and two pads (3Ba, 3Bb) connected by this and two conductive layers (5A, 5B) individually connected to the two pads (3Ba, 3Bb) are formed in a multilayer structure on a semiconductor substrate (1). A length of the fuse body (3A) is defined so that the melting location of the fuse (3) becomes positioned in the fuse body (3A) away from the region overlapped on the conductive layer (5A or 5B) when an electrical stress is applied between two conductive layers (5A, 5B) and the fuse (3) is melted.

Abstract: A semiconductor device includes: a lower layer interconnection formed on a chip; an upper layer interconnection formed in an upper layer above the lower layer interconnection above the chip; an interconnection via formed to electrically connect the lower layer interconnection and the upper layer interconnection; a via-type electric fuse formed to electrically connect the lower layer interconnection and the upper layer interconnection. The fuse is cut through heat generation, and a sectional area of the fuse is smaller than a sectional area of the upper layer interconnection and a via diameter of the fuse is smaller than that of the interconnection via.

Abstract: A fuse structure includes a non-planar fuse material layer typically located over and replicating a topographic feature within a substrate. The non-planar fuse material layer includes an angular bend that assists in providing a lower severance current within the non-planar fuse material layer.

Abstract: A nano-fuse structural arrangement, includes, for example, a semiconductor substrate having an electrically conductive region formed thereon; an electrically conductive elongated nano-structure having a maximum diameter of less than approximately 50 nm and a maximum length of approximately 250 nm and being formed on the electrically conductive region; a barrier having barrier parts completely spaced from and completely surrounding elongated outer surfaces of the nano-structure, the spaces between the barrier and surfaces consisting essentially of a vacuum and being approximately equally spaced, so that the electrically conductive elongated nano-structure is blowable responsive to an electrical current flowable there through in a range of approximately 4 ?A to approximately 120 ?A.