Abstract: Embodiments of the invention provides a method, device, and system for programming an electromigration fuse (eFuse) using a radio frequency (RF) signal. A first aspect of the invention provides a method of testing circuitry on a semiconductor chip, the method comprising: receiving a radio frequency (RF) signal using at least one antenna on the semiconductor chip; powering circuitry on the semiconductor chip using the RF signal; activating a built-in self test (BIST) engine within the circuitry; determining whether a fault exists within the circuitry using the BIST; and programming an electromigration fuse (eFuse) to alter the circuitry in response to a fault being determined to exist.

Abstract: A semiconductor package includes a semiconductor chip having a circuit section. A first chip selection electrode passes through a first position of the semiconductor chip, and the first chip selection electrode has a first resistance and outputs a first signal. A second chip selection electrode passes through a second position of the semiconductor chip, and the second chip selection electrode has a second resistance greater than the first resistance and outputs a second signal. A signal comparison part is formed in the semiconductor chip and is electrically connected to the first and second chip selection electrodes. The signal comparison part compares the first signal applied from the first chip selection electrode to the second signal applied from the second chip selection electrode and outputs a chip selection signal to the circuit section depending upon the result of the comparison.

Abstract: A semiconductor device includes: a plurality of NAND memory dies each including: a first wiring layer formed in the NAND memory die; a second wiring layer formed in the NAND memory die; a first insulation layer formed between the first wiring layer and the second wiring layer; and a first interlayer connector formed in the first insulation layer, a controller configured to control the NAND memory dies; a package housing the NAND memory dies and the controller; a connecting portion electrically connecting an inner side of the package and an outer side of the package; a first connecting wire; and a second connecting wire, wherein a resistance value per unit length of the first interlayer connector is larger than a resistance value per unit length of the first wiring layer, and wherein the first interlayer connector is cut off when a first current flows through the first interlayer connector.

Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Abstract: A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.

Abstract: A semiconductor device comprises a fuse having a blowing region at a center part for selectively connecting different two terminals; and a dummy contact positioned under the blowing region for forming empty space by being removed together with the blowing region in a blowing process.

Abstract: An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost.

Abstract: Multi-purpose poly edge test structure. According to an embodiment, the present invention provides a test structure. The test structure includes a doped silicon substrate, the doped silicon substrate being grounded, the doped silicon substrate including a first gate structure and a second gate structure, the first and second gate structures overlaying the doped silicon substrate. The test structure also includes a first conducting pad being electrically coupled to the first gate structure. The test structure also includes a second conducting pad being electrically coupled to the second gate structure.

Abstract: An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Abstract: A semiconductor device includes: a lower layer interconnection formed on a chip; an upper layer interconnection formed in an upper layer above the lower layer interconnection above the chip; an interconnection via formed to electrically connect the lower layer interconnection and the upper layer interconnection; a via-type electric fuse formed to electrically connect the lower layer interconnection and the upper layer interconnection. The fuse is cut through heat generation, and a sectional area of the fuse is smaller than a sectional area of the upper layer interconnection and a via diameter of the fuse is smaller than that of the interconnection via.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.

Abstract: A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.

Abstract: Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device.

Abstract: A fuse structure for a semiconductor integrated circuit (IC) can include a first node comprising a region of a metal layer of an IC manufacturing process and a second node comprising a region of a conductive layer residing on a layer of the IC manufacturing process below the metal layer of the first node. The fuse structure can include a fuse link comprising a conductive material, positioned substantially perpendicular to each of the metal and conductive layers. An upper end of the fuse link couples to the first node and a lower end of the fuse link, that is distal to the upper end, couples to the second node.

Abstract: A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The plurality of fuses may be arranged to correspond to the plurality of capacitor layers, and/or the plurality of fuses may be configured to select corresponding ones of the plurality of capacitor layers for controlling a capacitance of the plurality of capacitor layers.

Abstract: Nanotube switching devices having nanotube bridges are disclosed. Two-terminal nanotube switches include conductive terminals extending up from a substrate and defining a void in the substrate. Nantoube articles are suspended over the void or form a bottom surface of a void. The nanotube articles are arranged to permanently contact at least a portion of the conductive terminals. An electrical stimulus circuit in communication with the conductive terminals is used to generate and apply selected waveforms to induce a change in resistance of the device between relatively high and low resistance values. Relatively high and relatively low resistance values correspond to states of the device. A single conductive terminal and a interconnect line may be used. The nanotube article may comprise a patterned region of nanotube fabric, having an active region with a relatively high or relatively low resistance value. Methods of making each device are disclosed.

Abstract: A fuse of a semiconductor device includes first fuse metals formed over an underlying structure and a second fuse metal formed between the first fuse metals. Accordingly, upon blowing, the fuse metals are not migrated under conditions, such as specific temperature and specific humidity. Thus, reliability of a semiconductor device can be improved.

Abstract: A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region.

Abstract: A circuit board includes a semiconductor chip having an upper surface and side surfaces connected to the upper surface. A bonding pad is disposed on the upper surface of the semiconductor chip. A bump is disposed on the bonding pad and projects from the bonding pad by a predetermined height. A circuit board body has a recess part, and the semiconductor chip is positioned in the recess part so that the circuit board body covers the upper surface and the side surfaces of the semiconductor chip while exposing an end of the bump. A wiring line is disposed on the circuit board body and part of the wiring line is positioned over the bump. An opening is formed in a portion of the part of the wiring line over the bump to expose the bump. A reinforcing member physically and electrically connects the exposed bump and the wiring line.

Abstract: A pressure sensor includes a sense element port, a support ring and a plurality of interference fit slits to provide a flexible interference fit between the sense element port and the support ring to form a substantially flush lap joint. The sensor also includes an electronics board inside the support ring and attached to planar mounting tabs which provide a stable mounting. Gel flow barriers protect electronics board features from unwanted non-conductive gel. Double-ended symmetrical, tapered contact springs provide manufacturing cost savings and contribute to improved alignment of an interface connector of the sensor.

Abstract: A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Abstract: The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.

Abstract: An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the same or different networks selected from the group consisting of the one or more power distribution networks, the one or more ground distribution networks, the one or more data networks, and combinations thereof.

Abstract: Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and operate the apparatus and systems. Additional apparatus, systems, and methods are disclosed.

Abstract: A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.

Abstract: A semiconductor device includes a first island and a first electrode. The first island includes a first semiconductor region, a first insulation region, and a first insulating film. The first semiconductor region has first and second side surfaces adjacent to the first insulation region and the first insulating film, respectively. The first electrode is adjacent to the first insulation region and the first insulating film. The first insulating film is between the first electrode and the first semiconductor region.

Abstract: A fuse element utilizing a reaction between two layers by feeding current is manufactured. A fuse element including a first layer formed of an oxide or a nitride and a second layer that becomes high resistant by nitridation or oxidation, in which the first layer and the second layer are in contact with each other, is manufactured. For example, the fuse element is manufactured by using indium tin oxide for the first layer and aluminum for the second layer. By generating joule heat by applying voltage to the first layer and the second layer, oxygen in the indium tin oxide enters the aluminum, which changes the aluminum into aluminum oxide that presents an insulating property. The fuse element can be manufactured by a similar process as that of forming a TFT.

Abstract: A semiconductor device includes a plurality of stacked semiconductor chips; and a plurality of through-silicon vias (TSVs) including first TSVs and redundant TSVs and configured to commonly transfer a signal to the plurality of stacked semiconductor chips. At least one of the semiconductor chips includes a plurality of repair fuse units configured to store defect information as to at least one defect of the TSVs; and a plurality of latch units allocated to the respective TSVs and configured to store a plurality of signals indicating at least one TSV defect and outputted from the plurality of repair fuse units.

Abstract: According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a fuse window overlying the at least one fuse are, in one embodiment, formed in a same etch process. The method further includes performing at least one electrical measurement on the at least one electrical monitoring structure, wherein the at least one electrical measurement is utilized to monitor the structural integrity of the at least one fuse. A change in the at least one electrical measurement is utilized to indicate a change in the structural integrity of the at least one fuse. The at least one electrical monitoring structure can include, for example, a metal serpentine line and one or more metal combs.

Abstract: A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.

Abstract: A capacitor insulating film for use as an insulating film sandwiched between two electrodes is made of a crystal containing a hafnium element in a titanium site in place of a part of titanium elements contained in a crystal of a strontium titanate or barium strontium titanate.

Abstract: Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially the same dimensions as conductive features, such as conductive lines or vias, or are substantially the same dimensions as fill structures of the semiconductor device.

Abstract: A fuse structure for a semiconductor integrated circuit (IC) includes an anode comprising conductive material overlaying a diffusion material disposed within a substrate layer of the IC, wherein the diffusion material is electrically isolated from the substrate layer by at least one p-n junction. The fuse structure can include a cathode comprising conductive material overlaying the diffusion material. The fuse structure further can include a fuse link comprising conductive material overlaying the diffusion material, wherein a first end of the fuse link couples to the anode and a second end of the fuse link, that is distal to the first end, couples to the cathode.

Abstract: The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.

Abstract: A non-volatile resistive memory is provided. The memory includes at least one non-volatile memory cell and selection circuitry. Each memory cell has a two-terminal nanotube switching device having and a nanotube fabric article disposed between and in electrical communication with two conductive terminals. Selection circuitry is operable to select the two-terminal nanotube switching device for read and write operations. Write control circuitry, responsive to a control signal, supplies write signals to a selected memory cell to induce a change in the resistance of the nanotube fabric article, the resistance corresponding to an informational state of the memory cell. Resistance sensing circuitry in communication with a selected nonvolatile memory cell, senses the resistance of the nanotube fabric article and provides the control signal to the write control circuitry. Read circuitry reads the corresponding informational state of the memory cell.

Abstract: The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.

Abstract: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.

Abstract: A semiconductor chip includes: a semiconductor substrate in which a bonding pad is provided on a first surface thereof; a through silicon via (TSV) group including a plurality of TSVs connected to the bonding pad and exposed to a second surface opposite to the first surface of the semiconductor substrate; and a fuse box including a plurality of fuses connected to the plurality of TSVs and formed on the first surface of the semiconductor substrate.

Abstract: A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second plurality of memory elements disposed above the first plurality of memory elements.

Abstract: The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in contact with the second insulating layer and the metal layer.

Abstract: In a complex semiconductor device, electronic fuses may be formed in the active semiconductor material by using a semiconductor material of reduced heat conductivity selectively in the fuse body, wherein, in some illustrative embodiments, the fuse body may be delineated by a non-silicided semiconductor base material.

Abstract: A semiconductor device includes a first metal wiring which is formed over substructure; a first contact plug which is coupled to the first metal wiring and passes through a first interlayer insulating film provided over the substructure; a second metal wiring which is provided over the first interlayer insulating film and is coupled to the first contact plug; a second contact plug which is coupled to the second metal wiring and passes through a second interlayer insulating film which is provided over the first interlayer insulating film; and a fuse pattern and a data read fuse pattern which are coupled to the second contact plug and provided over the second interlayer insulating film.

Abstract: A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, fanning an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.

Abstract: A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.

Abstract: A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region.

Abstract: An integral circuit protection device includes a substrate disposed between first and second terminals. The substrate is composed of a resistive material. A first conductive layer is disposed on a first surface of the substrate and in electrical contact with the first terminal. A second conductive layer is disposed on a second surface of the substrate. A first electrically insulating layer is disposed on the second conductive layer and substantially covers the second conductive layer. The first electrically insulating layer includes an aperture. A fuse element is disposed on the first electrically insulating layer and is in electrical contact with the second conductive layer through the aperture and in electrical contact with the second terminal. The fuse element is in electrical series with the resistive material. A second electrically insulating layer is disposed over the fuse element.

Abstract: The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to the electrically conductive plate is a fuse. The invention also includes methods of forming semiconductor fuse arrangements.

Abstract: A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.