Including Programmable Passive Component (e.g., Fuse) Patents (Class 257/529)
  • Patent number: 10840049
    Abstract: Fuse programming circuits, devices and methods. In some embodiments, a fuse circuit can include a fuse pad configured to receive a voltage, a fuse having a first end coupled to the fuse pad and a second end coupled to a switching element configured to enable a current to pass from the fuse pad to a ground potential.
    Type: Grant
    Filed: July 15, 2018
    Date of Patent: November 17, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: Bo Zhou
  • Patent number: 10811354
    Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems associated with a fuse array of an integrated circuit. An integrated circuit may include a first metallization layer including a plurality of trenches separated by an interlayer dielectric (ILD), wherein the ILD forms a protrusion that extends above a top surface of the trenches. An etch stop layer may be disposed on the first metallization layer. The integrated circuit may further include a fuse disposed on the etch stop layer, wherein the fuse includes a fuse channel coupled between an anode and a cathode, wherein the fuse channel is disposed directly above the protrusion and is in contact with the etch stop layer. The integrated circuit may additionally or alternatively include one or more dummy regions adjacent to the fuse channel and separated from the fuse channel by a dielectric material. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Gwang-Soo Kim, Doug B. Ingerly
  • Patent number: 10784195
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Xiaoqiang Zhang, Haizhou Yin, Moosung M. Chae, Jinping Liu, Hui Zang
  • Patent number: 10775631
    Abstract: According to various embodiments, an electronic device includes: a housing including: a first plate; a second plate facing a direction opposite a direction of the first plate; and a sidewall surrounding a first space between the first plate and the second plate, the first space being a sealed space; and at least one electronic component arranged in the first space of the housing, wherein at least a part of the sidewall of the housing includes a moisture induction portion configured to induce moisture in the first space to be generated in a moisture induction region of the moisture induction portion that may be due, for example, to a difference in temperature between the first space and an external environment.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sukjin Yun, Seunghoon Kang, Kyeongsoo Kim, Jaecheon Kim, Hongki Moon, Yoonsun Park, Hyunjin Bai, Jaewook Jeong, Seungbo Hong, Jiseong Hwang
  • Patent number: 10770393
    Abstract: Back end of the line precision resistors that allow for high currents and for configuration as an eFuse by embedding a single thin film high resistive metal material within a dielectric layer, wherein the resisters are coupled to sidewalls of adjacent metal interconnects are described. The resistors can be formed in the metal one (M1) dielectric layer and can be coupled to sidewalls of the M1 interconnects. Also described are processes for fabricating integrated circuits including the resistors and/or e-Fuses.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew Tae Kim, Baozhen Li, Ernest Y. Wu, Chih-Chao Yang
  • Patent number: 10756082
    Abstract: A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song
  • Patent number: 10727181
    Abstract: A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Jae-Hong Kim, Seo-Woo Nam
  • Patent number: 10727116
    Abstract: Electronic device manufacturing and configuration methods include performing an additive deposition process that deposits a conductive, resistive, magnetic, semiconductor and/or thermally conductive material over a surface of a processed wafer metallization structure to set or adjust a circuit of a capacitor, an inductor, a resistor, an antenna and/or a thermal component of the metallization structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Paul Merle Emerson, Benjamin Stassen Cook
  • Patent number: 10720488
    Abstract: Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mattias Erik Dahlström, Li Jen Choi
  • Patent number: 10714200
    Abstract: A method for programming an electrically programmable fuse is disclosed. As conductive medium of the electrically programmable fuse exhibits different physical changes under different conditions, the conductive medium is changed from an initial physical state to a first physical state by using a first programming condition to program the electrically programmable fuse from a low resistance state to a medium resistance state, and the conductive medium is changed from the initial physical state or the first physical state to a second physical state by using a second programming condition to program the electrically programmable fuse from the low resistance state or the medium resistance state to a high resistance state. Transitions of three information storage states are achieved through two different programming conditions, so that the information storage density and chip area utilization rate of an electrically programmable fuse device can be significantly improved, and chip size reduction is facilitated.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 14, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuilong Yu, Kun Han
  • Patent number: 10629429
    Abstract: Methods and apparatuses for selectively depositing silicon oxide on a silicon oxide surface relative to a silicon nitride surface are described herein. Methods involve pre-treating a substrate surface using ammonia and/or nitrogen plasma and selectively depositing silicon oxide on a silicon oxide surface using alternating pulses of an aminosilane silicon precursor and an oxidizing agent in a thermal atomic layer deposition reaction without depositing silicon oxide on an exposed silicon nitride surface.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Lam Research Corporation
    Inventors: David Charles Smith, Dennis M. Hausmann
  • Patent number: 10622319
    Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekta Misra, Krishna R. Tunga
  • Patent number: 10619266
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate is provided. A pad metal and a fuse metal are formed on the substrate. A liner is formed on the pad metal and on the fuse metal. An etching stop layer is formed on the portion of the liner on the fuse metal. A dielectric layer and a passivation layer are formed on the liner and on the etching stop layer. After defining a pad opening and a fuse opening in the passivation layer, a first etching step is performed to remove the dielectric layer from the pad opening and the fuse opening until the pad metal and the etching stop layer are exposed. Afterward, a second etching step is performed to remove the exposed etching stop layer from the fuse opening until the liner on the fuse metal is exposed.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: April 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ming-Feng Kuo
  • Patent number: 10615119
    Abstract: Techniques facilitating back end of line electrical fuse structure and method of fabrication are provided. A device can comprise a first metal interconnect formed in a dielectric layer of a semiconductor chip. The device can also comprise a second metal interconnect formed in the dielectric layer and adjacent to the first metal interconnect. Further, the device can comprise a vertical electrical fuse element comprising a first portion of a conductive material deposited on a first surface of the first metal interconnect and a second portion of the conductive material deposited on a second surface of the second metal interconnect. The vertical electrical fuse element can comprise a first region comprising a first thickness and a second region comprising a second thickness different than the first thickness.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10607934
    Abstract: A fuse of a semiconductor device may include: a fuse link suitable for extending in a first direction and connecting first and second electrodes; a dummy strip suitable for extending in the first direction, and with a predetermined distance from the fuse link in a second direction perpendicular to the first direction; and an air channel formed between the fuse link and the dummy strip to contact with the fuse link.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 31, 2020
    Assignees: SK hynix Inc., INDUSTRY-ACAMEDIA COOPERATION GROUP OF SEJONG UNIVERSITY
    Inventors: Deok-Kee Kim, Jae Hong Kim, Seo Woo Nam
  • Patent number: 10600902
    Abstract: A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: March 24, 2020
    Assignee: Vishay Siliconix, LLC
    Inventor: Robert Xu
  • Patent number: 10597321
    Abstract: Processes of chamfering and/or beveling an edge of a glass substrate of arbitrary shape using lasers are described herein. Two general methods to produce chamfers on glass substrates are the first method involves cutting the edge with the desired chamfer shape utilizing an ultra-short pulse laser to create perforations within the glass; followed by an ion exchange.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: March 24, 2020
    Assignee: Corning Incorporated
    Inventors: Sasha Marjanovic, David Andrew Pastel, Garrett Andrew Piech, Jose Mario Quintal, Helmut Schillinger, Sergio Tsuda, Robert Stephen Wagner, Andrea Nichole Yeary
  • Patent number: 10586799
    Abstract: A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate. The method further includes converting the second material to a resistive material. The layers that include the resistive material form one or more electrical fuses.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Patent number: 10586855
    Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: March 10, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Hyun-Jin Cho, Tenko Yamashita, Hui Zang
  • Patent number: 10553535
    Abstract: A method for fabricating a semiconductor device including an electrically programmable fuse includes patterning dielectric material formed on a first electrode including a first conductive material to create one or more openings, and forming second conductive material within the one or more openings. Forming the second conductive material includes forming one or more voids encapsulated by the second conductive material such that the one or more voids have boundaries defined in part by portions of the second conductive material disposed between the one or more voids and the dielectric material. The portions of the second conductive material correspond to fuse links.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Chih-Chao Yang
  • Patent number: 10546822
    Abstract: A seal ring structure of an integrated circuit including a first discontinuous seal wall circumscribing a first portion of the integrated circuit, the first seal wall forming a first pattern on a substrate, and a second discontinuous seal wall circumscribing a second portion of the integrated circuit, the second seal wall forming a second pattern on the substrate and the second portion being at least partially offset from the first portion, wherein the first pattern of the first seal wall interlocks with the second pattern of the second seal wall such that the patterns are interweaved without intersecting, wherein a space is formed between the seal walls, the space creating a non-linear path to the integrated circuit, and wherein the seal ring structure fully circumscribes the integrated circuit. A method of forming such a seal ring structure is also disclosed.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: January 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas A. Polomoff, Vincent J. McGahay
  • Patent number: 10515852
    Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element electrically connected to the conductive feature. A first portion of the resistive element is over the dielectric layer, and a second portion of the resistive element extends towards the conductive feature.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Sheh Huang, Hsiu-Wen Hsueh, Yu-Hsiang Chen, Chii-Ping Chen
  • Patent number: 10504997
    Abstract: A semiconductor structure includes a substrate and a silicon-germanium (SiGe) fin formed on the substrate. The SiGe fin has a first portion having a first doping profile and a second portion having a second doping profile. The first portion of the SiGe fin has a Si-rich outer surface.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki, Koji Watanabe
  • Patent number: 10497700
    Abstract: An anti-fuse for a semiconductor device includes an electrode; a gate metal formed to extend from the electrode; a gate oxide layer formed under the gate metal; a semiconductor layer formed under the gate oxide layer to overlap with a center portion of the gate metal; and a first oxide layer formed under the gate metal and the gate oxide layer and on both sides of the semiconductor layer.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: December 3, 2019
    Assignees: SK hynix Inc., INDUSTRY-ACADEMIA COOPERATION GROUP OF SEJONG UNIVERSITY
    Inventors: Deok-kee Kim, Honggyun Kim, Jae Hong Kim, Seo Woo Nam
  • Patent number: 10472731
    Abstract: A method of forming a semiconductor structure is disclosed. A substrate is provided with a pad metal and a fuse metal formed thereon. A liner and an etching stop layer are formed at least covering a top surface of the fuse metal. A dielectric layer is formed on the substrate and a passivation layer is formed over the dielectric layer. A pad opening and a fuse opening are defined in the passivation layer. A first etching step is performed to remove the dielectric layer from the pad opening and the fuse opening to expose a top surface of the pad metal from the pad opening and an upper surface of the etching stop layer from the fuse opening respectively. A second etching step is performed to remove the etching stop layer from the fuse opening until an upper surface of the liner is exposed.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ming-Feng Kuo
  • Patent number: 10453792
    Abstract: A semiconductor device including an anti-fuse is disclosed. The semiconductor anti-fuse includes a highly doped source of a first conductivity type overlying a substrate. The semiconductor anti-fuse further includes a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate. The semiconductor anti-fuse further includes a highly doped fuse region extending over the highly doped source and including an epitaxial growth, the highly doped fuse region implanted with ions.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Pouya Hashemi, Miaomiao Wang, Takashi Ando
  • Patent number: 10424521
    Abstract: A method includes fabricating a set of die in a production run, each die comprising a set of pads at a periphery of a top metal layer, a first set of fuse elements, and a second set of fuse elements. Each fuse element of the first set of fuse elements couples a corresponding pad of the set to a corresponding bus when in a conductive state, and each fuse element of the second set couples a corresponding subset of pads of the set together when in a conductive state. The method further includes selecting a subset of the die of the production run for testing, and configuring each die of the subset for testing by placing each fuse element of the first set in a non-conductive state and placing each fuse element of the second set in a conductive state.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: September 24, 2019
    Assignee: NXP USA, INC.
    Inventor: George R. Leal
  • Patent number: 10381585
    Abstract: A thin film transistor includes a gate electrode, a insulating medium layer and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating medium layer. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating medium layer. The semiconducting structure includes a carbon nanotube structure. The second electrode is located on the second end.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 13, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Yuan-Hao Jin, Tian-Fu Zhang, Qun-Qing Li
  • Patent number: 10374180
    Abstract: A thin film transistor includes a gate, an insulating medium layer and a Schottky diode. The Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode is located on the surface of the insulating medium layer and includes a first metal layer and a second metal layer. The second electrode is located on the surface of the insulating medium layer and includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure includes a carbon nanotube structure.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 6, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Yuan-Hao Jin, Tian-Fu Zhang, Qun-Qing Li
  • Patent number: 10366855
    Abstract: Some embodiments include a fuse element assembly having a first portion configured to rupture as materials of the first portion flow to a second portion through electromigration. The assembly has a second portion configured to accumulate the materials that have flowed from the first portion. The assembly also has a control element configured to divide the flow of materials into at least two paths along the second portion. The first portion may be a fuse-link and the second portion may be a cathode coupled to the fuse-link through a narrow neck region. The control element may be, for example, a slit, a hole, a conductive contact, etc.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Sumio Ogawa
  • Patent number: 10366916
    Abstract: A semiconductor structure includes a substrate having a first region and a second region being adjacent each other; a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the patterned layer; and a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring includes a first width W1 and is spaced a first distance D1 from the first features, W1 being greater than D1.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chihy-Yuan Cheng, Chun-Chang Wu, Shun-Shing Yang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen
  • Patent number: 10336069
    Abstract: In one example, a printhead having an electrically-functional optical target. The printhead includes a substrate. An optical target having an optically-distinguishable shape and formed from at least one polysilicon strip is deposited on the substrate. An electrical connection to at least one of the polysilicon strips connect the strip into a circuit that is deposited on the substrate.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 2, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Ser Chia Koh, Chaw Sing Ho, John Patrick Oliver
  • Patent number: 10325846
    Abstract: A fuse structure may include an anode pattern, a cathode pattern and a connection member. The anode pattern may be formed on a semiconductor substrate. The cathode pattern may be formed on the anode pattern. The connection member may be electrically connected between the anode pattern and the cathode pattern. The connection member may have different widths.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventor: Dong Yean Oh
  • Patent number: 10301173
    Abstract: The present invention generally relates to an RF MEMS DVC and a method for manufacture thereof. To ensure that undesired grain growth does not occur and contribute to an uneven RF electrode, a multilayer stack comprising an AlCu layer and a layer containing titanium may be used. The titanium diffuses into the AlCu layer at higher temperatures such that the grain growth of the AlCu will be inhibited and the switching element can be fabricated with a consistent structure, which leads to a consistent, predictable capacitance during operation.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: May 28, 2019
    Assignee: CAVENDISH KINETICS, INC.
    Inventor: Mickael Renault
  • Patent number: 10276526
    Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: April 30, 2019
    Assignee: Powertech Technology Inc.
    Inventors: Hung-Hsin Hsu, Nan-Chun Lin, Shang-Yu Chang Chien
  • Patent number: 10276495
    Abstract: A semiconductor die including a substrate, a device layer over the substrate, and an adjustable component in the device layer is provided, where a surface of the device layer opposite the substrate is the frontside of the semiconductor die. At least a portion of the substrate is removed to expose a backside of the semiconductor die opposite the frontside. The adjustable component is then trimmed through the backside of the semiconductor die.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: April 30, 2019
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Dirk Robert Walter Leipold, Julio C. Costa, Baker Scott
  • Patent number: 10272671
    Abstract: A system for isolating a failed resistor in a liquid dispensing system including a fusible links described. The system includes drive circuitry to drive a voltage supply to a resistor. The fusible link is disposed between a field effect transistor (FET) and the resistor. The fusible link is to fuse apart upon failure of the resistor.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: April 30, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Stanley J. Wang, Terry McMahon, Mohammed S. Shaarawi, Donald W. Schulte
  • Patent number: 10269704
    Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
  • Patent number: 10262939
    Abstract: Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Shin-Puu Jeng, Shang-Yun Hou, Tzuan-Horng Liu, Shih-Wen Huang, Chun Hua Chang
  • Patent number: 10249357
    Abstract: A semiconductor device includes a substrate having a memory region and a peripheral region defined thereon, wherein the peripheral region comprises at least one transistor, the memory region comprises a plurality of memory cells, each memory cell comprises at least one gate structure and a capacitor structure, a mask layer disposed on the capacitor structure in the memory region, and a dielectric layer disposed on the substrate within the peripheral region, wherein a top surface of the dielectric layer is aligned with a top surface of the mask layer.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: April 2, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wen-Chin Lin, Jhih-Yuan Chen, Syue-Ren Wu, Meng-Hsun Wu
  • Patent number: 10242944
    Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 10242945
    Abstract: A semiconductor die including a substrate, a device layer over the substrate, and an adjustable component in the device layer is provided, where a surface of the device layer opposite the substrate is the frontside of the semiconductor die. At least a portion of the substrate is removed to expose a backside of the semiconductor die opposite the frontside. The adjustable component is then trimmed through the backside of the semiconductor die.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: March 26, 2019
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Dirk Robert Walter Leipold, Julio C. Costa, Baker Scott
  • Patent number: 10230003
    Abstract: A method of evaluating a thin-film transistor (TFT) which is disposed on a substrate, and includes at least: an oxide semiconductor layer which functions as a channel layer; and a channel protection layer disposed above the oxide semiconductor layer. The method includes: measuring a change in a reflectance of a microwave emitted to the oxide semiconductor layer while the oxide semiconductor layer is irradiated with excitation light by pulse irradiation; calculating a decay period which is a period of time taken for the reflectance to decay to 1/e or 1/e2, based on the change in the reflectance obtained in the measuring; and performing determination related to a threshold voltage of the oxide semiconductor layer, based on the decay period calculated in the calculating.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: March 12, 2019
    Assignee: JOLED INC.
    Inventors: Eiji Takeda, Toru Saito
  • Patent number: 10229878
    Abstract: A semiconductor device includes an insulating film formed to cover an electric fuse (EF1), an insulating film (IL1), an insulating film (IL2), an electric fuse (EF1), an insulating film (IL1), and an insulating film (IL2). The electric fuse (EF1) includes a fuse-blowing portion (FC1), a first pad portion (PD1), and a second pad portion (PD2). The fuse-blowing portion (FC1) is formed between the first pad portion (PD1) and the second pad portion (PD2) in a first direction and is a rectangular shape having a first short side and a second short side along a second direction perpendicular to the first direction. The insulating film (IL1) is formed continuously between the first short side and the second short side to cover the surface of the fuse-blowing portion (FC1). The insulating film (IL2) is formed to planarly surround the insulating film (IL1) and is arranged at an interval from the insulating film (IL1).
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: March 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshihiro Nomura
  • Patent number: 10186589
    Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: January 22, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroyuki Tomomatsu, Hiroshi Yamasaki, Sameer Pendharkar
  • Patent number: 10177088
    Abstract: An antifuse structure including an opening through a dielectric material to a contact surface and an antifuse material layer present within the opening. The antifuse material layer may be a phase change material alloy of tantalum and nitrogen, wherein at least a base surface of the antifuse material layer is present on the contact surface and sidewall surfaces of the antifuse material layer are present on sidewalls of the opening through the dielectric material. An airgap or solid material core may be in the opening atop the base surface of the phase change material alloy. An electrically conductive material may be in direct contact with at least the antifuse material layer.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10168299
    Abstract: A method for forming a nanogap includes forming a knockoff feature on a dielectric layer and forming a trench in the dielectric layer on opposite sides of the knockoff feature. A noble metal is deposited in the trenches and over the knockoff feature. A top surface is polished to level the noble metal in the trenches with a top of the dielectric layer to form electrodes in the trenches and to remove the noble metal from the knockoff feature. A nanochannel is etched into the dielectric layer such that the knockoff feature is positioned within the nanochannel. The knockoff feature is removed to form a nanogap between the electrodes.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adam M. Pyzyna, Joshua T. Smith, Benjamin H. Wunsch
  • Patent number: 10159150
    Abstract: The present disclosure is directed to a ceramic substrate that includes a plurality of contact pads, a plurality of electrical traces, and a microelectromechanical die. Contacts on the die are coupled to the plurality of contact pads through the plurality of electrical traces. The substrate also includes a plurality of memory bits formed directly on the substrate. Each memory bit is coupled between a first one of the contact pads and a second one of the contact pads.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: December 18, 2018
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS S.R.L.
    Inventors: Simon Dodd, Roberto Brioschi
  • Patent number: 10153298
    Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jie Sun, Fatma Arzum Simsek-Ege
  • Patent number: 10141320
    Abstract: A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate. The method further includes converting the second material to a resistive material. The layers that include the resistive material form one or more electrical fuses.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni