Including Programmable Passive Component (e.g., Fuse) Patents (Class 257/529)
  • Patent number: 11171087
    Abstract: The present disclosure provides a semiconductor structure employing an antifuse structure and a controlling method of the semiconductor structure. The semiconductor structure includes a semiconductor substrate, a transistor and an antifuse structure. The transistor is disposed on the semiconductor substrate. The antifuse structure is disposed on the semiconductor substrate and adjacent to the transistor. The antifuse structure includes a first conductive portion, a fusible portion and a second conductive portion. The first conductive portion is disposed in the semiconductor substrate. The fusible portion is disposed on the first conductive portion. The second conductive portion is disposed on the fusible portion. The antifuse structure encloses the transistor in a top view.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: November 9, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11152568
    Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Fa-Shen Jiang
  • Patent number: 11145380
    Abstract: Memory cells and methods of forming and operating the same include forming a doped crystalline semiconductor memory layer on a first electrode. The doped crystalline semiconductor memory layer has a programmable dopant activation level that determines a resistance of the doped crystalline semiconductor memory layer. A second electrode is formed on the doped crystalline semiconductor memory layer.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heng Wu, Tenko Yamashita, Oleg Gluschenkov, Alexander Reznicek
  • Patent number: 11147197
    Abstract: Embodiments may relate to a material to provide electrostatic discharge (ESD) protection in an electrical device. The material may include first and second electrically-conductive carbon allotropes. The material may further include an electrically-conductive polymer that is chemically bonded to the first and second electrically-conductive carbon allotropes such that an electrical signal may pass between the first and second electrically-conductive carbon allotropes. Other embodiments may be described or claimed.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Veronica Aleman Strong, Johanna M. Swan, Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid
  • Patent number: 11107764
    Abstract: Group III-V semiconductor fuses and their methods of fabrication are described. In an example, a fuse includes a gallium nitride layer on a substrate. An oxide layer is disposed in a trench in the gallium nitride layer. A first contact is on the gallium nitride layer on a first side of the trench, the first contact comprising indium, gallium and nitrogen. A second contact is on the gallium nitride layer on a second side of the trench, the second side opposite the first side, the second contact comprising indium, gallium and nitrogen. A filament is over the oxide layer in the trench, the filament coupled to the first contact and to the second contact wherein the filament comprises indium, gallium and nitrogen.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Tristan A. Tronic, Rajat K. Paul
  • Patent number: 11101213
    Abstract: An eFuse structure including a semiconductor substrate; back end of the line (BEOL) metallization levels on the semiconductor substrate; vias extending through the metallization levels; at least one of the metallization levels including one or more metallic plates in electrical contact with one of the vias, the one or more metallic plates having at least one fusible link in electrical contact with one or more additional vias. The eFuse structure may form a multi-fuse structure such that each fusible link may be fused separately or together at the same time.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Chih-Chao Yang, Jim Shih-Chun Liang, Tian Shen
  • Patent number: 11089689
    Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region 308 within the conductive structure. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 2, 2016
    Date of Patent: August 10, 2021
    Assignee: INTEL CORPORATION
    Inventors: Eric Li, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
  • Patent number: 11075183
    Abstract: A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Ik Lee, Dong-Wan Kim, Seokho Shin, Jung-Hoon Han, Sang-Oh Park
  • Patent number: 11031689
    Abstract: A rapid testing read out integrated circuit (ROIC) includes phase-change material (PCM) radio frequency (RF) switches residing on an application specific integrated circuit (ASIC). Each PCM RF switch includes a PCM and a heating element transverse to the PCM. The ASIC is configured to provide amorphizing and crystallizing electrical pulses to a selected PCM RF switch. The ASIC is also configured to determine if the selected PCM RF switch is in an OFF state or in an ON state. In one implementation, a testing method using the ASIC is disclosed.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 8, 2021
    Assignee: Newport Fab, LLC
    Inventors: David J. Howard, Gregory P. Slovin, Nabil Ei-Hinnawy
  • Patent number: 11011462
    Abstract: The present disclosure relates to a semiconductor device. A fuse layer is arranged within a first dielectric layer. A bond pad is arranged on the first dielectric layer. A second dielectric layer is arranged along sidewall and upper surfaces of the bond pad. A passivation layer is arranged over the first and second dielectric layers, and the passivation layer having a bond pad opening overlying the bond pad and a fuse opening overlying the fuse layer. The bond pad has a bottom surface that is co-planar with a bottom surface of the passivation layer.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Chun-Yi Yang, Chih-Hao Lin, Hong-Seng Shue, Ruei-Hung Jang
  • Patent number: 10962341
    Abstract: Techniques and architecture are disclosed for a system that includes a fuze at a leading end of a projectile body and a fuze setter configured to engage the fuze and to program the same prior to launch. The system, in one example, includes a plurality of electrical contact pads on an exterior surface of a fuze radome housing and a plurality of electrical contact pins on the fuze setter. The electrical contact pads are arranged in a rotationally symmetric pattern that enables an electrical interface to be formed with the electrical contact pins, regardless of the rotational orientation of the fuze. Commutation is performed to rotate signals to the electrical contact pins instead of requiring that the fuze be physically rotated to bring the electrical contact pads into alignment with the electrical contact pins.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: March 30, 2021
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Francis M. Feda, John R. Franzini, Gregory S. Notaro
  • Patent number: 10957642
    Abstract: A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse electrical contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Chih-Chao Yang, Miaomiao Wang, Donald Francis Canaperi
  • Patent number: 10935590
    Abstract: A semiconductor wafer includes a semiconductor substrate having a plurality of die areas separated from one another by dicing areas. Each die area includes one or more metal layers above the semiconductor substrate and a plurality of fuse structures formed in at least one of the one or more metal layers. Each fuse structure includes a fuse area between first and second fuse heads. Each die area also includes a first pair of contacts connected to different areas of the first fuse head of at least some of the fuse structures. The wafer can be singulated along the dicing areas into individual dies. A corresponding method of fuse verification is also provided.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: March 2, 2021
    Assignee: Infineon Technologies AG
    Inventors: Dietrich Bonart, Thomas Gross, Franziska Haering
  • Patent number: 10937759
    Abstract: This disclosure relates to a radio frequency (RF) transmission line for high performance RF applications. The RF transmission line includes a bonding layer having a bonding surface and configured to receive an RF signal, a barrier layer proximate the bonding layer, a diffusion barrier layer proximate the bonding layer and configured to prevent contaminant from entering the bonding layer, and a conductive layer proximate the diffusion barrier layer. The diffusion barrier layer has a thickness that allows the received RF signal to penetrate the diffusion barrier layer to the conductive layer. The diffusion barrier layer can be a nickel layer.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: March 2, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Sandra Louise Petty-Weeks, Guohao Zhang, Hardik Bhupendra Modi
  • Patent number: 10916501
    Abstract: Techniques facilitating back end of line electrical fuse structure and method of fabrication are provided. A device can comprise a first metal interconnect formed in a dielectric layer of a semiconductor chip. The device can also comprise a second metal interconnect formed in the dielectric layer and adjacent to the first metal interconnect. Further, the device can comprise a vertical electrical fuse element comprising a first portion of a conductive material deposited on a first surface of the first metal interconnect and a second portion of the conductive material deposited on a second surface of the second metal interconnect. The vertical electrical fuse element can comprise a first region comprising a first thickness and a second region comprising a second thickness different than the first thickness.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10916500
    Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a silicon pattern for a fuse element, a metal silicide layer formed on an upper surface and a side surface of the silicon pattern, a gate electrode for MISFET, and a metal silicide layer formed on an upper surface of the gate electrode. The height from the lower surface of the silicon pattern to the lower end of the metal silicide layer is lower than the height from the lower surface of the gate electrode to the lower end of the metal silicide layer.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 9, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomohiko Aika, Takayuki Igarashi, Takehiro Ochi
  • Patent number: 10910308
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: February 2, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: John J. Pekarik, Anthony K. Stamper, Vibhor Jain
  • Patent number: 10903162
    Abstract: A method for fabricating an electronic fuse includes forming a recess within a film material to define opposed contact segments and a central fuse segment interconnecting the contact segments and altering the material of the central fuse segment of the film material to increase electrical resistance characteristics of the central fuse segment. The central fuse segment may include defects such as voids created by directing a laser at the central fuse segment as a component of a laser annealing process. Alternatively, and or additionally, the central fuse segment may include dopants implementing via an ion implantation process to increase resistance characteristics of the central fuse segment.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Liying Jiang, Juntao Li, Chih-Chao Yang, Michael Rizzolo, Yi Song
  • Patent number: 10886216
    Abstract: The present disclosure provides an electric fuse structure and a manufacturing method therefor, the manufacturing method including providing a substrate, forming a polysilicon corresponding to the electric fuse structure on the substrate, performing a source-drain ion implantation of a first doping type on the polysilicon, performing a source-drain ion implantation of a second doping type on the polysilicon, the first doping type being different from the second doping type, and forming a metal salicide on the surface of the doped polysilicon. The electric fuse structure manufactured according to the manufacturing method provided in the present disclosure has a high post-value resistance, so that a programming current window is effectively optimized, and the manufactured electric fuse structure has a uniform internal interface and good electrical characteristics.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 5, 2021
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT MFG. CO., LTD.
    Inventors: Yanwei Zhang, Runling Li, Tianpeng Guan
  • Patent number: 10867945
    Abstract: A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: December 15, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto
  • Patent number: 10868239
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: 10840049
    Abstract: Fuse programming circuits, devices and methods. In some embodiments, a fuse circuit can include a fuse pad configured to receive a voltage, a fuse having a first end coupled to the fuse pad and a second end coupled to a switching element configured to enable a current to pass from the fuse pad to a ground potential.
    Type: Grant
    Filed: July 15, 2018
    Date of Patent: November 17, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: Bo Zhou
  • Patent number: 10811354
    Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems associated with a fuse array of an integrated circuit. An integrated circuit may include a first metallization layer including a plurality of trenches separated by an interlayer dielectric (ILD), wherein the ILD forms a protrusion that extends above a top surface of the trenches. An etch stop layer may be disposed on the first metallization layer. The integrated circuit may further include a fuse disposed on the etch stop layer, wherein the fuse includes a fuse channel coupled between an anode and a cathode, wherein the fuse channel is disposed directly above the protrusion and is in contact with the etch stop layer. The integrated circuit may additionally or alternatively include one or more dummy regions adjacent to the fuse channel and separated from the fuse channel by a dielectric material. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Gwang-Soo Kim, Doug B. Ingerly
  • Patent number: 10784195
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Xiaoqiang Zhang, Haizhou Yin, Moosung M. Chae, Jinping Liu, Hui Zang
  • Patent number: 10775631
    Abstract: According to various embodiments, an electronic device includes: a housing including: a first plate; a second plate facing a direction opposite a direction of the first plate; and a sidewall surrounding a first space between the first plate and the second plate, the first space being a sealed space; and at least one electronic component arranged in the first space of the housing, wherein at least a part of the sidewall of the housing includes a moisture induction portion configured to induce moisture in the first space to be generated in a moisture induction region of the moisture induction portion that may be due, for example, to a difference in temperature between the first space and an external environment.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sukjin Yun, Seunghoon Kang, Kyeongsoo Kim, Jaecheon Kim, Hongki Moon, Yoonsun Park, Hyunjin Bai, Jaewook Jeong, Seungbo Hong, Jiseong Hwang
  • Patent number: 10770393
    Abstract: Back end of the line precision resistors that allow for high currents and for configuration as an eFuse by embedding a single thin film high resistive metal material within a dielectric layer, wherein the resisters are coupled to sidewalls of adjacent metal interconnects are described. The resistors can be formed in the metal one (M1) dielectric layer and can be coupled to sidewalls of the M1 interconnects. Also described are processes for fabricating integrated circuits including the resistors and/or e-Fuses.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew Tae Kim, Baozhen Li, Ernest Y. Wu, Chih-Chao Yang
  • Patent number: 10756082
    Abstract: A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song
  • Patent number: 10727181
    Abstract: A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Jae-Hong Kim, Seo-Woo Nam
  • Patent number: 10727116
    Abstract: Electronic device manufacturing and configuration methods include performing an additive deposition process that deposits a conductive, resistive, magnetic, semiconductor and/or thermally conductive material over a surface of a processed wafer metallization structure to set or adjust a circuit of a capacitor, an inductor, a resistor, an antenna and/or a thermal component of the metallization structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Paul Merle Emerson, Benjamin Stassen Cook
  • Patent number: 10720488
    Abstract: Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mattias Erik Dahlström, Li Jen Choi
  • Patent number: 10714200
    Abstract: A method for programming an electrically programmable fuse is disclosed. As conductive medium of the electrically programmable fuse exhibits different physical changes under different conditions, the conductive medium is changed from an initial physical state to a first physical state by using a first programming condition to program the electrically programmable fuse from a low resistance state to a medium resistance state, and the conductive medium is changed from the initial physical state or the first physical state to a second physical state by using a second programming condition to program the electrically programmable fuse from the low resistance state or the medium resistance state to a high resistance state. Transitions of three information storage states are achieved through two different programming conditions, so that the information storage density and chip area utilization rate of an electrically programmable fuse device can be significantly improved, and chip size reduction is facilitated.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 14, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuilong Yu, Kun Han
  • Patent number: 10629429
    Abstract: Methods and apparatuses for selectively depositing silicon oxide on a silicon oxide surface relative to a silicon nitride surface are described herein. Methods involve pre-treating a substrate surface using ammonia and/or nitrogen plasma and selectively depositing silicon oxide on a silicon oxide surface using alternating pulses of an aminosilane silicon precursor and an oxidizing agent in a thermal atomic layer deposition reaction without depositing silicon oxide on an exposed silicon nitride surface.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Lam Research Corporation
    Inventors: David Charles Smith, Dennis M. Hausmann
  • Patent number: 10619266
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate is provided. A pad metal and a fuse metal are formed on the substrate. A liner is formed on the pad metal and on the fuse metal. An etching stop layer is formed on the portion of the liner on the fuse metal. A dielectric layer and a passivation layer are formed on the liner and on the etching stop layer. After defining a pad opening and a fuse opening in the passivation layer, a first etching step is performed to remove the dielectric layer from the pad opening and the fuse opening until the pad metal and the etching stop layer are exposed. Afterward, a second etching step is performed to remove the exposed etching stop layer from the fuse opening until the liner on the fuse metal is exposed.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: April 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ming-Feng Kuo
  • Patent number: 10622319
    Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekta Misra, Krishna R. Tunga
  • Patent number: 10615119
    Abstract: Techniques facilitating back end of line electrical fuse structure and method of fabrication are provided. A device can comprise a first metal interconnect formed in a dielectric layer of a semiconductor chip. The device can also comprise a second metal interconnect formed in the dielectric layer and adjacent to the first metal interconnect. Further, the device can comprise a vertical electrical fuse element comprising a first portion of a conductive material deposited on a first surface of the first metal interconnect and a second portion of the conductive material deposited on a second surface of the second metal interconnect. The vertical electrical fuse element can comprise a first region comprising a first thickness and a second region comprising a second thickness different than the first thickness.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10607934
    Abstract: A fuse of a semiconductor device may include: a fuse link suitable for extending in a first direction and connecting first and second electrodes; a dummy strip suitable for extending in the first direction, and with a predetermined distance from the fuse link in a second direction perpendicular to the first direction; and an air channel formed between the fuse link and the dummy strip to contact with the fuse link.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 31, 2020
    Assignees: SK hynix Inc., INDUSTRY-ACAMEDIA COOPERATION GROUP OF SEJONG UNIVERSITY
    Inventors: Deok-Kee Kim, Jae Hong Kim, Seo Woo Nam
  • Patent number: 10600902
    Abstract: A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: March 24, 2020
    Assignee: Vishay Siliconix, LLC
    Inventor: Robert Xu
  • Patent number: 10597321
    Abstract: Processes of chamfering and/or beveling an edge of a glass substrate of arbitrary shape using lasers are described herein. Two general methods to produce chamfers on glass substrates are the first method involves cutting the edge with the desired chamfer shape utilizing an ultra-short pulse laser to create perforations within the glass; followed by an ion exchange.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: March 24, 2020
    Assignee: Corning Incorporated
    Inventors: Sasha Marjanovic, David Andrew Pastel, Garrett Andrew Piech, Jose Mario Quintal, Helmut Schillinger, Sergio Tsuda, Robert Stephen Wagner, Andrea Nichole Yeary
  • Patent number: 10586799
    Abstract: A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate. The method further includes converting the second material to a resistive material. The layers that include the resistive material form one or more electrical fuses.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Patent number: 10586855
    Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: March 10, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Hyun-Jin Cho, Tenko Yamashita, Hui Zang
  • Patent number: 10553535
    Abstract: A method for fabricating a semiconductor device including an electrically programmable fuse includes patterning dielectric material formed on a first electrode including a first conductive material to create one or more openings, and forming second conductive material within the one or more openings. Forming the second conductive material includes forming one or more voids encapsulated by the second conductive material such that the one or more voids have boundaries defined in part by portions of the second conductive material disposed between the one or more voids and the dielectric material. The portions of the second conductive material correspond to fuse links.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Chih-Chao Yang
  • Patent number: 10546822
    Abstract: A seal ring structure of an integrated circuit including a first discontinuous seal wall circumscribing a first portion of the integrated circuit, the first seal wall forming a first pattern on a substrate, and a second discontinuous seal wall circumscribing a second portion of the integrated circuit, the second seal wall forming a second pattern on the substrate and the second portion being at least partially offset from the first portion, wherein the first pattern of the first seal wall interlocks with the second pattern of the second seal wall such that the patterns are interweaved without intersecting, wherein a space is formed between the seal walls, the space creating a non-linear path to the integrated circuit, and wherein the seal ring structure fully circumscribes the integrated circuit. A method of forming such a seal ring structure is also disclosed.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: January 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas A. Polomoff, Vincent J. McGahay
  • Patent number: 10515852
    Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element electrically connected to the conductive feature. A first portion of the resistive element is over the dielectric layer, and a second portion of the resistive element extends towards the conductive feature.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Sheh Huang, Hsiu-Wen Hsueh, Yu-Hsiang Chen, Chii-Ping Chen
  • Patent number: 10504997
    Abstract: A semiconductor structure includes a substrate and a silicon-germanium (SiGe) fin formed on the substrate. The SiGe fin has a first portion having a first doping profile and a second portion having a second doping profile. The first portion of the SiGe fin has a Si-rich outer surface.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki, Koji Watanabe
  • Patent number: 10497700
    Abstract: An anti-fuse for a semiconductor device includes an electrode; a gate metal formed to extend from the electrode; a gate oxide layer formed under the gate metal; a semiconductor layer formed under the gate oxide layer to overlap with a center portion of the gate metal; and a first oxide layer formed under the gate metal and the gate oxide layer and on both sides of the semiconductor layer.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: December 3, 2019
    Assignees: SK hynix Inc., INDUSTRY-ACADEMIA COOPERATION GROUP OF SEJONG UNIVERSITY
    Inventors: Deok-kee Kim, Honggyun Kim, Jae Hong Kim, Seo Woo Nam
  • Patent number: 10472731
    Abstract: A method of forming a semiconductor structure is disclosed. A substrate is provided with a pad metal and a fuse metal formed thereon. A liner and an etching stop layer are formed at least covering a top surface of the fuse metal. A dielectric layer is formed on the substrate and a passivation layer is formed over the dielectric layer. A pad opening and a fuse opening are defined in the passivation layer. A first etching step is performed to remove the dielectric layer from the pad opening and the fuse opening to expose a top surface of the pad metal from the pad opening and an upper surface of the etching stop layer from the fuse opening respectively. A second etching step is performed to remove the etching stop layer from the fuse opening until an upper surface of the liner is exposed.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ming-Feng Kuo
  • Patent number: 10453792
    Abstract: A semiconductor device including an anti-fuse is disclosed. The semiconductor anti-fuse includes a highly doped source of a first conductivity type overlying a substrate. The semiconductor anti-fuse further includes a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate. The semiconductor anti-fuse further includes a highly doped fuse region extending over the highly doped source and including an epitaxial growth, the highly doped fuse region implanted with ions.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Pouya Hashemi, Miaomiao Wang, Takashi Ando
  • Patent number: 10424521
    Abstract: A method includes fabricating a set of die in a production run, each die comprising a set of pads at a periphery of a top metal layer, a first set of fuse elements, and a second set of fuse elements. Each fuse element of the first set of fuse elements couples a corresponding pad of the set to a corresponding bus when in a conductive state, and each fuse element of the second set couples a corresponding subset of pads of the set together when in a conductive state. The method further includes selecting a subset of the die of the production run for testing, and configuring each die of the subset for testing by placing each fuse element of the first set in a non-conductive state and placing each fuse element of the second set in a conductive state.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: September 24, 2019
    Assignee: NXP USA, INC.
    Inventor: George R. Leal
  • Patent number: 10381585
    Abstract: A thin film transistor includes a gate electrode, a insulating medium layer and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating medium layer. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating medium layer. The semiconducting structure includes a carbon nanotube structure. The second electrode is located on the second end.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 13, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Yuan-Hao Jin, Tian-Fu Zhang, Qun-Qing Li
  • Patent number: 10374180
    Abstract: A thin film transistor includes a gate, an insulating medium layer and a Schottky diode. The Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode is located on the surface of the insulating medium layer and includes a first metal layer and a second metal layer. The second electrode is located on the surface of the insulating medium layer and includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure includes a carbon nanotube structure.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 6, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Yuan-Hao Jin, Tian-Fu Zhang, Qun-Qing Li