Including Inductive Element Patents (Class 257/531)
  • Patent number: 10741651
    Abstract: A terminal structure of an insulated gate bipolar transistor (IGBT) device includes a main junction, a cutoff ring, and a plurality of terminal rings disposed between the main junction and the cutoff ring, and a resistive element having a first terminal electrically connected to the main junction, a second terminal electrically connected to the cutoff ring, and a plurality of intermediate terminals electrically connected to the terminal rings, respectively. The resistive element is configured to uniformly distribute the lateral voltage between the main junction and the cutoff ring to the terminal rings to ensure that the peak electric field is uniformly distributed across the terminal structure, thereby reducing the terminal structure area and package cost of the IGBT device, while improving the device reliability.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 11, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Jian Liu
  • Patent number: 10734156
    Abstract: An inductor component including an inductor electrode includes an insulating layer and an outer electrode for external connection formed on the upper surface of the insulating layer. The inductor electrode includes a metal pin for input/output that has an upper end surface connected to the outer electrode and that is embedded in the insulating layer. The outer electrode includes a base electrode formed on the upper surface of the insulating layer and composed of a conductive paste, and a surface electrode formed on the base electrode by plating. The surface electrode is formed such that the area of a cross section thereof perpendicular to the thickness direction on an outer layer side away from the base electrode is larger than the area of a cross section thereof perpendicular to the thickness direction on an inner layer side close to the base electrode.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: August 4, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Shinichiro Banba, Mitsuyoshi Nishide, Norio Sakai
  • Patent number: 10734331
    Abstract: In a described example, an integrated circuit includes: a semiconductor substrate having a first surface and an opposite second surface; at least one dielectric layer overlying the first surface of the semiconductor substrate; at least one inductor coil in the at least one dielectric layer with a plurality of coil windings separated by coil spaces, the at least one inductor coil lying in a plane oriented in a first direction parallel to the first surface of the semiconductor substrate, the at least one inductor coil electrically isolated from the semiconductor substrate by a portion of the at least one dielectric layer; and trenches extending into the semiconductor substrate in a second direction at an angle with respect to the first direction, the trenches underlying the inductor coil and filled with dielectric replacement material.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Barry Jon Male, Rajarshi Mukhopadhyay
  • Patent number: 10720411
    Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Tetsuya Iida
  • Patent number: 10720487
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an etch stop layer over a semiconductor substrate and forming a magnetic element over the etch stop layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes forming a conductive line over the isolation element. In addition, the method includes forming a dielectric layer over the conductive line, the isolation element, and the magnetic element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Chi-Cheng Chen, Hon-Lin Huang, Wei-Li Huang, Chun-Yi Wu, Chen-Shien Chen
  • Patent number: 10713646
    Abstract: A portable communication device is provided. The portable communication device includes near field communication (NFC) circuitry; wireless charging circuitry; magnetic secure transmission (MST) circuitry; a flexible printed circuit board (FPCB) including a first substrate layer and a second substrate layer; an NFC coil electrically connected with the NFC circuitry, the NFC coil including a first portion formed on the first substrate layer and a second portion formed on the second substrate layer; a wireless charging coil electrically connected with the wireless charging circuitry, the wireless charging coil including a third portion formed on the first substrate layer and a fourth portion formed on the second substrate layer; and an MST coil electrically connected with the MST circuitry, the MST coil including a fifth portion formed on the first substrate layer and a sixth portion formed on the second substrate layer.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hee-Dong Lee, Chul-Hyung Yang, Ji-Woo Lee
  • Patent number: 10714410
    Abstract: A semiconductor structure including a substrate, a first well, a field oxide layer, a first conductive line and a second conductive line is provided. The substrate has a first conductivity type. The first well is formed on the substrate and has a second conductivity type. The field oxide layer is disposed on the first well. The first conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The second conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The first conductive line is spaced apart from the second conductive line.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: July 14, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Hsiao-Ling Chiang, Wen-Hsin Lin
  • Patent number: 10706993
    Abstract: A chip part is provided that includes a substrate in which an element region and an electrode region are set, an insulating film (a first insulating film and a second insulating film) which is formed on the substrate and which selectively includes an internal concave/convex structure in the electrode region on a surface, a first connection electrode and a second connection electrode which include, at a bottom portion, an anchor portion entering the concave portion of the internal concave/convex structure and which include an external concave/convex structure on a surface on the opposite side and a circuit element which is disposed in the element region and which is electrically connected to the first connection electrode and the second connection electrode.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 7, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Takuma Shimoichi, Yasuhiro Kondo, Keishi Watanabe, Takamichi Torii, Katsuya Matsuura
  • Patent number: 10700161
    Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 30, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin
  • Patent number: 10700159
    Abstract: A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel IP Corporation
    Inventors: Veronica Sciriha, Georg Seidemann
  • Patent number: 10699266
    Abstract: An electronic device is provided. The electronic device includes a housing; a plurality of coils that are disposed on a first layer within the housing; a plurality of other coils disposed on a second layer substantially parallel to the first layer; a first conductor that connects an end point of a first coil of the plurality of coils and a start point of a second coil of the plurality of other coils and conducts a current from the end point of the first coil to the start point of the second coil; and a second conductor that connects a start point of a third coil adjacent to an outer side of the first coil of the plurality of coils and an end point of the second coil and conducts the current to be applied from the end point of the second coil to the start point of the third coil, wherein the first conductor and the second conductor induce a directional magnetic field when the current flows.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hee-Dong Lee, Chul-Hyung Yang, Ji-Woo Lee
  • Patent number: 10692808
    Abstract: In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 23, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Renukprasad Hiremath, Hyeokjin Lim, Foua Vang, Xiangdong Chen, Venugopal Boynapalli
  • Patent number: 10685911
    Abstract: The present disclosure provides a semiconductor package, including a first semiconductor structure, a first bonding dielectric over the first semiconductor structure and surrounding a first bonding metallization structure, a through via over the first bonding dielectric, and a passive device passive device electrically coupled to the through via and the first bonding metallization structure. The present disclosure also provides a method for manufacturing a semiconductor package, including providing a first die, bonding a second die with the first die, wherein the second die partially covers the first die thereby forming a gap over an uncovered portion of the first die, filling the gap over the first die with dielectric, forming a through dielectric via (TDV) in the filled gap, and forming a passive device over the second die and the TDV.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Chen-Hua Yu
  • Patent number: 10672860
    Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
  • Patent number: 10671204
    Abstract: Provided is a novel touch panel that is highly convenience or reliable, a novel data processor that is highly convenient or reliable, a novel touch panel, a novel data processor, or a novel semiconductor device. The touch panel includes a sensor element and a display element. The sensor element includes a first conductive film and a second conductive film. The display element includes a layer containing a liquid crystal material and a third conductive film which is provided so that an electric field controlling the alignment of the liquid crystal material contained in the layer can be applied between the first conductive film and the third conductive film.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: June 2, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroyuki Miyake
  • Patent number: 10658973
    Abstract: Techniques for co-tuning of inductance (L) and capacitance (C) in a VNCAP-based LC tank oscillator are provided. In one aspect, an LC tank oscillator includes: a capacitor including at least two metal layers, each metal layer having metal fingers that are interdigitated, wherein an orientation of the metal fingers alternates amongst the at least two metal layers; and an inductor on the capacitor. Inter-layer vias can be present interconnecting the at least two metal layers creating conductive loops between the metal fingers, wherein an arrangement of the inter-layer vias in an area between the at least two metal layers is configured to co-tune both inductance and capacitance in the LC tank oscillator. A method of operating an LC tank oscillator and a method of co-tuning inductance and capacitance in an LC tank oscillator are also provided.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Zheng Xu, Hung Tran, Qianwen Chen, Ruqiang Bao
  • Patent number: 10637528
    Abstract: An inductor circuit includes first inductive circuit, second inductive circuit, and third inductive circuit. First inductive circuit at receiver side has a first end coupled to a first port of an antenna and a second end coupled to an input port of a receiving circuit. Second inductive circuit at transmitter side has a first end and a second end respectively coupled to output ports of a power amplifier. Third inductive circuit at antenna side has a first end coupled to a first port of the antenna and having a second end. Second inductive circuit and the third inductive circuit are disposed on an outer ring to form a ring shape and the third inductive circuit is disposed on an inner ring within the outer ring to form a spiral shape. Third inductive circuit is disposed between the second inductive circuit and the first inductive circuit.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: April 28, 2020
    Assignee: Audiowise Technology Inc.
    Inventor: Wen-Shun Liu
  • Patent number: 10609813
    Abstract: Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, Fern Nee Tan, Khang Choong Yong, Jiun Hann Sir
  • Patent number: 10601222
    Abstract: A T-coil IC includes a first inductor on an Mx layer. The first inductor has n turns, where n is at least 1? turns. The T-coil IC further includes a second inductor on an Mx?1 layer. The second inductor has n turns. The first inductor and the second inductor are connected together at a node. The first inductor on the Mx layer and the second inductor on the Mx?1 layer are mirror symmetric to each other. The T-coil IC further includes a center tap on an Mx?2?y layer, where y?0. The center tap is connected to the first inductor and the second inductor by a via stack at the node. In one configuration, n is 1?+0.5z turns, where z?0. An effective bridge capacitance of the T-coil IC may be approximately 25 fF.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Siqi Fan
  • Patent number: 10600565
    Abstract: The manufacture method of a coil component includes the steps of bonding a dummy metal layer onto one face of a mounting base, stacking a base insulating resin on the dummy metal layer, stacking a first spiral wiring and a first insulating resin in this order on the base insulating resin to cover the first spiral wiring with the first insulating resin and stacking a second spiral wiring and a second insulating resin in this order on the first insulating resin to cover the second spiral wiring with the second insulating resin to thereby form a coil substrate, detaching the mounting base from the dummy metal layer in a bonding face between the one face of the mounting base and the dummy metal layer, removing the dummy metal layer from the coil substrate, and covering the coil substrate with a magnetic resin.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: March 24, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Akinori Hamada, Kenji Nishiyama, Shinji Yasuda
  • Patent number: 10592893
    Abstract: An electronic device is provided. The electronic device includes a housing; a plurality of coils that are disposed on a first layer within the housing; a plurality of other coils disposed on a second layer substantially parallel to the first layer; a first conductor that connects an end point of a first coil of the plurality of coils and a start point of a second coil of the plurality of other coils and conducts a current from the end point of the first coil to the start point of the second coil; and a second conductor that connects a start point of a third coil adjacent to an outer side of the first coil of the plurality of coils and an end point of the second coil and conducts the current to be applied from the end point of the second coil to the start point of the third coil, wherein the first conductor and the second conductor induce a directional magnetic field when the current flows.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co. Ltd
    Inventors: Hee-Dong Lee, Chul-Hyung Yang, Ji-Woo Lee
  • Patent number: 10593662
    Abstract: A protection device includes a semiconductor substrate including a protection element; an insulating layer covering a surface of the semiconductor substrate; a conductive layer disposed in the insulating layer, and extending in a plane that is parallel with the surface of the semiconductor substrate; a passive element formed with an elongated conductor, curved in a plane that is parallel with the conductive layer, and located over the conductive layer; and an input terminal, an output terminal, and a ground terminal exposed in a surface of the insulating layer. One end of the passive element is electrically connected to the input terminal, the other end of the passive element and a high-potential-side terminal of the protection element are electrically connected to the output terminal, and a low-potential-side terminal of the protection element and the conductive layer are electrically connected to the ground terminal.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: March 17, 2020
    Assignee: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO
    Inventors: Narumasa Soejima, Takashi Suzuki, Kengo Shima, Yosuke Kanie, Kazuya Adachi
  • Patent number: 10580568
    Abstract: A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: March 3, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10573457
    Abstract: An embedded transformer device includes first, second, and auxiliary windings, defined in an insulating substrate by conductive vias joined together by conductive traces. The positions of the conductive vias are arranged to optimize the isolation properties of the transformer and to reduce the coupling of the transformer by increasing the leakage inductance. The embedded transformer device provides better isolation between input side and output side windings, and allows an oscillating LC circuit to be set up in the case of a short circuit, preventing high power from extending between the input and output terminals and thereby avoiding damage to the connected electrical components.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: February 25, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Jing Wang, Quinn Kneller, Scott Parish
  • Patent number: 10554078
    Abstract: The disclosure relates to a method, apparatus and system to wirelessly charge a device. Specifically, the disclosed embodiments provide improved charging stations for increased active charging area. In one embodiment, the disclosure relates to an offset device for use with a Power Receiving Unit (PRU). The offset device includes a conductive layer supporting an aperture, the aperture aligned with an inner most coil loop of the PRU; and a first slot formed in the conductive layer extending from the aperture to an outside edge of the conductive layer.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Songnan Yang, Janardhan Koratikere Narayan, Ntsanderh C. Azenui, Ahmad Khoshnevis
  • Patent number: 10535547
    Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: January 14, 2020
    Assignee: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
  • Patent number: 10522531
    Abstract: An integrated circuit device is described. The integrated circuit device comprises a substrate having transmitter for receiving a signal to be transmitted to a receiver of the substrate by way of a transmission channel; a first plurality of contacts adapted to receive a first integrated circuit die, wherein a contact of the first plurality of contacts is adapted to receive the signal to be transmitted by the transmitter; a second plurality of contacts adapted to receive a second integrated circuit die, wherein a contact of the second plurality of contacts is adapted to receive the signal transmitted by the transmitter and received by the receiver; a first resistive element coupled between a contact of the first plurality of contacts and the transmitter; and a second resistive element coupled between a contact of the second plurality of contacts and the receiver. A method of transmitting data in an integrated circuit is also described.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 31, 2019
    Assignee: Xilinx, Inc.
    Inventor: James Karp
  • Patent number: 10523253
    Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 31, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Yun, Chengjie Zuo, Mario Velez, Niranjan Sunil Mudakatte, Shiqun Gu, Jonghae Kim, David Berdy
  • Patent number: 10523016
    Abstract: An apparatus is provided comprising: a first power domain that includes a first component that operates at a first voltage level; a second power domain that includes a media access controller (MAC) that operates at a second voltage level; and a third power domain that includes a physical media access (PHY) device that operates at a third voltage level; wherein the first voltage level is higher than the second voltage level; and wherein the second voltage level is unreferenced; further including: a first reinforced electrical isolation circuit disposed on a first circuit path that includes at least one signal lane that extends between the first power domain and the second power domain; and a second reinforced electrical isolation circuit disposed on a second circuit path that includes at least one signal lane that extends between the MAC device and the PHY device.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: December 31, 2019
    Assignee: Analog Devices Global
    Inventors: Stefan Hacker, Andreas Koch, Ralph Patrick McCormick
  • Patent number: 10515755
    Abstract: A coil electronic component includes: a plurality of stacked coil layers each including coil patterns including anisotropic plating layers; conductive vias connecting the coil patterns formed on different coil layers to each other; and external electrodes electrically connected to the plurality of coil layers.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: December 24, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ki Seok Kim, Ye Jeong Kim, Myung Sam Kang, Kwang Hee Kwon
  • Patent number: 10515753
    Abstract: A coil component includes a substrate and a coil portion disposed on at least one surface thereof. The coil portion includes a first coil pattern disposed on one surface of the substrate, a first insulating layer covering the first coil pattern and having a first surface facing the substrate and a second surface opposing the first surface, and an intermediate layer including third and fourth surfaces opposing each other, the third surface being disposed to face the second surface of the first insulating layer, and average surface roughness of the fourth surface being lower than that of the second surface. The coil portion further includes a second coil pattern disposed on the fourth surface of the intermediate layer and connected to the first coil pattern through a conductive via, and a second insulating layer disposed in a space between the fourth surface and the second coil pattern.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 24, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Byung Seung Min
  • Patent number: 10504784
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit having an inductor with one or more turns arranged along vertical planes that intersect an underlying substrate. In some embodiments, the integrated circuit includes a plurality of conductive routing layers having conductive wires and conductive vias disposed within one or more dielectric structures abutting a first substrate. The plurality of conductive routing layers define an inductor having one or more turns respectively including a vertically extending segment arranged along a plane that intersects the first substrate. The vertically extending segment has a plurality of the conductive wires and the conductive vias.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • Patent number: 10498564
    Abstract: A high-speed serial link receiver system, comprises: an input terminal for receiving a signal; a pi-coil including a first inductor, a second inductor, and a third inductor; a first electrostatic discharge device (“ESD”); a second ESD; an on-die-termination (“ODT”); and a receiver. The first inductor, the second inductor, and the third inductor are serially connected. The input terminal is coupled to the first inductor. A serial connection between the first inductor and the second inductor is coupled to the first ESD device. A serial connection between the second inductor and the third inductor is coupled to the ODT. The second ESD device and the receiver are coupled to the third inductor.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: December 3, 2019
    Assignee: Invecas, Inc.
    Inventors: Majid Jalali Far, Venkata N. S. N. Rao
  • Patent number: 10489544
    Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 26, 2019
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 10490621
    Abstract: Apparatus implementing various structures to decrease the distance between two inductive elements for tuning an inductance with greater variability (a wider tuning range). One example integrated circuit (IC) package generally includes a laminate, a solder resist layer disposed on an upper surface of the laminate, and a semiconductor die disposed above the laminate and comprising a first inductor. At least a portion of a second inductor is disposed above a section of the solder resist layer, the first inductor at least partially overlaps the second inductor, and there is a gap between the first inductor and the second inductor.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Paragkumar Ajaybhai Thadesar, Mario Francisco Velez, Changhan Hobie Yun, Francesco Carrara, Jonghae Kim, Xiaoju Yu, Niranjan Sunil Mudakatte
  • Patent number: 10483379
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 19, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Qingmin Liu, Gang Wang
  • Patent number: 10483199
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Igarashi, Takuo Funaya
  • Patent number: 10475755
    Abstract: A method of manufacturing a semiconductor structure includes providing a transceiver, forming a molding to surround the transceiver, forming a plurality of recesses extending through the molding, disposing a conductive material into the plurality of recesses to form a plurality of vias, disposing and patterning an insulating layer over the molding, the plurality of vias and the transceiver, and forming a redistribution layer (RDL) over the insulating layer, wherein the RDL comprises an antenna disposed over the insulating layer and a dielectric layer covering the antenna, and a portion of the antenna is extended through the insulating layer and is electrically connected with the transceiver.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Vincent Chen, Hung-Yi Kuo, Chuei-Tang Wang, Hao-Yi Tsai, Chen-Hua Yu, Wei-Ting Chen, Ming Hung Tseng, Yen-Liang Lin
  • Patent number: 10475745
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Yueli Liu, Qinglei Zhang, Amanda E. Schuckman, Rui Zhang
  • Patent number: 10475718
    Abstract: A semiconductor device package includes a dielectric layer, a first RDL, a second RDL, an inductor, a first electronic component and a second electronic component. The first RDL is adjacent to a first surface of the dielectric layer, and the first RDL includes first conductive pieces. The second RDL is adjacent to a second surface of the dielectric layer, and the second RDL includes second conductive pieces. The inductor is disposed in the dielectric layer. The inductor includes induction pillars, wherein each of the induction pillars is disposed through the dielectric layer, and each of the induction pillars is interconnected between a respective one of the first conductive pieces of the first RDL and a respective one of the second conductive pieces of the second RDL. The first electronic component and the second electronic component are between the first RDL and the second RDL, and electrically connected to each other through the inductor.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: November 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Hung-Yi Lin, Cheng-Yuan Kung, Teck-Chong Lee, Shiuan-Yu Lin
  • Patent number: 10468345
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shiang Liao, Chewn-Pu Jou
  • Patent number: 10446486
    Abstract: A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least substantially through the first die and a first substantially helical conductor disposed around the first TSV. The second die includes a second TSV coupled to the first TSV and a second substantially helical conductor disposed around the second TSV. The first substantially helical conductor is configured to induce a change in a magnetic field in the first and second TSVs in response to a first changing current in the first substantially helical conductor, and the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the second TSV.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kyle K. Kirby
  • Patent number: 10447204
    Abstract: The present disclosure describes aspects of a switchable inductor network for wideband circuits. In some aspects, the switchable inductor network provides selectable inductance. The switchable inductor network includes a first coil and a second coil that includes a first inductive segment and a second inductive segment. Connection points of the second coil connect the second coil across a portion of the first coil. The switchable inductor network also includes a switch connected between the first inductive segment and the second inductive segment of the second coil. The switch is configured to change the selectable inductance of the switchable inductor network by selectively coupling the first inductive segment to the second inductive segment of the second coil in response to a control signal.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: October 15, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Masoud Moslehi Bajestan, Mehran Mohammadi Izad, Mohammad Farazian
  • Patent number: 10446476
    Abstract: A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: October 15, 2019
    Assignee: NXP USA, Inc.
    Inventors: Leo M. Higgins, III, Fred T. Brauchler, Burton Jesse Carpenter, Jinmei Liu, Mariano Layson Ching, Jr., Jinzhong Yao, Xingshou Pang, Jianhong Wang, Yadong Wei
  • Patent number: 10446485
    Abstract: A semiconductor device includes: a plurality of first wires formed in a first layer and indicating fixed potentials; and an inductor formed in a second layer stacked on the first layer, and wiring widths of the first wires located within a range of a formation region of the inductor in a plan view among the plurality of first wires are formed narrower than wiring widths of the first wires located outside the range of the formation region of the inductor.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 15, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shinichi Uchida
  • Patent number: 10439018
    Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: October 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Hao-chieh Chan
  • Patent number: 10404091
    Abstract: A coil substrate for wireless power transmission includes: an insulating substrate including a first surface and a second surface; a first wiring portion disposed on the first surface, wherein the first wiring portion includes first spiral patterns and a section in which opposing ends of each of the first spiral patterns are disposed parallel to each other; a second wiring portion disposed on the second surface and including second spiral patterns, wherein opposing ends of each of the second spiral patterns are spaced apart from each other; and conductive vias alternately connecting the first spiral patterns and the second spiral patterns to each other to form coil turns.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: September 3, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ki Won Chang, Hyung Wook Cho, Dong Woo Han, Si Hyung Kim, Tae Seok Yang, Choon Hee Kim, Chang Mok Han, Taek Woo Kim
  • Patent number: 10395814
    Abstract: A coil electronic component includes: a plurality of stacked coil layers each including coil patterns including anisotropic plating layers; conductive vias connecting the coil patterns formed on different coil layers to each other; and external electrodes electrically connected to the plurality of coil layers.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ki Seok Kim, Ye Jeong Kim, Myung Sam Kang, Kwang Hee Kwon
  • Patent number: 10396045
    Abstract: An apparatus and a system including an apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side and an opposite second side; an inductor disposed on the second side of the structure; and a contact coupled to the inductor and routed through the device stratum and coupled to at least one of the plurality of transistor devices on the first side. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum including a first side and an opposite second side, wherein the second side is coupled to the substrate; removing a portion of the substrate; forming at least one inductor on the second side of the device stratum; and coupling the at least one inductor to at least one of the plurality of transistor devices.
    Type: Grant
    Filed: September 27, 2015
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Paul B. Fischer
  • Patent number: 10381316
    Abstract: The disclosure relates to a semiconductor package device. The semiconductor package device includes a substrate having a first surface and a second surface opposite to the first surface and including a first conductive contact. The semiconductor package device further includes an electronic component disposed on the first surface of the substrate. The semiconductor package device further includes a metal frame disposed on the first surface of the substrate. The semiconductor package device further includes an antenna disposed on the metal frame, wherein the antenna is electrically isolated from the metal frame and electrically connected to the first conductive contact of the substrate.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 13, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Liang Chung, Pei-Ling Li