Including Inductive Element Patents (Class 257/531)
  • Patent number: 11411068
    Abstract: A semiconductor package may include a substrate, including an inductor array including inductor structures, and a semiconductor chip and a voltage regulator each on the substrate. Each of the inductor structures may include an input terminal, an output terminal, a coil between the input terminal and the output terminal, and conductive wirings. The inductor structures may be apart from one another in a second horizontal direction. Each of the coils may include a lower horizontal winding wound horizontally, an upper horizontal winding wound horizontally, and a conductive via. In a plan view, the coils may be arranged in zigzags, and the coils and the conductive wirings may be alternately arranged in the second horizontal direction.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 9, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sangwook Park
  • Patent number: 11407201
    Abstract: A composite member (1) satisfies the following expressions. X/(E×|CTE(B)?CTE(A)|)?50, X/(E×|CTE(B)?CTE(C)|)?50, Y/|CTE(B)?CTE(A)|×L(BA)?50, and Y/|CTE(B)?CTE(C)|×L(BC)?50. X: shear bond strength (MPa) between the heat dissipating base substrate and heat generating member, Y: fracture elongation of the thermoconductive insulating adhesive film, E: modulus of elasticity (MPa) of the thermoconductive insulating adhesive film, CTE(A): linear expansion coefficient (° C.?1) of the heat dissipating base substrate, CTE(B): linear expansion coefficient (° C.?1) of the thermoconductive insulating adhesive film, CTE(C): linear expansion coefficient (° C.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 9, 2022
    Assignees: TOYO INK SC HOLDINGS CO., LTD., TOYOCHEM CO., LTD.
    Inventors: Toshiichi Sawaguchi, Naohiro Tanaka, Kaori Sakaguchi, Kenji Andou, Hidenobu Kobayashi
  • Patent number: 11404364
    Abstract: A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
  • Patent number: 11404389
    Abstract: Embodiments include one or more air core inductors (ACIs) and a method of forming the ACIs. The ACI includes a first inductor loop on a substrate. The first inductor loop has a first line and a second line. The first line has a first thickness that is greater than a second thickness of the second line. The ACI also includes a dielectric over the substrate and the first and second lines. The first line has a top surface above a top surface of the second line. The ACI further includes a second inductor loop on the dielectric and the first inductor loop. The second inductor loop has is coupled to the top surface of the first line of the first inductor loop. The first inductor loop may also have a third thickness, where the third thickness is the distance between the top surfaces of the first and second line.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Jeremy Ecton, Suddhasattwa Nad, Kristof Darmawikarta, Yonggang Li, Xiaoying Guo
  • Patent number: 11404360
    Abstract: In some examples, an electronic device comprises a first magnetic member, a first adhesive layer abutting the first magnetic member, a second magnetic member, a second adhesive layer abutting the second magnetic member, and a laminate member between the first and second adhesive layers. The laminate member comprises first and second transformer coils, an electromagnetic interference (EMI) shield coil, and a set of thermally conductive members coupled to the EMI shield coil and extending in three dimensions. At least some of the thermally conductive members extend vertically through a thickness of the laminate member so as to be exposed to top and bottom surfaces of the laminate member. The electronic device includes a thermally conductive component coupled to at least one thermally conductive member in the set of thermally conductive members.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: August 2, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Zhemin Zhang, Yi Yan, Hiep Xuan Nguyen
  • Patent number: 11387315
    Abstract: A patterned shielding structure is disposed between an inductor structure and a substrate. The patterned shielding structure includes a shielding layer. The shielding layer includes a first main portion and a plurality of branch portions. The first main portion is T-shaped. The branch portions are connected to the first main portion.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 12, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 11374555
    Abstract: In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: June 28, 2022
    Assignee: Silicon Laboratories Inc.
    Inventors: Ruifeng Sun, Abdulkerim Coban
  • Patent number: 11371954
    Abstract: A capacitance sensing system for sensing frost and ice accumulation. The capacitance sensing system comprises a first capacitor formed by a portion of a metal heat exchanger and a sensor electrode electrically isolated from the metal heat exchanger, a tank oscillator comprising a second capacitor and an inductor connected in parallel with each other and coupled in parallel with the first capacitor, and a circuit coupled to the tank oscillator. The circuit coupled to the tank oscillator is configured to determine a resonant frequency of the tank oscillator, determine a capacitance value based on the resonant frequency of the tank oscillator, determine that the capacitance value is greater than a predefined threshold, and transmit a heater activation command in response to determining the capacitance value is greater than the predefined threshold.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 28, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bjoern Oliver Eversmann, Andreas Felix Martin Kraemer, Michael Seidl
  • Patent number: 11342294
    Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: May 24, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, OhHan Kim, HeeSoo Lee, DaeHyeok Ha, Wanil Lee
  • Patent number: 11342219
    Abstract: A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Kang Fu, Ming-Han Lee
  • Patent number: 11335632
    Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Prithwish Chatterjee, Junnan Zhao, Sai Vadlamani, Ying Wang, Rahul Jain, Andrew J. Brown, Lauren A. Link, Cheng Xu, Sheng C. Li
  • Patent number: 11335616
    Abstract: A semiconductor package may include a composite magnetic inductor that is formed integral with the semiconductor substrate. The composite magnetic inductor may include a composite magnetic resin layer and a plurality of conductive layers arranged such that the composite magnetic resin layer is interleaved between successive conductive layers. The resultant composite magnetic inductor may be disposed between dielectric layers. A core layer may be disposed proximate the composite magnetic inductor. A build-up layer may be disposed proximate the core layer or proximate the composite magnetic inductor in a coreless semiconductor substrate. A semiconductor die may couple to the build-up layer. The composite magnetic inductor beneficially provides a greater inductance than external inductors coupled to the semiconductor package.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Malavarayan Sankarasubramanian, Yongki Min, Ashay A. Dani, Kaladhar Radhakrishnan
  • Patent number: 11329124
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The isolation element partially covers a top surface of the magnetic element. The semiconductor device structure further includes a conductive line over the isolation element. In addition, the semiconductor device structure includes a dielectric layer over the conductive line and the magnetic element.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Chi-Cheng Chen, Hon-Lin Huang, Wei-Li Huang, Chun-Yi Wu, Chen-Shien Chen
  • Patent number: 11321701
    Abstract: A portable communication device is provided, which includes a housing including a rear cover; a battery disposed in the housing; NFC circuitry; wireless charging circuitry; MST circuitry; an FPCB including a plurality of layers substantially parallel to each other, at least a portion of the FPCB being disposed between the battery and the rear cover; an NFC coil electrically connected with the NFC circuitry, the NFC coil including a first portion and a second portion formed at different layers of the FPCB; a wireless charging coil electrically connected with the wireless charging circuitry, the wireless charging coil including a third portion and a fourth portion formed at different layers of the FPCB; and an MST coil electrically connected with the MST circuitry, the MST coil including a fifth portion and a sixth portion at different layers of the FPCB.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 3, 2022
    Inventors: Hee-Dong Lee, Chul-Hyung Yang, Ji-Woo Lee
  • Patent number: 11309243
    Abstract: A package has a first region and a second region. The package includes a first die, a second die, an encapsulant, and an inductor. The second die is stacked on and bonded to the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. A metal density in the first region is greater than a metal density in the second region.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sen-Bor Jan
  • Patent number: 11302470
    Abstract: A semiconductor element includes a first coil substantially located at a first plane; a second coil substantially located at the first plane; a connecting section that connects the first coil and the second coil; a third coil substantially located at a second plane different from the first plane; and a fourth coil substantially located at the second plane. The third coil and the first coil are connected through a through structure, and the fourth coil and the second coil are connected through a through structure. The third coil and the fourth are not directly connected.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 12, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 11296750
    Abstract: One example discloses a near-field wireless device, including: a stack of layers distributed along a first axis; a first near-field antenna having a conductive surface and embedded in a first layer within the stack of layers; wherein the conductive surface is configured to carry non-propagating quasi-static near-field electric-induction signals for on-body near-field communications; a second near-field antenna having an inductive loop and embedded in a second layer within the stack of layers; wherein the inductive loop is configured to carry non-propagating quasi-static near-field magnetic-induction signals for off-body near-field communications; wherein the first and second layers are different layers; and wherein the first and second antennas are not in galvanic contact.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: April 5, 2022
    Assignee: NXP B.V.
    Inventors: Anthony Kerselaers, Liesbeth Gommé
  • Patent number: 11287344
    Abstract: A pressure sensor module including a housing, a pressure sensor chip, and one or more of an integrated passive device (IDP) chip and discrete passive devices are disclosed. The pressure sensor chip and one or more of the IPD chip and the discrete passive devices are arranged within the housing.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 29, 2022
    Assignee: Infineon Technologies AG
    Inventors: Mathias Vaupel, Matthias Boehm, Steven Gross, Markus Loehndorf, Stephan Schmitt, Horst Theuss, Helmut Wietschorke
  • Patent number: 11282800
    Abstract: An inductor in a device package and a method of forming the inductor in the device package are described. The inductor includes a first conductive layer disposed on a substrate. The inductor also has one or more hybrid magnetic additively manufactured (HMAM) layers disposed over and around the first conductive layer to form one or more via openings over the first conductive layer. The inductor further includes one or more vias disposed into the one or more via openings, wherein the one or more vias are only disposed on the portions of the exposed first conductive layer. The inductor has a dielectric layer disposed over and around the one or more vias, the HMAM layers, and the substrate. The inductor also has a second conductive layer disposed over the one or more vias and the dielectric layer.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Feras Eid, Georgios C. Dogiamis
  • Patent number: 11276640
    Abstract: A semiconductor device includes a plurality of first wires formed in a first layer, a plurality of second wires formed to intersect the plurality of first wires in a second layer stacked on the first layer, a plurality of first vias formed at intersections of the plurality of first wires and the plurality of second wires, and an inductor formed in a third layer stacked on the first layer and the second layer.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: March 15, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shinichi Uchida
  • Patent number: 11277067
    Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a magnetic component, a bare power chip and a conductive set. The magnetic component includes a first surface and a second surface opposite to each other. The bare power chip is disposed on the magnetic component and includes a third surface and a fourth surface opposite to each other. The conductive set is disposed on the magnetic component and electrically connected with the magnetic component and the bare power chip. The third or fourth surface of the bare power chip is at least partially attached on the first or second surface of the magnetic component, and at least partially included in a projected envelopment of the corresponding first or second surface of the magnetic component, so as to facilitate the magnetic component to support the bare power chip.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: March 15, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Shouyu Hong, Qingdong Chen, Kai Lu, Pengkai Ji, Xiaoni Xin, Min Zhou, Yu Zhang, Jianhong Zeng
  • Patent number: 11271071
    Abstract: A semiconductor device includes a substrate having a surface and a thin film inductor formed on top of the surface of the substrate and having a conductive wire, a first stack of magnetic layers and a second stack of magnetic layers. The conductive wire is disposed between the first and second stacks of magnetic layers, and the thin film inductor is configured to provide a magnetic field in the first and second stacks of magnetic layers in response to a current passing through the conductive wire. The first stack of magnetic layers has a first edge portion extending in parallel with a longitudinal axis of the conductive wire, and the second stack of magnetic layers has a second edge portion that covers the first edge portion conformally and is separated from the first edge portion by an insulation layer.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 8, 2022
    Assignee: Nuvia, Inc.
    Inventor: Peng Zou
  • Patent number: 11257754
    Abstract: A semiconductor device includes a substrate having a first region, a second region, a first buffer region, and a second buffer region. A plurality of conductive lines is disposed on the first region of the substrate. An inductor is disposed on the second region of the substrate, and a dummy pattern is disposed on the first buffer region of the substrate. The first buffer region is provided between the first region and the second region. The second buffer region is provided between the first buffer region and the second region.
    Type: Grant
    Filed: August 24, 2019
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Nyung Lee, Jeong Hoon Ahn
  • Patent number: 11250985
    Abstract: A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: February 15, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 11251644
    Abstract: A semiconductor device package is provided, including a semiconductor device, a molding material, and a conductive slot. The molding material surrounds the semiconductor device. The conductive slot is positioned over the molding material and having an opening and at least two channels connecting the opening to the edges of the conductive slot.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chen-Hua Yu, Hao-Yi Tsai, Tzu-Sung Huang, Ming-Hung Tseng, Hung-Yi Kuo
  • Patent number: 11227713
    Abstract: An integrated transformer can be fabricated to include multiple first conductors, a magnetic core, and multiple second conductors. The first conductor can be fabricated within a first layer of a semiconductor layer stack. The magnetic core can be fabricated within multiple second layers, below the first layer, of the semiconductor layer stack. The multiple second conductors can be fabricated within a third layer, below the second layer, of the semiconductor layer stack. The multiple first conductors can be connected to the multiple second conductors to form a primary winding of the integrated transformer. The integrated transformer can additionally include a coupling element to wrap around the magnetic core to form a secondary winding of the integrated transformer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 18, 2022
    Inventors: Alan Roth, Eric Soenen
  • Patent number: 11222745
    Abstract: A coil according to one embodiment of the present invention is a coil in which a first electric wire on an inner peripheral side and a second electric wire on an outer peripheral side are wound side by side to connect ends of the electric wires with each other, and the coil includes a first region where the first electric wire abuts on the second electric wire of another adjacent turn and separates from the second electric wire of a same turn.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 11, 2022
    Assignee: SWCC SHOWA CABLE SYSTEMS CO., LTD.
    Inventors: Hideki Matsumoto, Kiyoshi Miura, Kentaro Nouchi
  • Patent number: 11201136
    Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles Leon Arvin, Bhupender Singh, Shidong Li, Chris Muzzy, Thomas Anthony Wassick
  • Patent number: 11189418
    Abstract: Disclosed herein is a coil component that includes first and second coil parts each spirally wound in a plurality of turns in directions opposite to each other. An innermost turn of the first coil part is radially divided into first and second conductor parts by a spiral slit, and at least an innermost turn of the second coil part is radially divided into third and fourth conductor parts by a spiral slit. The first conductor part is positioned radially inward of the second conductor part, and the third conductor part is positioned radially inward of the fourth conductor part. The inner peripheral end of the first conductor part is connected to the inner peripheral end of the fourth conductor part, and the inner peripheral end of the second conductor part is connected to the inner peripheral end of the third conductor part.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: November 30, 2021
    Assignee: TDK CORPORATION
    Inventors: Toshifumi Komachi, Kosuke Kunitsuka, Toshio Tomonari
  • Patent number: 11183475
    Abstract: A semiconductor structure including a plurality of semiconductor dies, an insulating encapsulant, and a redistribution structure disposed on the semiconductor dies and the insulating encapsulant is provided. The insulating encapsulant is interposed between adjacent two of the semiconductor dies, and the insulating encapsulant includes a first portion wider than a second portion connected to the first portion. The redistribution structure includes a dielectric layer overlying the insulating encapsulant, and a conductive trace overlying the dielectric layer and opposite to the insulating encapsulant. The conductive trace includes at least one turn and is connected to a conductive terminal of one of the adjacent two of the semiconductor dies, and the conductive trace extends across the dielectric layer to reach another conductive terminal of another one of the adjacent two of the semiconductor dies.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • Patent number: 11183471
    Abstract: A semiconductor device includes a semiconductor substrate, a multilayer wiring layer, a first inductor element, and a first capacitor element. The multilayer wiring layer is formed on the semiconductor substrate. The first inductor element and the first capacitor element are formed in the multilayer wiring layer. The first capacitor element is formed in the same layer as a layer in which the first inductor element is formed. The first capacitor element is formed inside the first inductor element in plan view.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 23, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutaka Nakashiba
  • Patent number: 11177242
    Abstract: A semiconductor device is disclosed including one or more semiconductor dies mounted on substrate. Each semiconductor die may be formed with a ferromagnetic layer on a lower, inactive surface of the semiconductor die. The ferromagnetic layer pulls the semiconductor dies down against each other and the substrate during fabrication to prevent warping of the dies. The ferromagnetic layer also balances out a mismatch of coefficients of thermal expansion between layers of the dies, thus further preventing warping of the dies.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yangming Liu, Ning Ye, Bo Yang
  • Patent number: 11145452
    Abstract: An inductor includes a body including a support member, a coil, and an encapsulant, and external electrodes on external surfaces of the body. The coil in the body may be formed so that a plurality of coil patterns are continuously formed, wherein the coil pattern includes first and second coil layers, and the encapsulant extends downward between adjacent coil patterns to be between first coil layers of adjacent coil patterns.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: October 12, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Boum Seock Kim, Byeong Cheol Moon, Kang Wook Bong, Young Min Hur, Joung Gul Ryu
  • Patent number: 11135270
    Abstract: A medicament for preventing or treating heart failure containing an antagonist of the corticotropin releasing hormone receptor 2 as an active ingredient.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: October 5, 2021
    Assignee: RAQUALIA PHARMA INC.
    Inventor: Mikito Takefuji
  • Patent number: 11139240
    Abstract: A semiconductor module includes a semiconductor chip including wiring formed over a semiconductor element such as a MISFET, a sealing resin part MR covering the semiconductor chip such that the wiring is exposed, and an inductor formed in redistribution wiring. The inductor overlaps with the sealing resin part covering at least a side surface of the semiconductor chip in plan view.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: October 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba
  • Patent number: 11133250
    Abstract: A semiconductor component may have a semiconductor body and an electrically conductive carrier layer. The semiconductor body may include a first semiconductor layer and a second semiconductor layer, a first main face and a second main face, situated opposite the first main face, wherein the first main face is formed by a surface of the first semiconductor layer and the second main face is formed by a surface of the second semiconductor layer. The semiconductor body may further include at least one side face connecting the first main face to the second main face. The electrically conductive carrier layer may regionally cover the second main face the carrier layer is structured in such a way that it has at least one contact-free depression. Furthermore, a method for producing such a semiconductor component is disclosed.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 28, 2021
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Isabel Otto, Dominik Scholz, Christian Leirer
  • Patent number: 11127529
    Abstract: A method of manufacturing a laminated coil component is a method of manufacturing a laminated coil component provided with a laminate obtained by laminating a coil conductor forming a spiral coil and an insulator layer. The method of manufacturing a laminated coil component includes a step of providing a conductor pattern configured to become a coil conductor on a green sheet configured to become an insulator layer, and a step of laminating a plurality of green sheets provided with the conductor pattern. The conductor pattern includes a pair of first side surfaces opposed to each other in an orthogonal direction orthogonal to a laminating direction of the green sheet. At the step of laminating a plurality of green sheets, a depression is formed on at least one of the pair of first side surfaces.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: September 21, 2021
    Assignee: TDK CORPORATION
    Inventors: Yuya Oshima, Makoto Yoshino, Yoji Tozawa, Junichi Otsuka, Kazuo Iwai, Yohei Tadaki, Shinichi Kondo, Kazuhiro Ebina, Mamoru Kawauchi
  • Patent number: 11107801
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Puu Jeng, Po-Yao Lin, Shuo-Mao Chen, Feng-Cheng Hsu, Chia-Hsiang Lin
  • Patent number: 11088071
    Abstract: A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first conductive line and a first inter metal dielectric (IMD) layer. The first substrate is over the first gate layer. The first shielding layer is over the first substrate. The first conductive line is over the first shielding layer. The first IMD layer is between the first substrate and the first conductive line.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
  • Patent number: 11083092
    Abstract: A planar coil element of the present invention includes an insulating base film having a first surface and a second surface opposite to the first surface, a first conductive pattern deposited on the first surface side of the insulating base film, and a first insulating layer covering the first conductive pattern on the first surface side, in which the first conductive pattern includes a core body and a widening layer deposited by plating on the outer surface of the core body, and the ratio of the average thickness of the first conductive pattern to the average circuit pitch of the first conductive pattern is ½ or more and 5 or less.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: August 3, 2021
    Assignee: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Hiroshi Ueda, Kousuke Miura, Yoshihito Yamaguchi, Yuka Urabe
  • Patent number: 11075176
    Abstract: In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hung-Yi Kuo, Hao-Yi Tsai, Ming Hung Tseng
  • Patent number: 11063019
    Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11056467
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Duesman, James E. Davis, Warren L. Boyer
  • Patent number: 11037885
    Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chien, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen, Yi-Shin Chu, Yu-Yang Shen
  • Patent number: 11031456
    Abstract: A rolled-up electromagnetic component for on-chip applications comprises: a multilayer sheet in a rolled configuration comprising at least one turn about a longitudinal axis; a core defined by a first turn of the rolled configuration; and a soft magnetic material disposed within the core, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. A method of making a rolled-up electromagnetic component for on-chip applications includes forming a rolled-up device comprising: a multilayer sheet in a rolled configuration having at least one turn about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer; and a core defined by a first turn of the rolled configuration. The method further includes introducing a soft magnetic material into the core.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: June 8, 2021
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Wen Huang, Zhendong Yang, Mark D. Kraman, Jimmy Ni, Zihao Ou, Qian Chen, J. Gary Eden
  • Patent number: 11024701
    Abstract: An integrated electronic component for broadband biasing that includes a monolithic substrate, a capacitor structure arranged in a trench network that extends into the substrate, and a continuous track of an electrically conducting material arranged in a crater that is formed in the substrate. The continuous track has one or several turns that have decreasing turn sections, and that are supported by a slanted peripheral wall of the crater for forming an inductor.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: June 1, 2021
    Assignee: MURATA INTEGRATED PASSIVE SOLUTIONS
    Inventors: Stéphane Bouvier, Jean-René Tenailleau
  • Patent number: 11024566
    Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: June 1, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Uchida, Akio Ono, Shinichi Kuwabara, Yasutaka Nakashiba
  • Patent number: 11018065
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a testing region and multiple first conductive lines over the testing region. The first conductive lines are electrically connected in series. The semiconductor device structure also includes multiple second conductive lines over the testing region. The second conductive lines are electrically connected in series, and the second conductive lines are physically separated from the first conductive lines. The semiconductor device structure further includes multiple magnetic structures wrapping around portions of the first conductive lines and wrapping around portions of the second conductive lines. The magnetic structures are arranged in a column.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mill-Jer Wang, Tang-Jung Chiu, Chi-Chang Lai, Chia-Heng Tsai, Mirng-Ji Lii, Weii Liao
  • Patent number: 11011295
    Abstract: An integrated circuit transformer structure includes at least two conductor groups stacked in parallel in different layers. A first spiral track is formed in the at least two conductor groups, the first spiral track included first turns of a first radius within each of the at least two conductor groups, and second turns of a second radius within each of the at least two conductor groups, the first and second turns being electrically connected. A second spiral track is formed in the at least two conductor groups, the second spiral track including third turns of a third radius within each of the at least two conductor groups and disposed in a same plane between the first and second turns in each of the at least two conductor groups.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Barry, Robert A. Groves, Venkata Nr. Vanukuru
  • Patent number: 11004811
    Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, and a RDL disposed over the transceiver. The RDL includes an antenna and a dielectric layer. The antenna is disposed over and electrically connected to the transceiver. The dielectric layer surrounds the antenna. The antenna includes an elongated portion and a via portion. The elongated portion extends over the molding, and the via portion is electrically connected to the transceiver.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Vincent Chen, Hung-Yi Kuo, Chuei-Tang Wang, Hao-Yi Tsai, Chen-Hua Yu, Wei-Ting Chen, Ming Hung Tseng, Yen-Liang Lin