Including Inductive Element Patents (Class 257/531)
  • Patent number: 10340077
    Abstract: Provided are a feed unit, a feed system, and an electronic device that enable transmission efficiency control according to the position of a device when electric power transmission using a magnetic field is performed between devices. The feed unit includes a power transmission section including a power transmission coil configured to perform electric power transmission using a magnetic field, and an auxiliary resonance section including one or a plurality of resonators. The resonator includes an auxiliary coil wound to form a gap in at least a partial region.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: July 2, 2019
    Assignee: SONY CORPORATION
    Inventor: Takashi Miyamoto
  • Patent number: 10340231
    Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hung Chen, Chu-Fu Lin, Ming-Tse Lin
  • Patent number: 10340871
    Abstract: The disclosure generally relates to a compact bypass and decoupling structure that can be used in a millimeter-wave radio frequency integrated circuit (RFIC). For example, according to various aspects, an RFIC incorporating the compact bypass and decoupling structure may comprise a grounded substrate, a mid-metal ground plane, a bypass capacitor disposed between the grounded substrate and the mid-metal ground plane, and a decoupling inductor disposed over the mid-metal ground plane. The bypass capacitor may close a current loop in the RFIC and the decoupling inductor may provide damping in a supply network associated with the RFIC. Furthermore, the decoupling conductor may have a self-resonance substantially close to an operating band associated with the RFIC to increase series isolation, introduce substrate losses that facilitate the damping in the supply network, and prevent high-Q resonances.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: July 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Alon Yehezkely, Sagi Kupferman
  • Patent number: 10319518
    Abstract: A method of fabricating a spiral inductor includes providing a substrate having a top surface and a bottom surface, forming a plurality of through holes aligned in a vertical plane and spaced apart from each other, forming a metal interconnect structure having at least one top metal layer on the top surface of the substrate, the metal interconnect structure configured to connect to a top portion of the through holes, and forming a redistribution layer having at least a bottom layer on the bottom surface of the substrate. The redistribution layer is configured to connect to a bottom portion of the through holes to form a spiral structure.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 11, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Dekui Qi, Haifang Zhang, Xuanjie Liu, Zheng Chen, Xin Li
  • Patent number: 10304686
    Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Sasha N. Oster, Fay Hua, Telesphor Kamgaing, Adel A. Elsherbini, Henning Braunisch, Johanna M. Swan
  • Patent number: 10297657
    Abstract: A device includes an insulating layer disposed over a silicon substrate. The insulating layer includes a core insulating area and a peripheral insulating area. A trench laterally encloses the core insulating area and separates the core insulating area from the peripheral insulating area. A magnetic winding coil is disposed within the trench and separates the core insulating area from the peripheral insulating area. A conductive inner core is disposed within the core insulating area and is surrounded by the magnetic winding coil. The conductive inner core is made of a first material that is electrically conductive, and the magnetic winding coil is made of a second material that is magnetic and differs from the first material.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Wen-Shiang Liao
  • Patent number: 10269735
    Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure including: a first conductive layer of a device structure; a second conductive layer of the device structure vertically separated from the first conductive layer, wherein a load resistor couples the second conductive layer to ground; a t-coil having a first end coupled to the first conductive layer, and a second end coupled to the second conductive layer; and a variable capacitor having a first end coupled to the first conductive layer, and a second end coupled to the second conductive layer, the variable capacitor having an adjustable capacitance.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: April 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Umesh Kumar Shukla, Sandeep Torgal, Venkata N. R. Vanukuru
  • Patent number: 10262782
    Abstract: An 8-shaped integrated inductor includes a first terminal; a second terminal; a third terminal; a bridging structure that includes a first metal segment and a second metal segment, the first metal segment and the second metal segment being disposed in different layers of a semiconductor structure and partially overlapping; a first sensing unit employing the first terminal and the third terminal as its two terminals and including the first metal segment; and a second sensing unit employing the second terminal and the third terminal as its two terminals and including the second metal segment and a third metal segment. The third metal segment is disposed at a metal layer different from the second metal segment and conductively connecting other metal segments of the second sensing unit without crossing the metal segments of the first sensing unit.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: April 16, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10263314
    Abstract: A power combiner in the form of a balanced LC combiner is provided. Inputs of the power combiner are isolated from one another via at least one RC matching element. The at least one RC matching element is dimensioned such that the connection between the inputs is at a stable potential during operation of the power combiner at at least one position. The power combiner can be formed in a planar design and have electrically conductive layers running parallel to one another. At least an inductor and a combiner capacitor are formed in the electrically conductive layers. A power combiner arrangement including the power combiner and high-frequency signal sources attached at least two inputs is also provided. The high-frequency signal sources can be in the form of frequency-agile transistor amplifiers.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: April 16, 2019
    Assignee: TRUMPF Huettinger GmbH + Co. KG
    Inventors: Andre Grede, Alexander Alt, Daniel Gruner, Anton Labanc
  • Patent number: 10256189
    Abstract: A scalable switching regulator architecture has an integrated inductor. In some embodiments an area and current drive capability of switches of the switching regulator is matched with an inductor built within an area above the switches. In some embodiments the combined switches and inductor are constructed as a unit cell and can be combined to form larger elements as required for higher current drive capability and multiphase operation.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 9, 2019
    Assignee: Chaoyang Semiconductor Jiangyin Technology Co., Ltd.
    Inventor: Taner Dosluoglu
  • Patent number: 10249579
    Abstract: An electronic apparatus includes, a substrate, one or more routing layers, and an active shield layer. The substrate includes active devices. The routing layers are electrically connected to the active devices and are configured to route electrical signals to and from the active devices. The active shield layer is disposed within a routing layer nearest to the substrate, the active shield layer includes metallic traces configured conduct active-shield signals that provide an indication of an attack on the apparatus.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 2, 2019
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Yuval Kirschner, Arnon Sharlin
  • Patent number: 10236209
    Abstract: Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die molding a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Sujit Sharan, Ravindranath Mahajan, Stefan Rusu, Donald S. Gardner
  • Patent number: 10237650
    Abstract: A feedback signal is employed to facilitate enhancing an acoustic overload point and electrostatic discharge protection of a sensor component and associated circuit. The sensor component comprises a backplate component and a diaphragm component. The backplate component is biased to a low-level voltage associated with a ground. The diaphragm component is biased to a defined high-voltage associated with a charge pump. The diaphragm component generates a signal based on movement of the diaphragm component in relation to the backplate component in response to the input signal. A feedback component receives the signal from the diaphragm component and generates an inverted signal based on the signal. The inverted signal or a processed inverted signal, which can be derived from a filter component that filters the inverted signal, is transmitted to the backplate component.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: March 19, 2019
    Assignee: INVENSENSE, INC.
    Inventors: Igor Mucha, Marek Matej, Peter Pracny
  • Patent number: 10236265
    Abstract: A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Stefan Kramp, Marco Koitz
  • Patent number: 10217563
    Abstract: A method of manufacturing a multi-layer coil includes steps of providing a substrate; forming a seed layer on the substrate; and plating the seed layer with N coil layers by N current densities according to N threshold ranges, so as to form the multi-layer coil on the substrate, wherein an i-th current density of the N current densities is lower than an (i+1)-th current density of the N current densities. A first coil layer of the N coil layers is plated on the seed layer by a first current density of the N current densities. When an aspect ratio of an i-th coil layer of the N coil layers is within an i-th threshold range of the N threshold ranges, an (i+1)-th coil layer of the N coil layers is plated on the i-th coil layer by the (i+1)-th current density.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: February 26, 2019
    Assignee: CYNTEC CO., LTD.
    Inventors: Chung-Hsiung Wang, Lang-Yi Chiang, Wei-Chien Chang, Yu-Hsin Lin
  • Patent number: 10217703
    Abstract: An integrated circuit device is described. The integrated circuit device comprises a substrate; a plurality of metal routing interconnect layers; an inductor formed in at least one metal layer of the plurality of metal routing interconnect layers; and a bottom metal layer between the plurality of metal routing interconnect layers and the substrate; wherein a pattern ground shield is formed in the bottom metal layer. A method of implementing an integrated circuit device is also disclosed.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: February 26, 2019
    Assignee: XILINX, INC.
    Inventors: Parag Upadhyaya, Jing Jing
  • Patent number: 10210981
    Abstract: An 8-shaped integrated inductor includes a first terminal; a second terminal; a third terminal; a bridging structure that includes a first metal segment and a second metal segment, the first metal segment and the second metal segment being disposed in different layers of a semiconductor structure and partially overlapping; a first sensing unit employing the first terminal and the third terminal as its two terminals and including the first metal segment; and a second sensing unit employing the second terminal and the third terminal as its two terminals and including the second metal segment and a third metal segment. The third metal segment is disposed at a metal layer different from the second metal segment and conductively connecting other metal segments of the second sensing unit without crossing the metal segments of the first sensing unit.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: February 19, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10199340
    Abstract: A signal transmission insulating device includes: a first coil; a second coil opposing the first coil to form a transformer together with the first coil; a first insulating film provided between the opposing first coil and second coil and made of a first dielectric material; a second insulating film surrounding the first coil and made of a second dielectric material having a lower resistivity or a higher permittivity than the first dielectric material; and a third insulating film surrounding the second coil and made of a third dielectric material having a lower resistivity or a higher permittivity than the first dielectric material.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: February 5, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Suga, Takao Tsurimoto, Hiroki Shiota, Kenichi Morokuma, Shoichi Orita, Fumitaka Tametani, Takahiro Inoue, Shiori Uota
  • Patent number: 10199573
    Abstract: A method of fabricating a semiconductor device includes aligning an alignment structure of a wafer to a direction of a magnetic field created by an external electromagnet and depositing a magnetic layer (e.g., NiFe) over the wafer in the presence of the magnetic field and while applying the magnetic field and maintaining a temperature of the wafer below 150° C. An insulation layer (e.g., AlN) is deposited on the first magnetic layer. The alignment structure of the wafer is again aligned to the direction of the magnetic field and a second magnetic layer is deposited on the insulation layer, in the presence of the magnetic field and while maintaining the temperature of the wafer below 150° C.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 5, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mona Eissa, Dok Won Lee, Byron Shulver, Yousong Zhang
  • Patent number: 10186371
    Abstract: A magnetic field generation apparatus includes a plurality of coplanar inductors disposed to form a planar structure, wherein each of the coplanar inductors is configured to generate a magnetic field having a basis vector that is orthogonal to a basis vector of a magnetic field generated by another one of the coplanar inductors.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: January 22, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nikolay Nikolaevich Olyunin, Ki Young Kim, Keum Su Song, Mikhail Nikolaevich Makurin
  • Patent number: 10181419
    Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: January 15, 2019
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
  • Patent number: 10181449
    Abstract: A semiconductor structure including an insulating encapsulant, a first semiconductor die, a second semiconductor die and a redistribution circuit layer is provided. The first and the second semiconductor dies embedded in the insulating encapsulant and separated from one another. The first semiconductor die includes a first active surface accessibly exposed and a first conductive terminal distributed at the first active surface. The second semiconductor die includes a second active surface accessibly exposed and a second conductive terminal distributed at the second active surface. The redistribution circuit layer including a conductive trace is disposed on the first and the second active surfaces and the insulating encapsulant. The conductive trace is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to the top width of the insulating encapsulant ranges from about 3 to about 10.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • Patent number: 10163878
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate including a front surface and a back surface; a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, at least a portion of the backside metallization layer forming an inductor structure; and an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate. A method for manufacturing a semiconductor structure is also disclosed.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsing-Chih Lin, Ching-Chun Wang
  • Patent number: 10157830
    Abstract: A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kyle K. Kirby
  • Patent number: 10134671
    Abstract: A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: November 20, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kyle K. Kirby
  • Patent number: 10128037
    Abstract: Inductors are fabricated in core layers according to a predefined semiconductor package manufacturing process rules. The inductors provide an embedded substrate trace inductor solution. The inductors may be part of an on-chip voltage regulator or any other circuit design. The inductors provide a core spiral structure to help increase inductance, particularly using magnetic field coupling between inductors. The core layers provide thicker and heavier conductive segments for the inductors, particularly as compared to inductors fabricated in build-up layers according to the semiconductor package manufacturing process rules.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: November 13, 2018
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Namhoon Kim, Sampath Komarapalayam Karikalan, Zhihui Wang, Jin Seong Choi, Boon Leong Tan, Edward Law
  • Patent number: 10115685
    Abstract: A method of manufacturing a semiconductor structure includes providing a transceiver, forming a molding to surround the transceiver, forming a plurality of recesses extending through the molding, disposing a conductive material into the plurality of recesses to form a plurality of vias, disposing and patterning an insulating layer over the molding, the plurality of vias and the transceiver, and forming a redistribution layer (RDL) over the insulating layer, wherein the RDL comprises an antenna disposed over the insulating layer and a dielectric layer covering the antenna, and a portion of the antenna is extended through the insulating layer and is electrically connected with the transceiver.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Vincent Chen, Hung-Yi Kuo, Chuei-Tang Wang, Hao-Yi Tsai, Chen-Hua Yu, Wei-Ting Chen, Ming Hung Tseng, Yen-Liang Lin
  • Patent number: 10115513
    Abstract: An integrated inductor structure includes a guard ring, a patterned ground shield, and an inductor. The guard ring includes an inner ring, an outer ring, and an interlaced structure. The inner ring is disposed in a first metal layer, and includes at least two inner ring openings. The outer ring is disposed in a second metal layer, and includes at least one outer ring opening. The interlaced structure is coupled to one of the at least two inner ring openings and the outer ring opening in an interlaced manner, such that the outer ring opening is enclosed. The patterned ground shield is disposed at an inner side of the inner ring, and coupled to the inner ring and the outer ring. The inductor is formed above the guard ring and the patterned ground shield.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: October 30, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10110166
    Abstract: A receiver front-end capable of receiving RF inputs having a broad range of levels. The receiver comprises a low-noise amplifier (LNA) operating in a variety of bias modes that cover a large gain range. Branches of the amplifier can be turned on in various combinations to allow selection of different bias modes. A degeneration inductor coupled to the source of the common source FET of each branch has a plurality of taps that are coupled to degeneration switches that can ground the tap to effectively shorten the degeneration inductor and reduce the amount of degeneration inductance. The degeneration inductor and associated switches can be fabricated using one of several physical layouts. Operating the degeneration switches to select the length of the degeneration inductor to match the bias mode reduces changes in the input impedance as different bias modes are selected.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: October 23, 2018
    Assignee: pSemi Corporation
    Inventor: Hossein Noori
  • Patent number: 10109404
    Abstract: A low profile inductor structure suitable for use in a high power density power converter has one or more windings formed by vias through a thin, generally planar body of magnetic material forming the inductor core and conductive cladding on the body of magnetic material or material covering the magnetic material body. Variation of inductance with load current and other operational or environmental parameters is reduced to any desired degree by forming a slot that removes all or a portion of the magnetic material between the locations of the vias.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 23, 2018
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Yipeng Su, Dongbin Hou, Fred C. Lee, Qiang Li
  • Patent number: 10109408
    Abstract: A magnetic patterned wafer used for production of magnetic-core-inductor chip bodies includes a peripheral end portion and at least one core chip unit that including a connecting portion, a breaking line, and a plurality of spaced apart chip bodies. The connecting portion is connected to the peripheral end portion and is spaced apart from the chip bodies by a tab-accommodating space. The breaking line has a plurality of connecting tabs that are spaced apart from one another and that are disposed in the tab-accommodating space. Each of the connecting tabs interconnects the connecting portion and a respective one of the chip bodies. The patterned wafer is made from a magnetic material.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: October 23, 2018
    Assignee: WAFER MEMS CO., LTD.
    Inventors: Min-Ho Hsiao, Pang-Yen Lee, Yen-Hao Tseng
  • Patent number: 10102967
    Abstract: A method for manufacturing an inductor core is developed, wherein the method comprises the following: Forming a first electrical conductor on a first surface of a plate-shaped magnetic core; forming a second electrical conductor on a second surface of the plate-shaped magnetic core, which is opposite the first surface; and forming the inductor core by dicing the plate-shaped magnetic core transverse to the first electrical conductor and second electrical conductor.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: October 16, 2018
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Bernhard Knott, Rainer Leuschner
  • Patent number: 10103554
    Abstract: There are provided a thin film coil and an electronic device having the same, the thin film coil including a substrate; and a coil pattern including a first coil strand and a second coil strand formed on both surfaces of the substrate, respectively, wherein the first coil strand formed on one surface of the substrate includes at least one gyration path that passes through the other surface of the substrate and gyrates.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: October 16, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dae Ki Lim, Tae Sung Kim, Hyeon Gil Nam, Chan Gwang An, Hyun Seok Lee, Ki Won Chang, Chang Mok Han, Sang Woo Bae, Sung Eun Cho, Jae Suk Sung
  • Patent number: 10090243
    Abstract: An inductor includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of contacts. Each of the first conductive lines is spaced apart from one another. Each of the second conductive lines is spaced apart from one another, and each of the second conductive lines crosses over each of the first conductive lines. Each of the contacts electrically interconnects one of the first conductive lines and one of the second conductive lines. These contacts are arranged in a way such that at least parts of the first conductive lines and at least parts of the second conductive lines form an electric current path serving as an inductor.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: October 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hao-Hsiang Chuang, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 10083922
    Abstract: A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Min Suet Lim, Chin Lee Kuan, Eng Huat Goh, Khang Choong Yong, Bok Eng Cheah, Jackson Chung Peng Kong, Howe Yin Loo
  • Patent number: 10037961
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, a plurality of conductive through vias, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The insulating encapsulation encapsulates sidewalls of the integrated circuit. The conductive through vias penetrate in the insulating encapsulation. The redistribution circuit structure is disposed on the integrated circuit, the conductive through vias and the insulating encapsulation. The redistribution conductive layer is electrically connected to the conductive terminals and the conductive through vias. A plurality of first contact surfaces of the conductive terminals and a plurality of second contact surfaces of the conductive through vias are in contact with the redistribution circuit structure, and a roughness of the first contact surfaces and the second contact surfaces ranges from 100 angstroms to 500 angstroms.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10033334
    Abstract: The disclosure is directed to a tunable peaking amplifier circuit including: an input node, an output node and a feedback node; a first input amplifier having an input connected to the input node and an output connected to the feedback node; a second input amplifier having an input connected to the input node; a coupling capacitor connected between an output of the second input amplifier and the feedback node; an amplifier having an input connected to the feedback node and an output connected to the output node; and a feedback circuit having an input coupled to the output node and an output connected to the feedback node, the feedback circuit including a tuning circuit for varying a transconductance of the feedback circuit to adjust an operational frequency of the peaking amplifier circuit.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 24, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael Chen, Steven M. Clements, Mohak Chhabra, Steven E. Mikes, Hayden C. Cranford, Jr.
  • Patent number: 10027228
    Abstract: An input smoothing circuit is provided between an input line and a ground line. A high-side transistor and a low-side transistor are provided in series between the two ends of the input smoothing circuit. The high-side transistor and the low-side transistor are arranged side by side in a first direction on a circuit board. Two current loops that run through the smoothing circuit, the high-side transistor, and the low-side transistor are formed to be substantially linearly symmetrical with respect to an axis of symmetry that extends in the first direction.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: July 17, 2018
    Assignee: Sony Interactive Entertainment Inc.
    Inventor: Kazuki Sasao
  • Patent number: 10026539
    Abstract: A thin film type coil component including coil patterns in a cross section shape having an undercut in lower portions thereof is provided. The coil patterns may reduce parasitic capacitance between the coil patterns, thereby minimizing electrical loss. The volume of the coil patterns may be increased, thereby improving inductance and resistance characteristics.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: July 17, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ju Hwan Yang, Young Seuck Yoo, Jae Yeol Choi, Jong Bong Lim
  • Patent number: 10020271
    Abstract: A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo
  • Patent number: 9997447
    Abstract: A semiconductor device package includes a carrier, a first insulation layer, a capacitor element, a plurality of interconnection structures, a plurality of substantially parallel top-side metal bars, and a plurality of substantially parallel bottom-side metal bars. The first insulation layer is on the carrier and has a first surface and a second surface adjacent to the carrier and opposite to the first surface, the first insulation layer defining a plurality of through holes. The capacitor element is in the first insulation layer, the capacitor element including a top electrode and a bottom electrode. The plurality of interconnection structures are within the through holes and formed as conductive through holes. The plurality of substantially parallel top-side metal bars are on the first surface of the first insulation layer. The plurality of substantially parallel bottom-side metal bars are on the second surface of the first insulation layer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 12, 2018
    Assignee: ADVANCED SSEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Hung-Yi Lin, Sheng-Chi Hsieh
  • Patent number: 9986640
    Abstract: A coil component includes coil conductors having a multilayer structure including via pads, and vias connected between the via pads on the respective layers. Portions or overall regions of the via pads on two layers which are adjacent to each other overlap each other, and the vias in two layers which are connected to each other by the via pad formed therebetween are disposed in alternating positions.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ju Hwan Yang, Jin Hyuck Yang, Jong Yun Lee, Won Chul Sim
  • Patent number: 9984819
    Abstract: A spiral inductor formed in a vertical plane relative to a planar surface of a substrate includes a plurality of through holes disposed in the vertical plane and spaced apart from each other, a metal interconnect structure on the top surface, and a redistribution layer on the bottom surface and having at least one bottom metal layer. The metal interconnect structure and the redistribution layer are connected to each other through the plurality of through holes to form the vertical spiral inductor. The thus formed vertical spiral inductor has a significantly reduced surface area comparing with lateral spiral inductors.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: May 29, 2018
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Dekui Qi, Haifang Zhang, Xuanjie Liu, Zheng Chen, Xin Li
  • Patent number: 9978717
    Abstract: The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: May 22, 2018
    Assignee: THRUCHIP JAPAN INC.
    Inventor: Tadahiro Kuroda
  • Patent number: 9976224
    Abstract: There are provided a chip electronic component comprising: a magnetic body including an insulation substrate; an internal coil part formed on at least one surface of the insulation substrate; and an external electrode formed on an end surface of the magnetic body and connected to the internal coil part, wherein the internal coil part includes a first coil pattern formed on the insulation substrate and a second coil pattern formed to coat the first coil pattern, and a ratio a/b of a width a of an upper surface of the first coil pattern with respect to a width b of a lower surface of the first coil pattern is less than 1.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong Jin Jeong, Sung Hoon Kim, Byung Seung Min
  • Patent number: 9953938
    Abstract: An electromagnetic coupler assembly includes a handle wafer having an oxide layer disposed on a first surface thereof. A layer of active semiconductor is disposed on the oxide layer and includes a voltage terminal to receive a supply voltage. A layer of dielectric material is disposed on the layer of active semiconductor. A main transmission line is disposed on the layer of dielectric material. A coupled transmission line is disposed on the layer of active semiconductor and is one of inductively coupled to the main transmission line and capacitively coupled to the main transmission line. At least a portion of one of the main transmission line and the coupled transmission line is disposed directly above at least a portion of the layer of active semiconductor.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 24, 2018
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Nuttapong Srirattana, David Scott Whitefield
  • Patent number: 9949381
    Abstract: An electronic device includes a substrate having an external surface, and an integrated circuit over the external surface of the substrate. The substrate is provided with an electrical connection network including electrical links for linking the integrated circuit to another electrical device. Some of the electrical links include an impedance-compensating inductor on an external surface of the substrate.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: April 17, 2018
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: David Auchere, Laurent Marechal
  • Patent number: 9941201
    Abstract: In one embodiment, an integrated circuit die includes first and second inductor structures, a first ground conductor, a second ground conductor and a conductive trace. The first ground conductor provides a first ground pathway for the first inductor structure. The second ground conductor provides a second ground pathway for the second inductor structure. The conductive trace coupled between the first and second ground conductors may magnetically decouple the first and second inductor structures. In addition, the integrated circuit die may also include conductive guard ring structures that surround the first and second inductor structures. One of the conductive guard ring structures may be connected to the first grounding pathway and the other conductive guard ring structure may be connected to the second grounding pathway. The conductive guard ring structures may further magnetically decouple the first and second inductor structures.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: April 10, 2018
    Assignee: Altera Corporation
    Inventors: Xiaohong Jiang, Nathaniel Wright Unger, Kyung Suk Oh
  • Patent number: 9933881
    Abstract: An inductive touch module and an inductive touch display device and the manufacturing method thereof are disclosed.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: April 3, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Xiangyang Xu
  • Patent number: 9929132
    Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: March 27, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Teck-Chong Lee, Chien-Hua Chen, Yung-Shun Chang, Pao-Nan Lee