Including Inductive Element Patents (Class 257/531)
  • Patent number: 11075176
    Abstract: In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hung-Yi Kuo, Hao-Yi Tsai, Ming Hung Tseng
  • Patent number: 11063019
    Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11056467
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Duesman, James E. Davis, Warren L. Boyer
  • Patent number: 11037885
    Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chien, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen, Yi-Shin Chu, Yu-Yang Shen
  • Patent number: 11031456
    Abstract: A rolled-up electromagnetic component for on-chip applications comprises: a multilayer sheet in a rolled configuration comprising at least one turn about a longitudinal axis; a core defined by a first turn of the rolled configuration; and a soft magnetic material disposed within the core, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. A method of making a rolled-up electromagnetic component for on-chip applications includes forming a rolled-up device comprising: a multilayer sheet in a rolled configuration having at least one turn about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer; and a core defined by a first turn of the rolled configuration. The method further includes introducing a soft magnetic material into the core.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: June 8, 2021
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Wen Huang, Zhendong Yang, Mark D. Kraman, Jimmy Ni, Zihao Ou, Qian Chen, J. Gary Eden
  • Patent number: 11024701
    Abstract: An integrated electronic component for broadband biasing that includes a monolithic substrate, a capacitor structure arranged in a trench network that extends into the substrate, and a continuous track of an electrically conducting material arranged in a crater that is formed in the substrate. The continuous track has one or several turns that have decreasing turn sections, and that are supported by a slanted peripheral wall of the crater for forming an inductor.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: June 1, 2021
    Assignee: MURATA INTEGRATED PASSIVE SOLUTIONS
    Inventors: Stéphane Bouvier, Jean-René Tenailleau
  • Patent number: 11024566
    Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: June 1, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Uchida, Akio Ono, Shinichi Kuwabara, Yasutaka Nakashiba
  • Patent number: 11018065
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a testing region and multiple first conductive lines over the testing region. The first conductive lines are electrically connected in series. The semiconductor device structure also includes multiple second conductive lines over the testing region. The second conductive lines are electrically connected in series, and the second conductive lines are physically separated from the first conductive lines. The semiconductor device structure further includes multiple magnetic structures wrapping around portions of the first conductive lines and wrapping around portions of the second conductive lines. The magnetic structures are arranged in a column.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mill-Jer Wang, Tang-Jung Chiu, Chi-Chang Lai, Chia-Heng Tsai, Mirng-Ji Lii, Weii Liao
  • Patent number: 11011295
    Abstract: An integrated circuit transformer structure includes at least two conductor groups stacked in parallel in different layers. A first spiral track is formed in the at least two conductor groups, the first spiral track included first turns of a first radius within each of the at least two conductor groups, and second turns of a second radius within each of the at least two conductor groups, the first and second turns being electrically connected. A second spiral track is formed in the at least two conductor groups, the second spiral track including third turns of a third radius within each of the at least two conductor groups and disposed in a same plane between the first and second turns in each of the at least two conductor groups.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Barry, Robert A. Groves, Venkata Nr. Vanukuru
  • Patent number: 11004811
    Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, and a RDL disposed over the transceiver. The RDL includes an antenna and a dielectric layer. The antenna is disposed over and electrically connected to the transceiver. The dielectric layer surrounds the antenna. The antenna includes an elongated portion and a via portion. The elongated portion extends over the molding, and the via portion is electrically connected to the transceiver.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Vincent Chen, Hung-Yi Kuo, Chuei-Tang Wang, Hao-Yi Tsai, Chen-Hua Yu, Wei-Ting Chen, Ming Hung Tseng, Yen-Liang Lin
  • Patent number: 10998265
    Abstract: A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 4, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Shaowu Huang, Javier A. DeLaCruz
  • Patent number: 10991653
    Abstract: In a semiconductor device, a semiconductor substrate includes a bulk layer, a buried oxide layer provided in at least a partial region on the bulk layer, and a surface single crystal layer on the buried oxide layer. An inductor is provided above a main surface side of the semiconductor substrate on which the surface single crystal layer is disposed. To increase a Q value of the inductor, a ground shield is an impurity region formed in the bulk layer below the inductor and below the buried oxide layer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: April 27, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Uchida, Yasutaka Nakashiba
  • Patent number: 10978423
    Abstract: A package assembly includes a substrate extending from a first substrate end to a second substrate end. A plurality of conductive traces extend along the substrate. A plurality of contacts are coupled with the respective conductive traces of the plurality of conductive traces. Each of the contacts of the plurality of contacts includes a contact pad coupled with a respective conductive trace of the plurality of conductive traces, and a contact post coupled with the contact pad, the contact post extends from the contact pad. A package cover layer is coupled over the plurality of contact posts. The plurality of contact posts are configured to penetrate the package cover layer and extend to a raised location above the package cover layer.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Sujit Sharan, Ravindranath V. Mahajan
  • Patent number: 10971296
    Abstract: A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen, Ho-Hsiang Chen, Min-Chie Jeng
  • Patent number: 10943719
    Abstract: In a coil component, an insulation layer covers an upper surface of a conductor pattern. Accordingly, insulating properties between the conductor pattern and a magnetic body are enhanced, and insulating properties between the conductor patterns are enhanced. In addition, in the coil component, the magnetic body enters a space between resin walls such that the insulation layer is covered. Therefore, a volume of the magnetic body above the conductor pattern is increased, and high coil characteristics are realized.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 9, 2021
    Assignee: TDK CORPORATION
    Inventors: Miyuki Asai, Hokuto Eda, Masazumi Arata, Hitoshi Ohkubo
  • Patent number: 10923577
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. The structure includes: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Johnatan A. Kantarovsky, Siva P. Adusumilli, Vibhor Jain
  • Patent number: 10916366
    Abstract: An inductor includes a body including an insulating portion formed of a plurality of layers and a magnetic portion surrounding the insulating portion and external electrodes disposed on external surfaces of the body, and a method of manufacturing the same. A coil portion is embedded in the insulating portion, and has a structure in which coil patterns formed on a plurality of layers are stacked while being connected to each other.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Yong Sam Lee
  • Patent number: 10903547
    Abstract: An electronic package includes an antenna structure and an adjustment structure arranged on a carrier structure. The antenna structure includes an antenna body and a feed line that are disposed on different layers and a conductive pillar that interconnects the layers to electrically connect the antenna body and the feed line. The adjustment structure extends from the feed line to improve the bandwidth of the antenna body.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: January 26, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ying-Wei Lu, Bo-Siang Fang, Kuan-Ta Chen
  • Patent number: 10896780
    Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 19, 2021
    Assignee: Intel IP Corporation
    Inventors: Saravana Maruthamuthu, Andreas Augustin, Andreas Wolter
  • Patent number: 10892087
    Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip with an on-chip transformer. The on-chip transformer includes a primary inductor and a secondary inductor. The primary inductor is configured to have a first-primary coil portion formed of a first patterned metal trace disposed in a first metal layer and a second-primary coil portion formed of a second patterned metal trace disposed in a second metal layer. The secondary inductor is configured to have a first-secondary coil portion formed of a third patterned metal trace that interleaves with the first patterned metal trace in the first metal layer and a second-secondary coil portion formed of a fourth patterned metal trace that interleaves with the second patterned metal trace in the second metal layer.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: January 12, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Min She, Zhendong Guo
  • Patent number: 10892646
    Abstract: An electrically conductive material configured having at least one opening of various unlimited geometries extending through its thickness is provided. The opening is designed to modify eddy currents that form within the surface of the material from interaction with magnetic fields that allow for wireless energy transfer therethrough. The opening may be configured as a cut-out, a slit or combination thereof that extends through the thickness of the electrically conductive material. The electrically conductive material is configured with the cut-out and/or slit pattern positioned adjacent to an antenna configured to receive or transmit electrical energy wirelessly through near-field magnetic coupling (NFMC). A magnetic field shielding material, such as a ferrite, may also be positioned adjacent to the antenna. Such magnetic shielding materials may be used to strategically block eddy currents from electrical components and circuitry located within a device.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: January 12, 2021
    Assignee: NuCurrent, Inc.
    Inventors: Alberto Peralta, Md. Nazmul Alam, Vinit Singh, Sina Haji Alizad
  • Patent number: 10833394
    Abstract: An electronic package and a method for fabricating the same are provided. An antenna frame, a first electronic component, and a second electronic component electrically connected to the antenna frame are disposed on a lower side of a carrying structure. An antenna structure is disposed on an upper side of the carrying structure and is electrically connected to the first electronic component. Therefore, two different types of antennas are integrated into an identical electronic package. Such the electronic package bonded to a circuit can transmit signals with two different wavelengths, even if the electronic package does not have any area increased.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: November 10, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wen-Jung Tsai, Mao-Hua Yeh, Chih-Hsien Chiu, Ying-Chou Tsai, Chun-Chi Ke
  • Patent number: 10832842
    Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Jagar Singh
  • Patent number: 10825599
    Abstract: A carrier structure includes a substrate, a first patterned circuit layer and at least one magnetic element. The substrate has a first surface and an opening passing through the substrate. The first patterned circuit layer is disposed on the first surface of the substrate and includes an annular circuit for generating an electromagnetic field. The magnetic element is disposed within the opening of the substrate, wherein the magnetic element couples the annular circuit and acts in response to the magnetic force of the electromagnetic field.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 3, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Chang-Fu Chen, Chun-Hao Chen, Kuan-Hsi Wu, Pi-Te Pan
  • Patent number: 10811339
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a uniform metal layer is formed above the second metal layer of the second wafer, the uniform metal layer is electrically connected to the second metal layer, and the uniform metal layer and the first metal layer are made of the same material. The uniform metal layer and the first metal layer simultaneously exposed by the subsequently formed TSV hole are made of the same material, the degree of over-etching is relatively easy to control in the etching process, and cross contamination of cleaning agents in the cleaning process can be avoided. In addition, when the interconnection layer is electrically connected to the first metal layer and the uniform metal layer, since the uniform metal layer and the first metal layer are made of the same material, the interconnection layer has better contact performance with the two.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 20, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tian Zeng
  • Patent number: 10804878
    Abstract: There are provided an acoustic resonator module, and a method of manufacturing the same. An acoustic resonator module includes a resonating part disposed on a substrate and an inductor electrically connected to the resonating part, and having at least a portion disposed to be spaced apart from the substrate.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 13, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: June Kyoo Lee, Chul Soo Kim, Won Kyu Jeung
  • Patent number: 10784192
    Abstract: Semiconductor devices having inductive structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a substrate and at least one circuit component coupled to the substrate. The semiconductor device can further include an inductive structure carried by the substrate and having a stack of alternating first and second layers. In some embodiments, the first layers comprise an oxide material and the second layers each include a coil of conductive material. The coils of conductive material can be electrically coupled (a) together to form an inductor and (b) to the at least one circuit component.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: James E. Davis, Kevin G. Duesman
  • Patent number: 10778211
    Abstract: A switching circuit includes first to (N+1)th input/output terminals and first to Nth field-effect transistors (FETs), for an integer N of two or more. When one of a source end and a drain end is referred to as a first end and another one is referred to as a second end, the first input/output terminal is electrically connected to the first ends of all of the first to Nth FETs. For each integer i of one to N, the second end of the ith FET is electrically connected to the (i+1)th input/output terminal. For at least one integer j of one to N, a combination in which an inductor component and a resistor component are electrically connected in series to each other is disposed between the first and second ends of the jth FET such that the combination is electrically connected in parallel to the jth FET.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: September 15, 2020
    Assignee: MURATA MANUFACTURING CO., LTD
    Inventor: Ken Kishimoto
  • Patent number: 10756727
    Abstract: A switching circuit includes a first input/output terminal, a second input/output terminal, a third input/output terminal, a first transistor, a second transistor, an inductor and a resistor. The first transistor is electrically connected between the first input/output terminal and the second input/output terminal. The second transistor is electrically connected between the first input/output terminal and the third input/output terminal. The inductor and the resistor are electrically connected in series with each other between the second input/output terminal and the third input/output terminal.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 25, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Ken Kishimoto
  • Patent number: 10748810
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive line over a substrate. The method includes forming a first protection cap over a first portion of the first conductive line. The first protection cap and the first conductive line are made of different conductive materials. The method includes forming a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The method includes forming a first opening in the first photosensitive dielectric layer and over the first protection cap. The method includes forming a conductive via structure and a second conductive line over the first conductive line. The conductive via structure is in the first opening and over the first protection cap, and the second conductive line is over the conductive via structure and the first photosensitive dielectric layer.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li Yang, Wei-li Huang, Sheng-Pin Yang, Chi-Cheng Chen, Hon-Lin Huang, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 10749524
    Abstract: An isolator circuit according to the present invention includes a first isolator, an AD converter, and a second isolator. The first isolator is configured to galvanically isolate a first terminal and a second terminal from each other. The first isolator receives an input pulse signal and outputs an output pulse signal to the second terminal. The AD converter is configured to output a digital signal corresponding to a duty ratio of the output pulse signal. The second isolator is configured to galvanically isolate the second terminal and the third terminal from each other. The second isolator is configured to receive the digital signal and outputs a feedback pulse signal to the third terminal.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: August 18, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takahiro Takamori, Kanji Kitamura, Tetsuya Masaoka
  • Patent number: 10741651
    Abstract: A terminal structure of an insulated gate bipolar transistor (IGBT) device includes a main junction, a cutoff ring, and a plurality of terminal rings disposed between the main junction and the cutoff ring, and a resistive element having a first terminal electrically connected to the main junction, a second terminal electrically connected to the cutoff ring, and a plurality of intermediate terminals electrically connected to the terminal rings, respectively. The resistive element is configured to uniformly distribute the lateral voltage between the main junction and the cutoff ring to the terminal rings to ensure that the peak electric field is uniformly distributed across the terminal structure, thereby reducing the terminal structure area and package cost of the IGBT device, while improving the device reliability.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 11, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Jian Liu
  • Patent number: 10734331
    Abstract: In a described example, an integrated circuit includes: a semiconductor substrate having a first surface and an opposite second surface; at least one dielectric layer overlying the first surface of the semiconductor substrate; at least one inductor coil in the at least one dielectric layer with a plurality of coil windings separated by coil spaces, the at least one inductor coil lying in a plane oriented in a first direction parallel to the first surface of the semiconductor substrate, the at least one inductor coil electrically isolated from the semiconductor substrate by a portion of the at least one dielectric layer; and trenches extending into the semiconductor substrate in a second direction at an angle with respect to the first direction, the trenches underlying the inductor coil and filled with dielectric replacement material.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Barry Jon Male, Rajarshi Mukhopadhyay
  • Patent number: 10734156
    Abstract: An inductor component including an inductor electrode includes an insulating layer and an outer electrode for external connection formed on the upper surface of the insulating layer. The inductor electrode includes a metal pin for input/output that has an upper end surface connected to the outer electrode and that is embedded in the insulating layer. The outer electrode includes a base electrode formed on the upper surface of the insulating layer and composed of a conductive paste, and a surface electrode formed on the base electrode by plating. The surface electrode is formed such that the area of a cross section thereof perpendicular to the thickness direction on an outer layer side away from the base electrode is larger than the area of a cross section thereof perpendicular to the thickness direction on an inner layer side close to the base electrode.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: August 4, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Shinichiro Banba, Mitsuyoshi Nishide, Norio Sakai
  • Patent number: 10720411
    Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Tetsuya Iida
  • Patent number: 10720487
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an etch stop layer over a semiconductor substrate and forming a magnetic element over the etch stop layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes forming a conductive line over the isolation element. In addition, the method includes forming a dielectric layer over the conductive line, the isolation element, and the magnetic element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Chi-Cheng Chen, Hon-Lin Huang, Wei-Li Huang, Chun-Yi Wu, Chen-Shien Chen
  • Patent number: 10713646
    Abstract: A portable communication device is provided. The portable communication device includes near field communication (NFC) circuitry; wireless charging circuitry; magnetic secure transmission (MST) circuitry; a flexible printed circuit board (FPCB) including a first substrate layer and a second substrate layer; an NFC coil electrically connected with the NFC circuitry, the NFC coil including a first portion formed on the first substrate layer and a second portion formed on the second substrate layer; a wireless charging coil electrically connected with the wireless charging circuitry, the wireless charging coil including a third portion formed on the first substrate layer and a fourth portion formed on the second substrate layer; and an MST coil electrically connected with the MST circuitry, the MST coil including a fifth portion formed on the first substrate layer and a sixth portion formed on the second substrate layer.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hee-Dong Lee, Chul-Hyung Yang, Ji-Woo Lee
  • Patent number: 10714410
    Abstract: A semiconductor structure including a substrate, a first well, a field oxide layer, a first conductive line and a second conductive line is provided. The substrate has a first conductivity type. The first well is formed on the substrate and has a second conductivity type. The field oxide layer is disposed on the first well. The first conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The second conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The first conductive line is spaced apart from the second conductive line.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: July 14, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Hsiao-Ling Chiang, Wen-Hsin Lin
  • Patent number: 10706993
    Abstract: A chip part is provided that includes a substrate in which an element region and an electrode region are set, an insulating film (a first insulating film and a second insulating film) which is formed on the substrate and which selectively includes an internal concave/convex structure in the electrode region on a surface, a first connection electrode and a second connection electrode which include, at a bottom portion, an anchor portion entering the concave portion of the internal concave/convex structure and which include an external concave/convex structure on a surface on the opposite side and a circuit element which is disposed in the element region and which is electrically connected to the first connection electrode and the second connection electrode.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 7, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Takuma Shimoichi, Yasuhiro Kondo, Keishi Watanabe, Takamichi Torii, Katsuya Matsuura
  • Patent number: 10699266
    Abstract: An electronic device is provided. The electronic device includes a housing; a plurality of coils that are disposed on a first layer within the housing; a plurality of other coils disposed on a second layer substantially parallel to the first layer; a first conductor that connects an end point of a first coil of the plurality of coils and a start point of a second coil of the plurality of other coils and conducts a current from the end point of the first coil to the start point of the second coil; and a second conductor that connects a start point of a third coil adjacent to an outer side of the first coil of the plurality of coils and an end point of the second coil and conducts the current to be applied from the end point of the second coil to the start point of the third coil, wherein the first conductor and the second conductor induce a directional magnetic field when the current flows.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hee-Dong Lee, Chul-Hyung Yang, Ji-Woo Lee
  • Patent number: 10700161
    Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 30, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin
  • Patent number: 10700159
    Abstract: A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel IP Corporation
    Inventors: Veronica Sciriha, Georg Seidemann
  • Patent number: 10692808
    Abstract: In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 23, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Renukprasad Hiremath, Hyeokjin Lim, Foua Vang, Xiangdong Chen, Venugopal Boynapalli
  • Patent number: 10685911
    Abstract: The present disclosure provides a semiconductor package, including a first semiconductor structure, a first bonding dielectric over the first semiconductor structure and surrounding a first bonding metallization structure, a through via over the first bonding dielectric, and a passive device passive device electrically coupled to the through via and the first bonding metallization structure. The present disclosure also provides a method for manufacturing a semiconductor package, including providing a first die, bonding a second die with the first die, wherein the second die partially covers the first die thereby forming a gap over an uncovered portion of the first die, filling the gap over the first die with dielectric, forming a through dielectric via (TDV) in the filled gap, and forming a passive device over the second die and the TDV.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Chen-Hua Yu
  • Patent number: 10672860
    Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
  • Patent number: 10671204
    Abstract: Provided is a novel touch panel that is highly convenience or reliable, a novel data processor that is highly convenient or reliable, a novel touch panel, a novel data processor, or a novel semiconductor device. The touch panel includes a sensor element and a display element. The sensor element includes a first conductive film and a second conductive film. The display element includes a layer containing a liquid crystal material and a third conductive film which is provided so that an electric field controlling the alignment of the liquid crystal material contained in the layer can be applied between the first conductive film and the third conductive film.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: June 2, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroyuki Miyake
  • Patent number: 10658973
    Abstract: Techniques for co-tuning of inductance (L) and capacitance (C) in a VNCAP-based LC tank oscillator are provided. In one aspect, an LC tank oscillator includes: a capacitor including at least two metal layers, each metal layer having metal fingers that are interdigitated, wherein an orientation of the metal fingers alternates amongst the at least two metal layers; and an inductor on the capacitor. Inter-layer vias can be present interconnecting the at least two metal layers creating conductive loops between the metal fingers, wherein an arrangement of the inter-layer vias in an area between the at least two metal layers is configured to co-tune both inductance and capacitance in the LC tank oscillator. A method of operating an LC tank oscillator and a method of co-tuning inductance and capacitance in an LC tank oscillator are also provided.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Zheng Xu, Hung Tran, Qianwen Chen, Ruqiang Bao
  • Patent number: 10637528
    Abstract: An inductor circuit includes first inductive circuit, second inductive circuit, and third inductive circuit. First inductive circuit at receiver side has a first end coupled to a first port of an antenna and a second end coupled to an input port of a receiving circuit. Second inductive circuit at transmitter side has a first end and a second end respectively coupled to output ports of a power amplifier. Third inductive circuit at antenna side has a first end coupled to a first port of the antenna and having a second end. Second inductive circuit and the third inductive circuit are disposed on an outer ring to form a ring shape and the third inductive circuit is disposed on an inner ring within the outer ring to form a spiral shape. Third inductive circuit is disposed between the second inductive circuit and the first inductive circuit.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: April 28, 2020
    Assignee: Audiowise Technology Inc.
    Inventor: Wen-Shun Liu
  • Patent number: 10609813
    Abstract: Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, Fern Nee Tan, Khang Choong Yong, Jiun Hann Sir
  • Patent number: 10601222
    Abstract: A T-coil IC includes a first inductor on an Mx layer. The first inductor has n turns, where n is at least 1? turns. The T-coil IC further includes a second inductor on an Mx?1 layer. The second inductor has n turns. The first inductor and the second inductor are connected together at a node. The first inductor on the Mx layer and the second inductor on the Mx?1 layer are mirror symmetric to each other. The T-coil IC further includes a center tap on an Mx?2?y layer, where y?0. The center tap is connected to the first inductor and the second inductor by a via stack at the node. In one configuration, n is 1?+0.5z turns, where z?0. An effective bridge capacitance of the T-coil IC may be approximately 25 fF.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Siqi Fan