Abstract: In one embodiment, an integrated circuit die includes first and second inductor structures, a first ground conductor, a second ground conductor and a conductive trace. The first ground conductor provides a first ground pathway for the first inductor structure. The second ground conductor provides a second ground pathway for the second inductor structure. The conductive trace coupled between the first and second ground conductors may magnetically decouple the first and second inductor structures. In addition, the integrated circuit die may also include conductive guard ring structures that surround the first and second inductor structures. One of the conductive guard ring structures may be connected to the first grounding pathway and the other conductive guard ring structure may be connected to the second grounding pathway. The conductive guard ring structures may further magnetically decouple the first and second inductor structures.

Abstract: An inductive touch module and an inductive touch display device and the manufacturing method thereof are disclosed.

Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

Abstract: An embedded magnetic component transformer includes first, second, and auxiliary electrical windings in an insulating substrate including conductive vias joined together by conductive traces. The first electrical windings are divided by a tap terminal into first and second winding portions, which are interleaved with one another and energized by separate transistors. Heat generated by the first and second winding portions is transferred more equally to the separate transistors. Equal or substantially equal path lengths between each of the transistors and the first electrical windings improve flux balance allowing the transistors to conduct for equal or substantially equal times during a switching cycle. Thus, the switching cycle of the embedded transformer is more symmetric with respect to each of the transistors and winding portions, improving the electrical characteristics of the transformer.

Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.

Abstract: A packaged RF amplifier device includes a transistor and an output circuit. The transistor includes a control terminal and first and second current carrying terminals. The output circuit is coupled between the first current carrying terminal and an output lead. The output circuit includes first and second inductive elements coupled in series. The first inductive element, which may be a first bondwire array or an integrated inductance, is coupled between the first current carrying terminal and a node. The second inductive element, which includes a second bondwire array, is coupled between the node and the output lead. The device also includes a shunt circuit with a shunt capacitor and a third bondwire array coupled between the first current carrying terminal and the shunt capacitor. The first and second inductive elements and the third bondwire array are configured to have a desired mutual inductance.

Abstract: In some examples, device includes an integrated circuit (IC) inside a first insulating layer, an inductor, and a second insulating layer arranged between the first insulating layer and the inductor. The first insulating layer shares an interface with the second insulating layer, and the inductor is attached to the second insulating layer. The device further includes a conductive path configured to conduct electricity between the IC and the inductor, wherein the conductive path is inside the second insulating layer.

Abstract: An integrated circuit includes a first inductor, a second inductor, and a blocker. The first inductor is disposed in a metal layer, and the second is disposed in the metal layer. The blocker is disposed on the metal layer and located between the first inductor and the second inductor. The blocker is configured to block coupling occurring between the first inductor and the second inductor.

Abstract: Passive electrical devices are described with a polymer carrier. In one example, a conductive layer is formed over a polymer substrate in a pattern to form a passive electrical device and at least two terminals of the device. A plurality of external connection pads are connected to the terminals of the device.

Abstract: A semiconductor device includes: a substrate; a first layer that is stacked on the substrate and includes an inductor; and a bump group that is arranged above the first layer, wherein the bump group includes a plurality of bumps that are arranged under a predetermined rule, and at least one bump that is different from the plurality of bumps and whose center does not overlap the inductor when the semiconductor device is viewed in a plan view from a direction vertical to a plane on which the bump group is provided.

Abstract: This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.

Abstract: A system, method, and device for improving the functioning of security tags for use with merchandise are provided. A security tag device, to be used in conjunction with a tag monitoring device, may be provided with a product. The product may be conductive or may have metallic packaging. The security tag may include a planar dielectric substrate having a first side and an opposing side. An electronic article surveillance (EAS) circuit may be placed on the first side of the planar dielectric substrate. A ferrite sheet having a first side and an opposing side may be coupled to the opposing side of the planar dielectric substrate. A metal backing sheet may be coupled to the opposing side of the ferrite sheet. The planar dielectric substrate may be centered or offset on the ferrite sheet and the ferrite sheet may be centered or offset on the metal backing sheet.

Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.

Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer, wherein a top surface of the metal structure is level with a top surface of the stress reduction layer.

Abstract: A series stacked, solenoidally wound, multipath inductor includes a plurality of turns disposed about a center region on two layers. The turns on the two layers have corresponding geometry therebetween. Each of the plurality of turns includes two or more segments that extend length-wise along the turns. The segments have positions that vary from an innermost position relative to the center region and an outermost position relative to the center region. A cross-over architecture is configured to couple the segments of a turn on one layer with the segments on a turn on another layer to form segment paths that have a substantially same length for all segment paths in a segment path grouping between the two layers.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the first connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip.

Abstract: A circuit including a die and an integrated passive device. The die includes a first substrate and at least one active device. The integrated passive device includes a first layer, a second substrate, a second layer and an inductance. The inductance includes vias, where the vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars, where the pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.

Abstract: In accordance with the disclosed semiconductor chip and multi-chip module, signal transmission is made possible between semiconductor chips that are placed on a plane so as to be adjacent to each other through inductive coupling without affecting other coils such as in an oscillation circuit or an antenna circuit for RF communication. A multilayer solenoid coil, where a plane of the coil formed in a multilayer wiring structure in a semiconductor body is parallel to a main surface of the semiconductor body, is formed along at least one side end surface of the semiconductor body.

Abstract: Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack.

Abstract: Disclosed herein are methods of forming one or more transducer elements in a transducer region of a slider by electrodepositing one or more metal ions from an ionic liquid solvent, and related sliders.

Abstract: An active component of an integrated voltage regulator (IVR) circuit is deployed within an IC device for regulating an operating voltage thereof. An interposer interconnects the IC device with a power source. A passive inductive component of the IVR circuit is deployed upon a surface of the IC device or the interposer. The inductive component has a magnetic core and a winding (e.g., wire-bond), wound about the magnetic core.

Abstract: A varainductor includes a spiral inductor, a ground ring, and a floating ring. The floating ring is disposed between the ground ring and the spiral inductor and surrounds a ring portion of the spiral inductor. A switching element, controlled by a switch control signal, selectively electrically connects the ground ring to the floating ring. The switching element includes one or more switches. The one or more switches are controlled by one or more signals of the switch control signal to adjust the inductance level of the varainductor.

Abstract: Some implementations provide an integrated device (e.g., semiconductor device) that includes a substrate and an inductor in the substrate. In some implementations, the inductor is a solenoid inductor. The inductor includes a set of windings. The set of windings has an inner perimeter. The set of windings includes a set of interconnects and a set of vias. The set of interconnects and the set of vias are located outside the inner perimeter of the set of windings. In some implementations, the set of windings further includes a set of capture pads. The set of interconnects is coupled to the set of vias through the set of capture pads. In some implementations, the set of windings has an outer perimeter. The set of pads is coupled to the set of interconnects such that the set of pads is at least partially outside the outer perimeter of the set of windings.

Abstract: Power conversion systems, filter circuits and integrated filter resistor and inductor apparatus are presented, in which a damping resistor is integrated with a filter inductor by winding joined resistor winding portions proximate to one another at least partially around a filter inductor core leg to form an integrated filter resistor and inductor apparatus for interconnection with filter capacitors to provide an input filter or an output filter for a motor drive or other power conversion system.

Abstract: There are disclosed impedance matching networks and technique for impedance matching to microwave power transistors. Distributed capacitor inductor networks are used so as to provide a high degree of control and accuracy, especially in terms of inductance values, in comparison to existing lumped capacitor arrangements. The use of bond wires is reduced, with inductance being provided primarily by microstrip transmission lines on the capacitors.

Abstract: A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices.

Abstract: Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view.

Abstract: Various embodiments may relate to a component arrangement, including a carrier, wherein at least one electronic component is formed in the carrier, a first metallization layer over the carrier, wherein the first metallization layer has a first metallic coupling structure, which is electrically coupled to the at least one electronic component, a second metallization layer over the first metallization layer, wherein the second metallization layer has a second metallic coupling structure, wherein the first metallic coupling structure is coupled to the second metallic coupling structure by means of at least one via, and a plurality of additional vias, which extend at least between the first metallization layer and the second metallization layer and are electrically conductively coupled to one another in such a way that they form a coil, which has a coil region which is at an angle to the main processing surface of the carrier.

Abstract: The present disclosure relates to power management apparatuses and systems utilizing synchronous common coupling. A power management apparatus may include a synchronous common coupling, a plurality of ports, and a plurality of electrically isolated stacks connected through the synchronous common coupling. Each electrically isolated stack may include at least one stage, each stage including a source/load bridge, a flux bridge, and a direct current (DC) bus. The source/load bridge may be connected to a source or load through one of the plurality of ports, the flux bridge may be connected to an electrically isolated winding in the synchronous common coupling, and the flux bridge may be connected to the source/load bridge through the DC bus.

Abstract: An integrated inductor structure includes a capacitor, a guard ring, a patterned shield, and an inductor. The guard ring is coupled to the capacitor. The patterned shield is coupled to the guard ring through the capacitor, such that the patterned shield is floating. The inductor is disposed above the guard ring and the patterned shield.

Abstract: Semiconductor component comprising at least two semiconductor regions are disclosed. In one embodiment the semiconductor regions of the semiconductor component are electrically isolated from one another by an insulator, and a deposited, patterned, metallic layer extends over the semiconductor regions and over the insulator.

Abstract: A fuse device having contacts configured to reduce electro-migration is disclosed. In some exemplary embodiments, the fuse structure includes an anode disposed at a first end and a cathode disposed at a second end. A fuse link extends between and contacts the anode and the cathode. A boundary between the fuse link and the cathode has a center point, and each connector of a plurality of cathode connectors has a center point that is an equal distance from the center point of the boundary between the fuse link and the cathode. In some such embodiments, each connector of the plurality of cathode connectors is a different size than an anode connector, whereas in some such embodiments, each connector of the plurality of cathode connectors is substantially a same size as the anode connector along at least one axis.

Abstract: A high-frequency transmission device includes first and second resonators as ring-shaped wires each having an opening part at a part thereof, first and second input/output terminals each electrically connected to both resonators, a first ground shield formed on a plane different from planes on which both resonators are arranged, a second ground shield formed on a plane different from the planes on which both resonators and the first ground shield are arranged, and first and second ground wires each formed to surround peripheries of both resonators. The ground shields and the ground wires are respectively connected to each other. A dielectric wire is present between both ground wires, and the ground wires are not electrically connected to each other.

Abstract: A method of forming a semiconductor structure includes forming a seed layer over a top surface of a substrate and a protect layer over a top surface of the seed layer. The method also includes forming a magnetic film on a top surface of the protect layer and a top surface of the substrate in at least one opening formed in the seed layer and the protect layer. The method further includes forming at least one patterned magnetic feature on the top surface of the substrate by electro-etching the magnetic film, wherein the seed layer provides a self-stop for the electro-etching of the magnetic film.

Abstract: The present disclosure relates to a multi-layer substrate structure with an embedded die to miniaturize designs and improve performance. The multi-layer substrate structure includes a core layer having a cavity and a die mounted within the cavity. The die has a die body, a die conductive element on a top surface of the die body, and a dielectric layer over the die conductive element. The multi-layer substrate structure also includes a substrate conductive element formed over a portion of a top surface of the core layer and extending over at least a portion of the die conductive element. Overlapping portions of the die conductive element and the substrate conductive element are separated by the dielectric layer and form an electronic component.

Abstract: An integrated circuit contains three thin film resistors over a dielectric layer. The first resistor body includes only a bottom thin film layer and the first resistor heads include the bottom thin film layer, a middle thin film layer and a top thin film layer. The second resistor body and heads include all three thin film layers. The third resistor body does not include the middle thin film layer. The three resistors are formed using two etch masks.

Abstract: A semiconductor device comprises a guarded circuit. The semiconductor device also comprises a guard ring surrounding the guarded circuit. The semiconductor device further comprises a resonant circuit coupled with the guard ring. The resonant circuit comprises an input node coupled with the guard ring. The resonant circuit also comprises an inductor. The resonant circuit further comprises a capacitor coupled with the inductor. The resonant circuit additionally comprises a ground node configured to carry a ground voltage. The inductor and the capacitor are coupled between the input node and the ground node.

Abstract: In a communication control device in which an antenna electrode having an antenna connected thereto, a power supply circuit, and a communication circuit are mounted on a mounting board, the antenna electrode is disposed at one corner portion on a principal surface of the mounting board, the communication circuit is disposed on a side of a first side of the principal surface that shares the corner portion, and the power supply circuit is disposed on a side of a second side facing the first side. Further, a first signal path connecting the antenna electrode and the communication circuit extends along the first side, and a second signal path connecting the antenna electrode and the power supply circuit extends along a third side that shares the corner portion and is perpendicular to the first side.

Abstract: An electrostatic discharge protection device including a silicon controlled rectifier. In one example, the silicon controlled rectifier includes a first n-type region located in a semiconductor substrate. The silicon controlled rectifier also includes a first p-type region located adjacent the first n-type region in the semiconductor substrate. The silicon controlled rectifier further includes an n-type contact region and a p-type contact region located in the first n-type region. The silicon controlled rectifier also includes an n-type contact region and a p-type contact region located in the first p-type region. The silicon controlled rectifier further includes a blocking region having a higher resistivity than the first p-type region. The blocking region is located between the n-type contact region and the p-type contact region in the first p-type region for reducing a trigger voltage of the silicon controlled rectifier.

Abstract: An optoelectronic semiconductor component includes an optoelectronic thin-film chip; and a thermally conductive and electrically insulating element, wherein both the thin-film chip and the element are embedded in a molded body, a top surface of the thin-film chip and a bottom surface of the element are not covered by the molded body, the top surface of the thin-film chip is approximately flush with a top surface of the molded body, the bottom surface of the element is approximately flush with a bottom surface of the molded body, the molded body includes a first embedded conductor structure and a second embedded conductor structure, and the first conductor structure and the second conductor structure extends to the bottom surface of the molded body.

Abstract: A multi-layer ground shield structure of interconnected elements is disclosed. The ground shield structure may include a first patterned layer of a ground shield structure, a second patterned layer of the ground shield structure, and a spacer between the first patterned layer and the second patterned layer. The first patterned layer includes first conductive elements interconnected within the first patterned layer according to a first pattern. The second patterned layer includes second conductive elements interconnected within the second patterned layer according to a second pattern.

Abstract: An electrostatically tunable magnetoelectric inductor including: a substrate; a piezoelectric layer; and a magnetoelectric structure comprising a first electrically conductive layer, a magnetic film layer, a second electrically conductive layer, and recesses formed so as to create at least one electrically conductive coil around the magnetic film layer; with a portion of the substrate removed so as to enhance deformation of the piezoelectric layer. Also disclosed is a method of making the same. This inductor displays a tunable inductance range of >5:1 while consuming less than 0.5 mJ of power in the process of tuning, does not require continual current to maintain tuning, and does not require complex mechanical components such as actuators or switches.

Abstract: A 3-dimensional (3-D) magnetic core device includes a substrate, a first magnetic shell formed on the substrate, and a first group of conductive traces embedded in a first insulator layer formed on the first magnetic shell. A magnetic core plane is formed on the first insulator layer, and a second group of conductive traces are embedded in a second insulator layer formed on the magnetic core plane. A second magnetic shell is formed on the second insulator layer, and the first and second group of conductive traces are conductively coupled by using conductive vias.

Abstract: Structures and methods for implementing high performance symmetric multi-port inductors are provided. The multiport inductor structure includes a plurality of conductors which are structured and arranged in turns to obtain symmetry between a plurality of selected input terminals connecting to respective ones of the plurality of conductors.

Abstract: An embodiment device package includes a semiconductor device die comprising a passivation layer at a top surface, a first conductive line over the passivation layer and electrically connected to the device die, and a second conductive line over the passivation layer and electrically connected to the device die. The first conductive line is thicker than the second conductive line, and the first conductive line and the second conductive line are formed in a same device package layer.

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate; and a plurality of parallel first conductive layers formed on the substrate. The semiconductor structure also includes a composite magnetic structure having a plurality of magnetic layers and a plurality of insulation layers with a sandwich arrangement formed on a portion of the substrate and portions of surfaces of the plurality of first conductive layers. Further, the semiconductor structure includes a plurality of first conductive vias and a plurality of second conductive vias formed on the first conductive layers at both sides of the composite magnetic structure. Further, the semiconductor structure also includes a plurality of second conductive layers formed on a top surface of the composite magnetic structure, top surfaces of the first conductive vias, and top surfaces of the second conductive vias to form at least one coil structure wrapping around the composite magnetic structure.

Abstract: A semiconductor package includes an output inductor placed over a support substrate, a power semiconductor die having a bottom surface situated on the support substrate and a top surface having an active region, where the output inductor is coupled to the active region on the top surface of the support substrate, and where the support substrate includes a plurality of bar vias. The output inductor is a packaged component having at least two leads in electrical connection with the active region of the power semiconductor die. The support substrate further includes routing conductors in electrical connection with the active region of the power semiconductor die. The power semiconductor die includes a control transistor and a sync transistor connected in a half-bridge.

Abstract: A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil.

Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.