Abstract: A semiconductor device includes a plurality of first wires formed in a first layer, a plurality of second wires formed to intersect the plurality of first wires in a second layer stacked on the first layer, a plurality of first vias formed at intersections of the plurality of first wires and the plurality of second wires, and an inductor formed in a third layer stacked on the first layer and the second layer.

Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a magnetic component, a bare power chip and a conductive set. The magnetic component includes a first surface and a second surface opposite to each other. The bare power chip is disposed on the magnetic component and includes a third surface and a fourth surface opposite to each other. The conductive set is disposed on the magnetic component and electrically connected with the magnetic component and the bare power chip. The third or fourth surface of the bare power chip is at least partially attached on the first or second surface of the magnetic component, and at least partially included in a projected envelopment of the corresponding first or second surface of the magnetic component, so as to facilitate the magnetic component to support the bare power chip.

Abstract: A semiconductor device includes a substrate having a surface and a thin film inductor formed on top of the surface of the substrate and having a conductive wire, a first stack of magnetic layers and a second stack of magnetic layers. The conductive wire is disposed between the first and second stacks of magnetic layers, and the thin film inductor is configured to provide a magnetic field in the first and second stacks of magnetic layers in response to a current passing through the conductive wire. The first stack of magnetic layers has a first edge portion extending in parallel with a longitudinal axis of the conductive wire, and the second stack of magnetic layers has a second edge portion that covers the first edge portion conformally and is separated from the first edge portion by an insulation layer.

Abstract: A semiconductor device includes a substrate having a first region, a second region, a first buffer region, and a second buffer region. A plurality of conductive lines is disposed on the first region of the substrate. An inductor is disposed on the second region of the substrate, and a dummy pattern is disposed on the first buffer region of the substrate. The first buffer region is provided between the first region and the second region. The second buffer region is provided between the first buffer region and the second region.

Abstract: A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.

Abstract: A semiconductor device package is provided, including a semiconductor device, a molding material, and a conductive slot. The molding material surrounds the semiconductor device. The conductive slot is positioned over the molding material and having an opening and at least two channels connecting the opening to the edges of the conductive slot.

Abstract: An integrated transformer can be fabricated to include multiple first conductors, a magnetic core, and multiple second conductors. The first conductor can be fabricated within a first layer of a semiconductor layer stack. The magnetic core can be fabricated within multiple second layers, below the first layer, of the semiconductor layer stack. The multiple second conductors can be fabricated within a third layer, below the second layer, of the semiconductor layer stack. The multiple first conductors can be connected to the multiple second conductors to form a primary winding of the integrated transformer. The integrated transformer can additionally include a coupling element to wrap around the magnetic core to form a secondary winding of the integrated transformer.

Abstract: A coil according to one embodiment of the present invention is a coil in which a first electric wire on an inner peripheral side and a second electric wire on an outer peripheral side are wound side by side to connect ends of the electric wires with each other, and the coil includes a first region where the first electric wire abuts on the second electric wire of another adjacent turn and separates from the second electric wire of a same turn.

Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

Abstract: Disclosed herein is a coil component that includes first and second coil parts each spirally wound in a plurality of turns in directions opposite to each other. An innermost turn of the first coil part is radially divided into first and second conductor parts by a spiral slit, and at least an innermost turn of the second coil part is radially divided into third and fourth conductor parts by a spiral slit. The first conductor part is positioned radially inward of the second conductor part, and the third conductor part is positioned radially inward of the fourth conductor part. The inner peripheral end of the first conductor part is connected to the inner peripheral end of the fourth conductor part, and the inner peripheral end of the second conductor part is connected to the inner peripheral end of the third conductor part.

Abstract: A semiconductor structure including a plurality of semiconductor dies, an insulating encapsulant, and a redistribution structure disposed on the semiconductor dies and the insulating encapsulant is provided. The insulating encapsulant is interposed between adjacent two of the semiconductor dies, and the insulating encapsulant includes a first portion wider than a second portion connected to the first portion. The redistribution structure includes a dielectric layer overlying the insulating encapsulant, and a conductive trace overlying the dielectric layer and opposite to the insulating encapsulant. The conductive trace includes at least one turn and is connected to a conductive terminal of one of the adjacent two of the semiconductor dies, and the conductive trace extends across the dielectric layer to reach another conductive terminal of another one of the adjacent two of the semiconductor dies.

Abstract: A semiconductor device includes a semiconductor substrate, a multilayer wiring layer, a first inductor element, and a first capacitor element. The multilayer wiring layer is formed on the semiconductor substrate. The first inductor element and the first capacitor element are formed in the multilayer wiring layer. The first capacitor element is formed in the same layer as a layer in which the first inductor element is formed. The first capacitor element is formed inside the first inductor element in plan view.

Abstract: A semiconductor device is disclosed including one or more semiconductor dies mounted on substrate. Each semiconductor die may be formed with a ferromagnetic layer on a lower, inactive surface of the semiconductor die. The ferromagnetic layer pulls the semiconductor dies down against each other and the substrate during fabrication to prevent warping of the dies. The ferromagnetic layer also balances out a mismatch of coefficients of thermal expansion between layers of the dies, thus further preventing warping of the dies.

Abstract: An inductor includes a body including a support member, a coil, and an encapsulant, and external electrodes on external surfaces of the body. The coil in the body may be formed so that a plurality of coil patterns are continuously formed, wherein the coil pattern includes first and second coil layers, and the encapsulant extends downward between adjacent coil patterns to be between first coil layers of adjacent coil patterns.

Abstract: A medicament for preventing or treating heart failure containing an antagonist of the corticotropin releasing hormone receptor 2 as an active ingredient.

Abstract: A semiconductor module includes a semiconductor chip including wiring formed over a semiconductor element such as a MISFET, a sealing resin part MR covering the semiconductor chip such that the wiring is exposed, and an inductor formed in redistribution wiring. The inductor overlaps with the sealing resin part covering at least a side surface of the semiconductor chip in plan view.

Abstract: A semiconductor component may have a semiconductor body and an electrically conductive carrier layer. The semiconductor body may include a first semiconductor layer and a second semiconductor layer, a first main face and a second main face, situated opposite the first main face, wherein the first main face is formed by a surface of the first semiconductor layer and the second main face is formed by a surface of the second semiconductor layer. The semiconductor body may further include at least one side face connecting the first main face to the second main face. The electrically conductive carrier layer may regionally cover the second main face the carrier layer is structured in such a way that it has at least one contact-free depression. Furthermore, a method for producing such a semiconductor component is disclosed.

Abstract: A method of manufacturing a laminated coil component is a method of manufacturing a laminated coil component provided with a laminate obtained by laminating a coil conductor forming a spiral coil and an insulator layer. The method of manufacturing a laminated coil component includes a step of providing a conductor pattern configured to become a coil conductor on a green sheet configured to become an insulator layer, and a step of laminating a plurality of green sheets provided with the conductor pattern. The conductor pattern includes a pair of first side surfaces opposed to each other in an orthogonal direction orthogonal to a laminating direction of the green sheet. At the step of laminating a plurality of green sheets, a depression is formed on at least one of the pair of first side surfaces.

Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.

Abstract: A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first conductive line and a first inter metal dielectric (IMD) layer. The first substrate is over the first gate layer. The first shielding layer is over the first substrate. The first conductive line is over the first shielding layer. The first IMD layer is between the first substrate and the first conductive line.

Abstract: A planar coil element of the present invention includes an insulating base film having a first surface and a second surface opposite to the first surface, a first conductive pattern deposited on the first surface side of the insulating base film, and a first insulating layer covering the first conductive pattern on the first surface side, in which the first conductive pattern includes a core body and a widening layer deposited by plating on the outer surface of the core body, and the ratio of the average thickness of the first conductive pattern to the average circuit pitch of the first conductive pattern is ½ or more and 5 or less.

Abstract: In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.

Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer.

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.

Abstract: A rolled-up electromagnetic component for on-chip applications comprises: a multilayer sheet in a rolled configuration comprising at least one turn about a longitudinal axis; a core defined by a first turn of the rolled configuration; and a soft magnetic material disposed within the core, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. A method of making a rolled-up electromagnetic component for on-chip applications includes forming a rolled-up device comprising: a multilayer sheet in a rolled configuration having at least one turn about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer; and a core defined by a first turn of the rolled configuration. The method further includes introducing a soft magnetic material into the core.

Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.

Abstract: An integrated electronic component for broadband biasing that includes a monolithic substrate, a capacitor structure arranged in a trench network that extends into the substrate, and a continuous track of an electrically conducting material arranged in a crater that is formed in the substrate. The continuous track has one or several turns that have decreasing turn sections, and that are supported by a slanted peripheral wall of the crater for forming an inductor.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a testing region and multiple first conductive lines over the testing region. The first conductive lines are electrically connected in series. The semiconductor device structure also includes multiple second conductive lines over the testing region. The second conductive lines are electrically connected in series, and the second conductive lines are physically separated from the first conductive lines. The semiconductor device structure further includes multiple magnetic structures wrapping around portions of the first conductive lines and wrapping around portions of the second conductive lines. The magnetic structures are arranged in a column.

Abstract: An integrated circuit transformer structure includes at least two conductor groups stacked in parallel in different layers. A first spiral track is formed in the at least two conductor groups, the first spiral track included first turns of a first radius within each of the at least two conductor groups, and second turns of a second radius within each of the at least two conductor groups, the first and second turns being electrically connected. A second spiral track is formed in the at least two conductor groups, the second spiral track including third turns of a third radius within each of the at least two conductor groups and disposed in a same plane between the first and second turns in each of the at least two conductor groups.

Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, and a RDL disposed over the transceiver. The RDL includes an antenna and a dielectric layer. The antenna is disposed over and electrically connected to the transceiver. The dielectric layer surrounds the antenna. The antenna includes an elongated portion and a via portion. The elongated portion extends over the molding, and the via portion is electrically connected to the transceiver.

Abstract: A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit.

Abstract: In a semiconductor device, a semiconductor substrate includes a bulk layer, a buried oxide layer provided in at least a partial region on the bulk layer, and a surface single crystal layer on the buried oxide layer. An inductor is provided above a main surface side of the semiconductor substrate on which the surface single crystal layer is disposed. To increase a Q value of the inductor, a ground shield is an impurity region formed in the bulk layer below the inductor and below the buried oxide layer.

Abstract: A package assembly includes a substrate extending from a first substrate end to a second substrate end. A plurality of conductive traces extend along the substrate. A plurality of contacts are coupled with the respective conductive traces of the plurality of conductive traces. Each of the contacts of the plurality of contacts includes a contact pad coupled with a respective conductive trace of the plurality of conductive traces, and a contact post coupled with the contact pad, the contact post extends from the contact pad. A package cover layer is coupled over the plurality of contact posts. The plurality of contact posts are configured to penetrate the package cover layer and extend to a raised location above the package cover layer.

Abstract: A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.

Abstract: In a coil component, an insulation layer covers an upper surface of a conductor pattern. Accordingly, insulating properties between the conductor pattern and a magnetic body are enhanced, and insulating properties between the conductor patterns are enhanced. In addition, in the coil component, the magnetic body enters a space between resin walls such that the insulation layer is covered. Therefore, a volume of the magnetic body above the conductor pattern is increased, and high coil characteristics are realized.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. The structure includes: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.

Abstract: An inductor includes a body including an insulating portion formed of a plurality of layers and a magnetic portion surrounding the insulating portion and external electrodes disposed on external surfaces of the body, and a method of manufacturing the same. A coil portion is embedded in the insulating portion, and has a structure in which coil patterns formed on a plurality of layers are stacked while being connected to each other.

Abstract: An electronic package includes an antenna structure and an adjustment structure arranged on a carrier structure. The antenna structure includes an antenna body and a feed line that are disposed on different layers and a conductive pillar that interconnects the layers to electrically connect the antenna body and the feed line. The adjustment structure extends from the feed line to improve the bandwidth of the antenna body.

Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip with an on-chip transformer. The on-chip transformer includes a primary inductor and a secondary inductor. The primary inductor is configured to have a first-primary coil portion formed of a first patterned metal trace disposed in a first metal layer and a second-primary coil portion formed of a second patterned metal trace disposed in a second metal layer. The secondary inductor is configured to have a first-secondary coil portion formed of a third patterned metal trace that interleaves with the first patterned metal trace in the first metal layer and a second-secondary coil portion formed of a fourth patterned metal trace that interleaves with the second patterned metal trace in the second metal layer.

Abstract: An electrically conductive material configured having at least one opening of various unlimited geometries extending through its thickness is provided. The opening is designed to modify eddy currents that form within the surface of the material from interaction with magnetic fields that allow for wireless energy transfer therethrough. The opening may be configured as a cut-out, a slit or combination thereof that extends through the thickness of the electrically conductive material. The electrically conductive material is configured with the cut-out and/or slit pattern positioned adjacent to an antenna configured to receive or transmit electrical energy wirelessly through near-field magnetic coupling (NFMC). A magnetic field shielding material, such as a ferrite, may also be positioned adjacent to the antenna. Such magnetic shielding materials may be used to strategically block eddy currents from electrical components and circuitry located within a device.

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

Abstract: An electronic package and a method for fabricating the same are provided. An antenna frame, a first electronic component, and a second electronic component electrically connected to the antenna frame are disposed on a lower side of a carrying structure. An antenna structure is disposed on an upper side of the carrying structure and is electrically connected to the first electronic component. Therefore, two different types of antennas are integrated into an identical electronic package. Such the electronic package bonded to a circuit can transmit signals with two different wavelengths, even if the electronic package does not have any area increased.

Abstract: A carrier structure includes a substrate, a first patterned circuit layer and at least one magnetic element. The substrate has a first surface and an opening passing through the substrate. The first patterned circuit layer is disposed on the first surface of the substrate and includes an annular circuit for generating an electromagnetic field. The magnetic element is disposed within the opening of the substrate, wherein the magnetic element couples the annular circuit and acts in response to the magnetic force of the electromagnetic field.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a uniform metal layer is formed above the second metal layer of the second wafer, the uniform metal layer is electrically connected to the second metal layer, and the uniform metal layer and the first metal layer are made of the same material. The uniform metal layer and the first metal layer simultaneously exposed by the subsequently formed TSV hole are made of the same material, the degree of over-etching is relatively easy to control in the etching process, and cross contamination of cleaning agents in the cleaning process can be avoided. In addition, when the interconnection layer is electrically connected to the first metal layer and the uniform metal layer, since the uniform metal layer and the first metal layer are made of the same material, the interconnection layer has better contact performance with the two.

Abstract: There are provided an acoustic resonator module, and a method of manufacturing the same. An acoustic resonator module includes a resonating part disposed on a substrate and an inductor electrically connected to the resonating part, and having at least a portion disposed to be spaced apart from the substrate.

Abstract: Semiconductor devices having inductive structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a substrate and at least one circuit component coupled to the substrate. The semiconductor device can further include an inductive structure carried by the substrate and having a stack of alternating first and second layers. In some embodiments, the first layers comprise an oxide material and the second layers each include a coil of conductive material. The coils of conductive material can be electrically coupled (a) together to form an inductor and (b) to the at least one circuit component.

Abstract: A switching circuit includes first to (N+1)th input/output terminals and first to Nth field-effect transistors (FETs), for an integer N of two or more. When one of a source end and a drain end is referred to as a first end and another one is referred to as a second end, the first input/output terminal is electrically connected to the first ends of all of the first to Nth FETs. For each integer i of one to N, the second end of the ith FET is electrically connected to the (i+1)th input/output terminal. For at least one integer j of one to N, a combination in which an inductor component and a resistor component are electrically connected in series to each other is disposed between the first and second ends of the jth FET such that the combination is electrically connected in parallel to the jth FET.

Abstract: A switching circuit includes a first input/output terminal, a second input/output terminal, a third input/output terminal, a first transistor, a second transistor, an inductor and a resistor. The first transistor is electrically connected between the first input/output terminal and the second input/output terminal. The second transistor is electrically connected between the first input/output terminal and the third input/output terminal. The inductor and the resistor are electrically connected in series with each other between the second input/output terminal and the third input/output terminal.