Abstract: Embodiments of the present invention provide an apparatus, a system, and a method, and include a generally rectilinear body having a first surface and a second surface. The second surface is substantially perpendicular to the first surface. An electrically operative element is disposed on the first surface, and has opposite ends. Spaced apart terminations are disposed on the second surface, and are electrically coupled with the opposite ends of the electrically operative element. The terminations are designed to be coupled with a substrate.

Abstract: This Invention is a design method and a system for a miniaturized silicon circuit whereby the circuit is split into two pieces. This process is known to the Inventor as a bifurcated circuit or disintegrated circuit and is titled the “Split Chip” by the Inventor. The Split Chip contemplates an RFID enabled consumer oriented tracking system which protects consumer privacy. The goal of this Invention is accomplished by splitting the RFID transponder circuit into a retained piece and a detached piece. Each piece is contained on a separate wafer of silicon. The two pieces are electrically connected by a fine piece of conductive material. Each piece is dependent upon the other in order to disgorge data. The electrical connection between the two pieces can be severed by the consumer. This is accomplished by tearing the fine piece of conductive material at a designated spot on the substrate. The result of the tear is that the Split Chip is now moribund.

Abstract: A semiconductor device structure includes a semiconductor substrate, a resistor layer, and a capacitor layer. The resistor layer is configured to overlie the semiconductor substrate. The resistor layer has a resistor disposed therewithin. The capacitor layer is configured to overlie the resistor layer. The capacitor layer has a capacitor disposed over and electrically connected with the resistor. Further, a semiconductor device that generates a constant output voltage from an input voltage includes a semiconductor substrate, a resistor layer, and a capacitor layer. The resistor layer is configured to overlie the semiconductor substrate. The resistor layer has a resistor disposed therewithin. The capacitor layer is configured to overlie the resistor layer. The capacitor layer has a capacitor disposed over and electrically connected with the resistor.

Abstract: A multiple function thin-film resistor-capacitor array is used for an optical fiber receiving module. A dielectric thin film with desired pattern and thickness is form on surface of a silicon substrate by semiconductor manufacture process. Resistors of different resistances and capacitors of different capacitances or the combination thereof, and circuit connection therebetween can be provided by controlling the thickness and shape of thin film. The thickness of the thin-film resistor-capacitor array is adjusted by grinding to provide a substrate of a photodiode. The photodiode can be die bonded to the resistor-capacitor array with desired optical position.

Abstract: A dielectric layer is formed over a substrate comprising a semiconductor material. A magnetic layer is formed over the dielectric layer. The magnetic layer comprises an amorphous alloy comprising cobalt.

Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

Abstract: In one embodiment, a split well region of one conductivity type is formed in semiconductor substrate of an opposite conductivity type. The split well region forms one plate of a floating capacitor and an electrode of a transient voltage suppression device.

Abstract: A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask.

Abstract: The invention proposes an interposer assembly architecture for noise suppression circuits on the package of a CPU or high power, high frequency VLSI device. In this architecture, charge is stored on dedicated capacitors at a voltage substantially higher than the operating voltage of the VLSI device. These capacitors are mounted upon active circuits that are packaged to match the size and form factor of the capacitors and this assembly is then attached to the package substrate. Charge is conveyed from the capacitor terminals on the backside of the packaged active circuits chip. Depending upon the capacitor construction, these terminals may either be double-sided contact terminals along the edge of the active device's package, or may be feed-through contacts.

Abstract: A semiconductor integrated circuit includes an inductor formed by a conductive loop that is fabricated on one or more metal layers. The inductor also includes a dielectric region provided adjacent to the conductive loop. The semiconductor integrated circuit may also include a pattern of electrically isolated metallic fill structures formed within the dielectric region.

Abstract: In an electronic circuit device including a substrate including a front surface on which an electronic circuit element is mounted and a reverse surface opposite to the front surface in a thickness direction of the substrate, an electrically conductive terminal member electrically connected to the electronic circuit element, a lead frame extending perpendicular to the thickness direction to face the reverse surface in the thickness direction, and a sealing resin covering at least partially the electronic circuit element, substrate and lead frame while at least a part of the electrically conductive terminal member is prevented from being covered by the sealing resin, the substrate extends to project outward from an end of the lead frame in a transverse direction perpendicular to the thickness direction while the end of the lead frame is covered by the sealing resin.

Abstract: It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the like, is formed over a substrate, separated from the substrate, and transferred onto a circuit board 100. An electrical conduction with a wiring pattern 114 provided in the circuit board 100 is made by a wire 112 or a solder 107, thereby forming a high frequency module or the like.

Abstract: A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second interlayer insulation film in which the MIM capacitive element is buried. A contact electrically connects the lower electrode and the upper interconnection. The lower electrode is mainly formed of Al, so that they are lower in electrical resistance than barrier metal, and also low in stress value. Therefore, it becomes possible to widen the area of the lower electrode for electrically connecting the contact while restraining their influences on charge accumulation and close contact between the lower electrode and the insulation film. In addition, since the electrical resistance is lowered, the thickness of the lower electrode can be increased.

Abstract: An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses 20 and 22 in the mesa 14. The size of recesses 20 and 22 can be used to tune the value of the electrical resistance between contacts 16 and 18.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A new method to form RF devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A top metal level is defined overlying the substrate. The top metal level comprises pads and portions of planned RF devices. A first passivation layer is formed overlying the top metal level. The first passivation layer is patterned to selectively expose the pads and the parts of planned RF devices. A dielectric layer is formed overlying the top metal level and the first passivation layer. The dielectric layer is patterned to selectively expose the top metal level. An RF metal level is defined overlying the dielectric layer and the top metal level to thereby complete the RF devices. A second passivation layer is formed overlying the RF metal level, the dielectric layer, and the top metal level. The second passivation layer is patterned to expose the pads. The method is disclosed for damascene and non-damascene metal.

Abstract: As for the resistor on the semiconductor substrate, it is required to achieve obtaining a metal resistor, which can be formed in the latter half of a preliminary process for manufacturing a semiconductor, in addition to forming a polysilicon resistor, which is formed in the first half of the preliminary process. A capacitor having MIM structure comprises a lower electrode, a capacitive insulating film and an upper electrode, all of which are sequentially formed in this sequence. A resistor structure having MIM structure also comprises a lower electrode, a capacitive insulating film and a resistor, all of which are sequentially formed in this sequence. In this case, the biasing conditions thereof should be selected so that the resistor structure lower electrode of the MIM structure resistor is not coupled to any electric potential, and is in a floating condition.

Abstract: A decoupling capacitor includes a fixed resistance in series with the capacitor, the resistance formed by contacts connecting a polysilicon layer to metal and a diffusion layer to metal; the contacts being of location and quantity sufficient for limiting defect current while allowing the capacitor to function at high frequency. N pairs of contacts in at least two sets of contacts are separated by a distance K sufficient to achieve a leakage limiting resistance of R and a bandwidth limiting resistance of R/2.

Abstract: A semiconductor apparatus includes lower conductive film strips, an inter-layer insulating layer, implanted conductive members, and upper conductive film strips. The lower conductive film strips are formed in a pattern closely adjacent in a line width orientation, electrically separated from each other. The inter-layer insulating layer is formed the lower conductive film strips. The implanted conductive members are implanted in connection holes formed in the inter-layer insulating layer at positions corresponding to both edge sides of the lower conductive film strips. The upper conductive film strips are formed on the implanted conductive members and the inter-layer insulating layer to connect the lower conductive film strips in series so that the lower conductive film strips, the implanted conductive members, and the upper conductive film strips form an electric coil.

Abstract: There is here disclosed a semiconductor device comprising a capacitor provided on a substrate and formed by sandwiching a capacitive insulating film between lower and upper electrodes, an interlayer insulating film of an n-th layer (n is 1 or greater integer) provided on the substrate to cover the capacitor, and a plurality of plugs and a plurality of wirings provided on the substrate, wherein an electrode wiring among the wirings which is electrically connected to the lower or upper electrode above the capacitor is provided in an interlayer insulating film of an (n+1)-th layer or more formed on the interlayer insulating film of the n-th layer.

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a spirally patterned conductor layer which terminates in a microelectronic structure within the center of the spirally patterned conductor layer. The spirally patterned conductor layer forms a planar spiral inductor, and the microelectronic structure formed within the center of the spirally patterned conductor layer further comprises a series of electrically interconnected sub-patterns. The method contemplates a microelectronic fabrication fabricated in accord with the method. The microelectronic fabrication is fabricated with optimal performance while occupying minimal microelectronic substrate area.

Abstract: A thin film capacitor with small electrode resistance and great Q-value which comprises a small number of thin films that are deposited successively is disclosed. It is effective for miniaturization and high density packaging of a device and for preventing poor characteristics and degradation of reliability. A plurality of lower electrodes 2 are provided on a supporting substrate 1, which are spaced apart from each other in a high frequency signal propagation direction P. Two upper electrodes 5 spaced apart from each other in the high frequency signal propagation direction P are provided on one of the plurality of the lower electrodes 2 through a thin film dielectric layer 4, by which two capacitance elements are formed. The upper electrodes 5 are connected together by an extraction electrode 8 so that the two capacitance elements are connected in series.

Abstract: A thin-film RC circuit element suitable for a transmission line termination circuit is prepared by a process wherein 1) a first metal layer of an anodizable metal is deposited on a substrate; 2) the exposed surface of the anodizable metal layer is anodized to produce an oxide layer, 3) a second metal layer of electrically conductive metal is provided on the oxide layer, and 4) the first metal layer is etched to form an electrically resistive conductive path electrically connected to the region f the first metal layer beneath the second metal layer. A thin-film RC circuit element is also provided having a first layer of an anodizable metal formed on an electrically insulating substrate so as to provide two capacitor plates connected by a resistive strip, an oxide layer formed on the capacitor plates, and upper capacitor plates positioned on the oxide layer in register with the lower capacitor plates.

Abstract: A semiconductor apparatus includes lower conductive film strips, an inter-layer insulating layer, implanted conductive members, and upper conductive film strips. The lower conductive film strips are formed in a pattern closely adjacent in a line width orientation, electrically separated from each other. The inter-layer insulating layer is formed the lower conductive film strips. The implanted conductive members are implanted in connection holes formed in the inter-layer insulating layer at positions corresponding to both edge sides of the lower conductive film strips. The upper conductive film strips are formed on the implanted conductive members and the inter-layer insulating layer to connect the lower conductive film strips in series so that the lower conductive film strips, the implanted conductive members, and the upper conductive film strips form an electric coil.

Abstract: There is provided a trimming pattern enabling trimming to be implemented with ease and time required for trimming to be shortened without causing damage to internal elements. The invention provides the trimming pattern for use in trimming of a semiconductor integrated circuit, comprising two pads to which a voltage is applied, a thin line part interconnecting the two pads, and two connecting parts disposed away from each side of the thin line part, and connected to an adjustment circuit and the semiconductor integrated circuit, respectively. With the invention, trimming is executed by a method of turning the adjustment circuit connected to the connecting parts into the ON state by connecting fused metal of the thin line part to the connecting parts. In this case, since the fused metal can be caused to come into contact with the connecting parts nearby with greater ease than fusion cutting of the thin line part, trimming can be implemented with ease and in shorter time.

Abstract: The present invention relates to the field of a semiconductor device having a ferroelectric material capacitor and method of making the same. The semiconductor device includes a capacitor having a triple-level oxygen barrier layer pattern formed by an oxygen barrier metal layer, a material layer formed of a conductive solid solution by compounding the oxygen barrier metal layer and oxygen, and an oxygen barrier metal on an interlayer dielectric with a contact plug. The capacitor also has an electrode and a ferroelectric film electrically contacting to the oxygen barrier layer. Further, a wetting layer is formed between the oxygen barrier layer and the contact plug, and an iridium oxygen layer is formed between the oxygen barrier layer and a capacitor electrode.

Abstract: A filter circuit (10) is formed on a semiconductor substrate (11) formed with a trench (40) that is lined with a dielectric layer (38). A conductive material (37) is disposed in the trench and coupled to a node (62) to provide a capacitance that modifies a frequency response of an input signal (VIN) to produce a filtered signal (VOUT). An electrostatic discharge device includes an inductor (74) coupled to back to back diodes (17, 18) formed in the substrate to avalanche when a voltage on the node reaches a predetermined magnitude.

Abstract: According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprises a metal resistor situated over the first intermetallic dielectric layer and below a second intermetallic dielectric layer. The integrated circuit chip further comprises a second interconnect metal layer over the second intermetallic dielectric layer. The integrated circuit chip further comprises a first intermediate via connected to first terminal of the metal resistor, where the first intermediate via is further connected to a first metal segment patterned in the second interconnect metal layer.

Abstract: A dielectric layer is formed over a substrate comprising a semiconductor material. A magnetic layer is formed over the dielectric layer. The magnetic layer comprises an amorphous alloy comprising cobalt.

Abstract: A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/° C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).

Abstract: A semiconductor device has a silicon layer and a first dielectric layer. A transistor has a drain and a source that are at least partially in the silicon layer. The transistor further has a gate and a spacer defining the gate. The first dielectric layer forms the spacer. A capacitor has first and second electrodes, the first electrode is formed at least partially in the silicon layer, and the first dielectric layer provides a dielectric for the capacitor between the first and second electrodes. A resistor has a resistive region formed at least partially in the silicon layer and has first and second resistor contact areas defined by the first dielectric layer. A second dielectric layer electrically isolates the transistor, the capacitor, and the resistor from conductive lines.

Abstract: The invention provides systems and methods for interconnecting circuit devices, wherein decoupling capacitors are disposed on a substrate and an interconnect layer having a pattern of circuit connections is formed by a deposition process over the capacitors thereby embedding the decoupling capacitors within the interconnect layer. Circuit devices can be mounted to the surface of the deposited interconnect layer at locations that minimize, or substantially minimize, the interconnect length between the chip device and the decoupling capacitors for that circuit device.

Abstract: A voltage supply bypass capacitor for use with a semiconductor integrated circuit chip or module comprising a ferroelectric dielectric having electromechanical properties designed to provide maximum losses at selected frequencies.

Abstract: An interconnect module and a method of manufacturing the same is described comprising: a substrate, an interconnect section formed on the substrate, and a variable passive device section formed on the substrate located laterally adjacent to the interconnect section. The interconnect section has at least two metal interconnect layers separated by a dielectric layer and the variable passive device has at least one moveable element. The moveable element is formed from a metal layer which is formed from the same material and at the same time as one of the two interconnect layers. The moveable element is formed on the dielectric layer and is released by local removal of the dielectric layer. Additional interconnect layers and intermediate dielectric layers may be added.

Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention has an MIM structure capacitor connected between a power source potential electrode wiring and a ground potential electrode wiring each via at least one interlayer connection wiring.

Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

Abstract: A capacitor in a semiconductor device and a method for fabricating the same is disclosed. Disclosed the method for fabricating the capacitor in a semiconductor device comprises the steps of: forming a lower electrode made of doped silicon materials on a semiconductor substrate; depositing a thin silicon nitride layer on the lower electrode; forming a silicon oxynitride layer on the surface of the silicon nitride layer through oxidation of the silicon nitride layer; depositing a dielectric layer on the silicon oxynitride layer; and forming an upper electrode on the dielectric layer.

Abstract: A flip-chip integrated circuit includes a circuit substrate having electronic components. The circuit substrate typically includes GaAs or Si. Another substrate can include Group III nitride based active semiconductor devices. This substrate typically includes SiC and can be separated to provide individual nitride devices. After separation, one or more of the Group III devices can be flip-chip mounted onto the circuit substrate. The electronic components on the circuit substrate can be coupled to the nitride devices using conductive interconnects and/or vias.

Abstract: Certain embodiments of the present invention relate to a semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate. The semiconductor device includes an interlayer dielectric layer, an embedded connection layer and a connection layer, wherein the interlayer dielectric layer is located between the semiconductor substrate and the capacitor element. The connection layer and the embedded connection layer are used to electrically connect a lower electrode of the capacitor element to another semiconductor element. The connection layer is located in a common layer of a bit line that is a component of the DRAM. The embedded connection layer is located in a connection hole formed in the interlayer dielectric layer.

Abstract: An electrostatic discharge (ESD) structure for use in an integrated circuit (IC). The ESD structure comprises a metallic resistor and a metallic capacitor that are electrically coupled in series to form a resistor-capacitor (RC) component having an appropriate RC time constant. The RC component maintains a level of charge between ground and a shunt node to ensure that, during an ESD event, electrostatic charge on a power supply, VDD, associated with the ESD structure is shunted via a shunt path from said power supply VDD to said ground. By using metal to create the metal resistor and capacitor, charge leakage problems that result from parasitic capacitance associated with using an RC component comprised of either a poly, active, or nwell resistor in combination a diode are eliminated. By eliminating such charge leakage problems, a more reliable RC component, and thus a more reliable RC time constant, are obtained.

Abstract: A semiconductor device includes a metal-insulator-metal (MIM) capacitor having a lower metal layer disposed on a substrate, a dielectric film, and upper metal layers, a testing electrode pad connected to the lower metal layer of the MIN capacitor, two connecting terminals located on the substrate connected to the upper metal layers, and a field effect transistor (FET) having an electrode connected to one of the upper metal layers. By grounding the connecting terminals located on the substrate, and impressing a test voltage on the testing electrode pad, a withstand voltage test of the MIM capacitor can be conducted without damaging the FET.

Abstract: An object of the present invention is to improve the relationship between the switching loss and the conduction loss in a semiconductor device comprising a diode and a switching device made of silicon carbide, while suppressing occurrence of voltage oscillation of the device having a high amplitude. A resistor (12) is connected in parallel to a diode (11) made of silicon carbide. Although a resistive component of the diode (11) varies widely with turn-on and turn-off of the diode (11), connecting the resistor (12) in parallel to the diode (11) allows suppression of variations in a resistive component of an LCR circuit formed by the diode (11) and an external wiring. Accordingly, the LCR circuit is unlikely to satisfy the condition of natural oscillation and an increase in the quality factor of the LCR circuit is suppressed.

Abstract: A semiconductor device in which a cell capacitor with an MIM or MIS structure is formed using a conductive material with a low resistivity for the upper electrode and a resistance element is formed using a conductive material with high resistance without increasing the complexity of the fabrication process. A plate electrode used for the upper electrode of the cell capacitor and for the resistance element is made by forming a three-layer structure including a low resistance conductive material layer, an insulating film layer on the low resistance conductive material layer, and a high resistance conductive material layer on the insulating film layer, patterning the three-layer structure in the same shape, and using the low resistance conductive material layer as the upper electrode of the cell capacitor and the high resistance conductive material layer as the resistance element.

Abstract: An RC network is integrated in a semiconductor circuit chip and is connected between an input pad or pin and a ground node coupled to a substrate of the chip. The RC network has a plurality of resistance elements, a plurality of capacitance elements and a plurality of connection/isolation elements, which are provided in each case between at least one of the resistance elements and the individual capacitive elements. The inventive circuit configuration enables an optional and independent setting of the input capacitance and of the input resistance of the semiconductor circuit chip, depending on the connection/isolation state of the connection/isolation elements.

Abstract: A method of utilizing passive circuit components in an integrated circuit comprising the steps of providing a plurality of integrated capacitive elements and a plurality of integrated inductive elements interconnected to form an electrical circuit wherein each inductive element has a width and creates a circumferential magnetic field. Each integrated inductive element is oriented such that the circumferential magnetic field is parallel to the plane of each adjacent integrated capacitive element and parallel to the width of the integrated inductive element so that the resistance of the electrical circuit is decreased and the quality factor is increased.

Abstract: The inductance element according to the present invention includes: an inductance section, provided above a semiconductor substrate via insulating films, which is composed of a conductive film pattern setted to have a predetermined inductance value; and an impurity region, provided on the semiconductor substrate so as to be positioned at least at an area under the conductive film pattern, which has a grounding potential and a denser impurity than that of the semiconductor substrate. The inductance element is provided in a semiconductor device.

Abstract: In a semiconductor chip, conductive tracks run in a rewiring layer from contact pads to contact elevations. The contact pads are formed as vias. The conductive tracks are constructed in sections as bottom electrodes of trimming capacitors. The top electrode of the trimming capacitors is formed by a metal plane of the rewiring layer.

Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.

Abstract: A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the substrate. A hard masking layer is formed over the silicon oxide layer. The hard masking layer includes a full thickness portion and a thinner portion. The polysilicon layer below the full thickness portion is lightly doped forming a high resistance region. Below the thinner portion the polysilicon layer is heavily doped forming a low resistance region. However, in spite of the differences in resistance, the high resistance region and the low resistance region have the same thickness.

Abstract: An integrated circuit having capacitive elements for smoothing a supply voltage is described. In this case, at least one additional metal electrode, which is configured as a high frequency-optimized capacitance and is distinguished by an extremely low sheet resistance, is connected in parallel with the MOS capacitances. By connecting the areally highly effective MOS capacitance, which, however, is connected with a somewhat higher impedance, in parallel with areally less effective metal capacitances, which, however, are connected to the supply voltage in a very low-impedance manner, it is possible to obtain broadband buffering and thus decoupling of high-frequency interference signals. Very high-frequency interference components are attenuated on the chip and do not pass into the system surrounding the integrated circuit.