Polycrystalline Silicon (doped Or Undoped) Patents (Class 257/538)
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Patent number: 8482100Abstract: A resistor array includes a semiconductor substrate, a plurality of isolation regions, a plurality of dummy active regions and a plurality of unit resistors. The plurality of isolation regions are formed in the semiconductor substrate. The plurality of dummy active regions are formed in the semiconductor substrate between the plurality of isolation regions. The plurality of unit resistors are formed on the plurality of dummy active regions.Type: GrantFiled: September 1, 2011Date of Patent: July 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Young-Jin Cho
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Publication number: 20130154687Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.Type: ApplicationFiled: October 30, 2012Publication date: June 20, 2013Applicant: Static Control Components, Inc.Inventor: Static Control Components, Inc.
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Patent number: 8436447Abstract: In a first aspect, a memory cell is provided, the memory cell including: (a) a first conducting layer formed above a substrate; (b) a second conducting layer formed above the first conducting layer; (c) a structure formed between the first and second conducting layers, wherein the structure includes a sidewall that defines an opening extending between the first and second conducting layers, and wherein the structure is comprised of a material that facilitates selective, directional growth of carbon nano-tubes; and (d) a carbon-based switching layer that includes carbon nano-tubes formed on the sidewall of the structure. Numerous other aspects are provided.Type: GrantFiled: April 23, 2010Date of Patent: May 7, 2013Assignee: SanDisk 3D LLCInventors: Pankaj Kalra, Raghuveer S. Makala
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Patent number: 8426942Abstract: A semiconductor device includes a semiconductor substrate, a base insulating layer, a silicon fuse, a pair of silicon wires, a silicon guard ring, an insulation coating, a first interlayer insulating layer, a via guard ring, a metal guard ring, a final insulating layer, and a fuse window. The base insulating layer is disposed over the semiconductor substrate. The silicon fuse is disposed on the base insulating layer. The pair of silicon wires is disposed on the base insulating layer. The silicon guard ring is disposed on the base insulating layer. The insulation coating is deposited at least over surfaces of the silicon wires. The first interlayer insulating layer is disposed on the base insulating layer. The final insulating layer is disposed on the interlayer insulating layer. The fuse window is defined above the silicon fuse inside the guard rings.Type: GrantFiled: July 21, 2010Date of Patent: April 23, 2013Assignee: Ricoh Company, Ltd.Inventors: Masashi Oshima, Masaya Ohtsuka, Ryuta Isobe
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Patent number: 8410480Abstract: The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity.Type: GrantFiled: February 19, 2010Date of Patent: April 2, 2013Assignee: National Chip Implementation Center National Applied Research LaboratoriesInventors: Chin-Fong Chiu, Ying Zong Juang, Hann Huei Tsai, Sheng-Hsiang Tseng, Chen-Fu Lin
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Publication number: 20130056854Abstract: Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.Type: ApplicationFiled: November 2, 2012Publication date: March 7, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Stefan FLACHOWSKY, Jan HOENTSCHEL, Thilo SCHEIPER
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Publication number: 20130049168Abstract: A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.Type: ApplicationFiled: August 23, 2011Publication date: February 28, 2013Inventors: Jie-Ning Yang, Shih-Chieh Hsu, Yao-Chang Wang, Chi-Horn Pai, Chi-Sheng Tseng, Kun-Szu Tseng, Ying-Hung Chou, Chiu-Hsien Yeh
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Publication number: 20130032926Abstract: An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.Type: ApplicationFiled: July 19, 2012Publication date: February 7, 2013Inventors: Pascal FORNARA, Arnaud Regnier
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Publication number: 20120319240Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.Type: ApplicationFiled: June 14, 2011Publication date: December 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
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Publication number: 20120319241Abstract: The resistor segments may be placed in a spatial region of an integrated circuit. Junctions formed between the resistor segments and conductors may be placed at locations such that each junction has a paired counterpart of the same type that is spaced to form respective same junction type centroids (i.e., geometric centers). The different type centroids may be substantially coincident, meaning that the centroids substantially overlap. In this manner, junction voltages (or offset voltages) generated by one pair of junctions may cancel out the junction voltages generated by another pair of junctions in the resistor circuit.Type: ApplicationFiled: June 14, 2012Publication date: December 20, 2012Applicant: ANALOG DEVICES, INC.Inventors: Yijing LIN, Damien MCCARTNEY
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Publication number: 20120313664Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.Type: ApplicationFiled: July 29, 2011Publication date: December 13, 2012Applicant: STATIC CONTROL COMPONENTS, INC.Inventors: William Eli Thacker, III, Robert Francis Tenczar, Michael Clinton Hoke
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Publication number: 20120280361Abstract: Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.Type: ApplicationFiled: May 4, 2011Publication date: November 8, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
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Patent number: 8242580Abstract: Provided is a method which is capable of producing polycrystalline silicon resistors with a high ratio accuracy so that a precision resistor circuit may be designed. A semiconductor device has a structure in which an occupation area of a metal portion covering a low concentration impurity region constituting each of the polycrystalline silicon resistors is adjusted so that ratio accuracy may be further corrected after a resistance is corrected.Type: GrantFiled: February 4, 2010Date of Patent: August 14, 2012Assignee: Seiko Epson Instruments Inc.Inventor: Akiko Tsukamoto
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Patent number: 8227888Abstract: A semiconductor component including a first integrated circuit in a substrate which is adapted to produce electrical signals with a high-frequency signal component, wherein the substrate is such that the high-frequency signal component can propagate on a substrate surface and/or in the substrate interior, a second integrated circuit in the same substrate which is such that its function can be compromised by high-frequency signals, and a countersignal circuit in the same substrate which is adapted to deliver an electrical countersignal which at least at a selected location of the substrate surface and/or the substrate interior attenuates or eliminates the high-frequency electrical signal component emanating from the first integrated circuit, wherein the countersignal circuit includes a receiver which is adapted to produce an electrical signal dependent on the instantaneous field strength of the high-frequency signal component, and a shielding transistor provided in the substrate and having a control electrodeType: GrantFiled: April 8, 2005Date of Patent: July 24, 2012Assignee: IHP GmbH—Innovations for High Performance MicroelectronicsInventors: Gunther Lippert, Gerald Lippert
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Publication number: 20120175737Abstract: A semiconductor power device integrated with a Gate-Source ESD diode for providing an electrostatic discharge (ESD) protection and a Gate-Drain clamp diode for drain-source avalanche protection. The semiconductor power device further includes a Nitride layer underneath the diodes and a thick oxide layer as an etching stopper layer for protecting a thin oxide layer on top surface of body region from over-etching.Type: ApplicationFiled: March 9, 2012Publication date: July 12, 2012Applicant: Force Mos Technology Co., Ltd.Inventor: Fu-Yuan HSIEH
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Publication number: 20120146187Abstract: A method of forming a semiconductor structure includes forming at least one trench in an insulator layer formed on a substrate. A distance between a bottom edge of the at least one trench and a top surface of a substrate is shorter than a distance between an uppermost surface of the insulator layer and the top surface of the substrate. The method also includes: forming a resistor on the insulator layer and extending into the at least one trench; forming a first contact in contact with the resistor; and forming a second contact in contact with the resistor such that current is configured to flow from the first contact to the second contact through a central portion of the resistor.Type: ApplicationFiled: December 14, 2010Publication date: June 14, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent A. ANDERSON, Jed H. RANKIN, Robert R. ROBISON
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Patent number: 8169052Abstract: A metal electrode is disposed on each of a plurality of resistor groups which are made of polycrystalline silicon resistors and constitute a resistor circuit. The metal electrode is connected to an end of the resistor via another interconnecting layer. Accordingly, the external influence which the metal electrode receives during a semiconductor manufacturing process is prevented from directly acting on the resistor, whereby resistance variation is suppressed.Type: GrantFiled: December 4, 2008Date of Patent: May 1, 2012Assignee: Seiko Instruments Inc.Inventor: Hirofumi Harada
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Patent number: 8138573Abstract: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.Type: GrantFiled: April 23, 2010Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Ethan H. Cannon, Alvin W. Strong
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Publication number: 20120038026Abstract: A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.Type: ApplicationFiled: October 26, 2011Publication date: February 16, 2012Applicant: GLOBALFOUNDRIES Inc.Inventor: Steven R. Soss
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Patent number: 8093134Abstract: A phase change memory device includes a semiconductor substrate having a conductive region, a heater electrode formed on the semiconductor substrate and including a connection element which is composed of carbon nanotubes electrically connected with the conductive region, and a phase change pattern layer contacting the connection element of the heater electrode.Type: GrantFiled: November 9, 2010Date of Patent: January 10, 2012Assignee: Hynix Semiconductor Inc.Inventor: Min Seok Son
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Patent number: 8076754Abstract: A silicide-interface polysilicon resistor is disclosed. The silicide-interface polysilicon resistor includes a substrate, an oxide layer located on top of the substrate, and a polysilicon layer located on top of the oxide layer. The polysilicon layer includes multiple semiconductor junctions. The silicide-interface polysilicon resistor also includes a layer of silicide sheets, and at least one of the silicon sheets is in contact with one of the semiconductor junctions located within the polysilicon layer.Type: GrantFiled: March 9, 2007Date of Patent: December 13, 2011Assignee: Silicon LaboratoriesInventors: Steven G. Young, David M. Szmyd
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Patent number: 8049305Abstract: A resistance-change memory device using stress engineering is described, including a first layer including a first conductive electrode, a second layer above the first layer including a resistive-switching element, a third layer above the second layer including a second conductive electrode, where a first stress is created in the switching element at a first interface between the first layer and the second layer upon heating the memory element, and where a second stress is created in the switching element at a second interface between the second layer and the third layer upon the heating. A stress gradient equal to a difference between the first stress and the second stress has an absolute value greater than 50 MPa, and a reset voltage of the memory element has a polarity relative to a common electrical potential that has a sign opposite the stress gradient when applied to the first conductive electrode.Type: GrantFiled: October 15, 2009Date of Patent: November 1, 2011Assignee: Intermolecular, Inc.Inventors: Michael Miller, Prashant Phatak, Tony Chiang
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Publication number: 20110260290Abstract: In a first aspect, a memory cell is provided, the memory cell including: (a) a first conducting layer formed above a substrate; (b) a second conducting layer formed above the first conducting layer; (c) a structure formed between the first and second conducting layers, wherein the structure includes a sidewall that defines an opening extending between the first and second conducting layers, and wherein the structure is comprised of a material that facilitates selective, directional growth of carbon nano-tubes; and (d) a carbon-based switching layer that includes carbon nano-tubes formed on the sidewall of the structure. Numerous other aspects are provided.Type: ApplicationFiled: April 23, 2010Publication date: October 27, 2011Inventors: Pankaj Kalra, Raghuveer S. Makala
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Patent number: 8044450Abstract: A semiconductor device comprising a resistance element with a high resistance and high resistance accuracy and a non-volatile semiconductor storage element is rationally realized by comprising the non-volatile semiconductor storage element comprising a first isolation formed to isolate a first semiconductor area, a first insulator, and a first electrode in a self-aligned manner, and a second electrode, and the resistance element comprising a second isolation formed to isolate a second semiconductor area, a third insulator and a conductor layer in a self-aligned manner, and third and fourth electrodes formed on each end of the conductor layer via a fourth insulator, and connected with the conductor layer. The conductor layer or the third and fourth electrodes include the same material with the first or second electrode, respectively.Type: GrantFiled: July 6, 2005Date of Patent: October 25, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiro Noguchi, Susumu Yoshikawa, Koichi Fukuda
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Patent number: 8030738Abstract: Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a semiconductor device with the resistor pattern. Embodiments of the invention also provide a semiconductor device with a resistor pattern that is formed narrower than the minimum line width that can be defined in a photolithographic process so that sheet resistance thereof increases, and a method of fabricating the same.Type: GrantFiled: June 26, 2006Date of Patent: October 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Yoo-Cheol Shin
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Patent number: 8026556Abstract: A method of manufacturing a resistive divider circuit, includes providing a silicon body having a plurality of opposing pairs of intermediate taps extending therefrom. Each tap comprises a thin silicon stem supporting a relatively wider silicon platform. A silicidation protection (SIPROT) layer is deposited over the body and intermediate taps and then patterned to expose the platform. A silicidation process is performed to silicidate the platform to form a contact pad of relatively low resistivity.Type: GrantFiled: April 19, 2007Date of Patent: September 27, 2011Assignee: NXP B.V.Inventor: Andy C. Negoi
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Publication number: 20110227192Abstract: Provided are a semiconductor device including a highly precise resistor formed of a polycrystalline silicon film and a method of manufacturing the same, in which: a portion of a base insulating film below a portion of the polycrystalline silicon film which becomes a resistance region into a convex shape; and the polycrystalline silicon film which becomes the resistor is selectively formed into a thin film, while an electrode lead-out region remains thick so as to obtain the resistor with high precision, high resistivity, and a preferable temperature coefficient while preventing penetration in an opening for contact.Type: ApplicationFiled: May 26, 2011Publication date: September 22, 2011Inventor: Yuichiro Kitajima
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Publication number: 20110215321Abstract: A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance.Type: ApplicationFiled: March 8, 2010Publication date: September 8, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roger A. Booth, JR., Kangguo Cheng, Rainer Loesing, Chengwen Pei, Xiaojun Yu
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Patent number: 8008723Abstract: Aimed at reducing the area of a protective circuit in a semiconductor device provided therewith, a semiconductor device of the present invention has a first-conductivity-type well, a plurality of first diffusion layers formed in the well, a plurality of second diffusion layers formed in the well, and a diffusion resistance layer formed in the well, wherein the first diffusion layers have a second conductivity type, and are connected in parallel with each other to an input/output terminal of the semiconductor device; the second diffusion layers are arranged alternately with a plurality of first diffusion layers, and are connected to a power source or to the ground; the diffusion resistance layer has a second conductivity type, and is located in adjacent to any of the plurality of second diffusion layers; the diffusion resistance layer is connected to the input/output terminal of the semiconductor device, while being arranged in parallel with the first diffusion layers, and connects the internal circuit and theType: GrantFiled: February 24, 2009Date of Patent: August 30, 2011Assignee: Renesas Electronics CorporationInventor: Takayuki Nagai
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Patent number: 8009011Abstract: An electrically adjustable resistor comprises a resistive polysilicon layer dielectrically isolated from one or more doped semiconducting layers. A tunable voltage is applied to the doped semiconducting layers, causing the resistance of the polysilicon layer to vary. Multiple matched electrically adjustable resistors may be fabricated on a single substrate, tuned by a single, shared doped semiconductor layer, creating matched, tunable resistor pairs that are particularly useful for differential amplifier applications. Multiple, independently adjustable resistors may also be fabricated on a common substrate.Type: GrantFiled: June 26, 2008Date of Patent: August 30, 2011Assignee: Semtech CorporationInventors: Stuart B. Molin, Paul Nygaard
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Patent number: 7982287Abstract: A system and method is disclosed for providing a resistor protect layer to protect a thin film resistor in a semiconductor device. A thin film resistor is formed on a dielectric layer and a resistor protect layer is placed over the thin film resistor. An etch procedure is employed to facet the corners of the resistor protect layer. The faceted corners of the resistor protect layer reduce the step height of the resistor protect layer. Then a conductor is deposited over the resistor protect layer and the dielectric layer. When portions of the conductor are subsequently etched away, the resistor protect layer protects the underlying thin film resistor from being exposed to the etch process.Type: GrantFiled: May 11, 2009Date of Patent: July 19, 2011Assignee: National Semiconductor CorporationInventor: Rodney Hill
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Patent number: 7977201Abstract: In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.Type: GrantFiled: August 14, 2008Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, Robert Robison, Yun Shi, William R. Tonti
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Publication number: 20110163419Abstract: An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology.Type: ApplicationFiled: September 19, 2008Publication date: July 7, 2011Applicant: AGERE SYSTEMS INC.Inventors: Frank A. Baiocchi, James T. Cargo, John M. DeLucca, Barry J. Dutt, Charles Martin
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Patent number: 7939911Abstract: In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.Type: GrantFiled: August 14, 2008Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, Robert Robison, Yun Shi, William R. Tonti
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Patent number: 7932146Abstract: A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.Type: GrantFiled: March 20, 2008Date of Patent: April 26, 2011Assignee: United Microelectronics Corp.Inventors: Yi-Wen Chen, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Tian-Fu Chiang, Chien-Ting Lin, Guang-Hwa Ma
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Patent number: 7915995Abstract: A resistive circuit includes a first terminal and a second terminal and polycrystalline first and second resistive segments coupled between the first and second terminals. A third terminal A is coupled to the first resistive segment, and a third terminal B is coupled to the second resistive segment. The third terminal A has a first voltage with respect to the first terminal, and the third terminal B has a second voltage with respect to the second terminal. With this arrangement, the non-linearity of resistance of the first resistive segment at least partially compensates for non-linearity of resistance of the second resistive segment.Type: GrantFiled: September 29, 2009Date of Patent: March 29, 2011Assignee: Cirrus Logic, Inc.Inventors: Hua Yang, Ammisetti Prasad, John L. Melanson
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Publication number: 20110057267Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.Type: ApplicationFiled: September 4, 2009Publication date: March 10, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry Hak-Lay Chuang, Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu, Bao-Ru Young
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Patent number: 7884442Abstract: An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses 20 and 22 in the mesa 14. The size of recesses 20and 22 can be used to tune the value of the electrical resistance between contacts 16 and 18.Type: GrantFiled: February 26, 2007Date of Patent: February 8, 2011Assignee: Raytheon CompanyInventors: David D. Heston, Jon E. Mooney
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Patent number: 7855434Abstract: A semiconductor device is provided wherein a foundation insulating film is formed over a semiconductor substrate, a metal resistance element is formed on the foundation insulating film, and contacts are formed at both ends of the metal resistance element in a longitudinal direction of the metal resistance element and connected to the metal resistance element. The foundation insulating film comprises a single upwardly concave curved surface constituting not less than about 40 percent of an upper surface of the metal resistance element between the contacts in the longitudinal direction thereof. The curved surface of the foundation insulating film causes the metal resistance element to comprise a single upwardly concave curved surface constituting not less than about 40 percent of upper and lower surfaces of the metal resistance element between the contacts in the longitudinal direction thereof.Type: GrantFiled: March 26, 2008Date of Patent: December 21, 2010Assignee: Ricoh Company, Ltd.Inventor: Kimihiko Yamashita
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Patent number: 7851887Abstract: A phase change memory device includes a semiconductor substrate having a conductive region, a heater electrode formed on the semiconductor substrate and including a connection element which is composed of carbon nanotubes electrically connected with the conductive region, and a phase change pattern layer contacting the connection element of the heater electrode.Type: GrantFiled: December 29, 2008Date of Patent: December 14, 2010Assignee: Hynix Semiconductor Inc.Inventor: Min Seok Son
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Patent number: 7838966Abstract: A semiconductor device may include a resistance pattern including a resistance material on a substrate. The resistance pattern may include first and second spaced apart base elements, a bridge element, and first, second, third, and fourth extension elements. The first and second base elements may be substantially parallel, and the bridge element may be connected between respective center portions of the first and second spaced apart base elements. The first and second extension elements may be connected to opposite ends of the first base element and may extend toward the second base element, and the third and fourth extension elements may be connected to opposite ends of the second base element and may extend toward the first base element. Related methods are also discussed.Type: GrantFiled: July 5, 2007Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Xiao Quan Wang, Chang-Bong Oh, Seung-Hwan Lee
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Patent number: 7804154Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.Type: GrantFiled: December 11, 2008Date of Patent: September 28, 2010Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
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Patent number: 7804155Abstract: A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first doped-type region receives a control bias, the second doped-type region receives a reference bias, and a resistance between the second doped-type region and the substrate is adjusted in response to a voltage difference between the control bias and the reference bias.Type: GrantFiled: January 23, 2009Date of Patent: September 28, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Min-Hwa Chi
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Patent number: 7803687Abstract: A method for forming a thin film resistor includes providing a substrate having a transistor region and a thin film resistor region defined thereon, sequentially forming a dielectric layer, a metal layer and a first hard mask layer on the substrate, patterning the first hard mask layer to form at least a thin film resistor pattern in the thin film resistor region, sequentially forming a polysilicon layer and a second hard mask layer on the substrate, patterning the second hard mask layer to form at least a gate pattern in the transistor region, and performing an etching process to form a gate and a thin film resistor respectively in the transistor region and the thin film resistor region.Type: GrantFiled: October 17, 2008Date of Patent: September 28, 2010Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor-Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
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Patent number: 7795701Abstract: A first insulation film is provided on a semiconductor substrate. A high resistance element formed from polysilicon is provided on the first insulation film. A second insulation film is provided on the high resistance element. A hydrogen diffusion preventing film having a hydrogen diffusion coefficient smaller than that of the second insulation film is provided on the second insulation film. The hydrogen diffusion preventing film covers a part of the high resistance element.Type: GrantFiled: March 11, 2008Date of Patent: September 14, 2010Assignee: Panasonic CorporationInventors: Hidenori Iwadate, Takeshi Kobiki
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Publication number: 20100214705Abstract: An electrostatic discharge (ESD) protection element includes a first diode, a second diode, and a poly resistor. The first diode is connected between a first voltage and an input/output (I/O) pad. The second diode is connected between the I/O pad and a second voltage. The poly resistor is formed on the second diode.Type: ApplicationFiled: February 12, 2010Publication date: August 26, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Suk-Jin Kim, Han-Gu Kim, Jae-Hyok Ko, Hyo-Cheol Ban, Min-Chang Ko, Kyoung-Ki Jeon
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Publication number: 20100200953Abstract: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.Type: ApplicationFiled: April 23, 2010Publication date: August 12, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ethan H. Cannon, Alvin W. Strong
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Publication number: 20100200952Abstract: Provided is a method which is capable of producing polycrystalline silicon resistors with a high ratio accuracy so that a precision resistor circuit may be designed. A semiconductor device has a structure in which an occupation area of a metal portion covering a low concentration impurity region constituting each of the polycrystalline silicon resistors is adjusted so that ratio accuracy may be further corrected after a resistance is corrected.Type: ApplicationFiled: February 4, 2010Publication date: August 12, 2010Inventor: Akiko Tsukamoto
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Patent number: 7768004Abstract: In a semiconductor device including a semiconductor substrate and an electrode pad formed over the semiconductor substrate, at least one of test element is formed in a region of the semiconductor substrate beneath the electrode pad. The test element is electrically isolated from upper conductive layers outside of the region and the electrode pad.Type: GrantFiled: October 24, 2005Date of Patent: August 3, 2010Assignee: NEC Electronics CorporationInventor: Hideomi Shintaku
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Patent number: 7759763Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.Type: GrantFiled: May 6, 2008Date of Patent: July 20, 2010Assignee: Renesas Technology Corp.Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka