Abstract: An SRAM according to the present invention includes a voltage-down circuit and an internal circuit. The voltage-down circuit includes three resistors, two PMOS transistors and an NMOS transistor. One PMOS transistor directly applies an external power supply voltage to the internal circuit. The NMOS transistor applies a voltage obtained by reducing the external power supply voltage by a threshold voltage thereof to the internal circuit. The value of a predetermined voltage as a condition for switching such application of the voltage by the PMOS transistor and application Of the voltage by the NMOS transistor is determined by the resistance ratio of the two resistors. Each of the three resistors is formed by a plurality of resistance elements of one kind. Thus, even if the process parameter varies, the ratio of the resistance values of the two resistors which determines the switching point can be kept constant, thereby preventing variation in switching point.

Abstract: A solid imaging device including a substrate voltage generating device possessing high display quality, high reliability, and method of manufacturing. The solid imaging device includes a plurality of photoelectric conversion elements, a vertical charge transfer portion for transferring the signal charges generated by the photoelectric conversion element, and a substrate voltage generating circuit. The substrate generating circuit 10 includes a variable resistor 11 formed by arranging a plurality of sets formed by selection switches 13 and resistors 14a-14e, and a load resistor 12 disposed by connecting with the variable resistor 11 between the source potential Vdd and the earth potential, and the substrate voltage Vsub is obtained from a contact between the variable resistor 11 and the load resistor 12. The selection switches 13 are consituted by antifuse elements.

Abstract: A capacitor structure (100) including first and second capacitor plates (102, 106) insulatingly spaced from each other by a capacitor dielectric (102). A first set of conductive posts (301) electrically couple to the first capacitor plate (102) and extend away from the capacitor dielectric (104). A first conductive structure (302) comprising a material with lower resistivity than the first capacitor plate (102) is electrically coupled to the first set of conductive posts (301). In a preferred embodiment, a second set of conductive posts (501) are electrically coupled to the second capacitor plate (106) and extend away from the capacitor dielectric (102). A second conductive structure (503) is electrically coupled to the second set of conductive posts (501).

Abstract: A semiconductor device which has a MOS transistor having a gate electrode composed of a first conductive film formed on a silicon substrate; a resistance element composed of a second conductive film formed on a field insulating film formed on the silicon substrate; and a plurality of conductive film patterns formed in parallel at predetermined intervals on the surface of the field insulating film, wherein the plurality of conductive film patterns are of the first conductive film type connected with a predetermined potential, and the top surface and side of each of the plurality of conductive film patterns are covered with an insulating film; wherein the resistance element is formed reciprocative-crossing several times in the orthogonal direction to the plurality of conductive film patterns through the insulating film on the plurality of conductive film patterns.

Abstract: The present invention relates to a composite integrated circuit including at least one well that separates analog and digital blocks of the circuit, this well being connected to a first terminal of a power supply of biasing of one of the two blocks, and being of type opposite to that of the circuit substrate, and a resistor being interposed on the well biasing link.

Abstract: An SRAM is provided with a high-resistance element for loading including a high-resistance portion, which extends onto adjacent memory cell. An interlayer insulating film is formed between the high-resistance portions.

Abstract: In a resistance element formed by a connection layer including a flexing portion, the connection layer is constructed by a high resistance section including the flexing portion and a low resistance section. Boundaries between the high resistance section and the low resistance section are approximately in parallel with a bisector of the connection layer at the flexing portion.

Abstract: A polycrystalline silicon coated nitride-lined shallow trench technique for isolating active regions on an integrated circuit involves reducing the oxide encroachment and the "bird's beak" structure. The technique involves forming an isolation trench, or recess, in the substrate. This recess is then lined with a layer of silicon dioxide layer, and then a layer of silicon nitride. Subsequently, a polycrystalline silicon material is deposited in the recess and is then oxidized to form a field oxide and planarized. Since the recess is nitride-lined, which prevents oxidizing species from reaching the oxide layer beneath the nitride layer, and the polycrystalline silicon is oxidized, the result is zero oxide encroachment resulting in the elimination of the "bird's beak" structure.

Abstract: A static random access memory device includes: a semiconductor substrate divided into a cell array portion and a periphery circuit portion; a first insulating layer for insulating devices formed on the substrate from a thin-film transistor; a conductive layer formed on the first insulating layer in the cell array portion, for supplying power; a buffer layer formed on the conductive layer in the cell array portion; a second insulating layer formed on the buffer layer in the cell array portion and on the first insulating layer of the periphery circuit portion; and a metal wiring pattern formed on the second insulating layer. A first portion of the metal wiring pattern connects to the conductive layer via a first contact hole which is formed passing through the second insulating layer and the buffer layer, thus exposing the conductive layer in the cell array portion.

Abstract: A resistor is formed between devices in an integrated circuit by forming a patterned trench in an intralayer dielectric (ILD) deposited over the devices, filling the trench with polysilicon and planarizing the polysilicon. The resistance of the resistor is defined by determining and selecting the size and form of the trench including the width, length, depth and orientation of the trench. In some embodiments, the resistance of the resistor is also controlled by adding selected amounts and species of dopants to the polysilicon. In some embodiments, the resistance is controlled by directly saliciding the polysilicon in the trench.

Abstract: A resistor network having a precise ratio of resistances of all resistors within the network while having a compact layout to minimize area is described. The integrated circuit resistor network has a plurality of unit resistors. Each unit resistor is composed of a thin film resistive material. The area of the thin film resistive material to form the unit resistor is a median value of the resistor elements to be formed into said integrated circuit resistor network. Each unit resistor has a contact means to connect to the plurality of unit resistors. A plurality of metal interconnection segments will connect to the contact means to form said integrated circuit resistor network. A plurality of metal conductive segments are connected to a metal interconnection segments and to external circuitry to connect the external circuitry to the integrated circuit resistor network.

Abstract: A polysilicon load structure and its manufacturing method for static random access memory, comprising the steps of first providing a semiconductor substrate, and then forming a first insulating layer over the substrate. Next, a trench is etched out from the insulating layer forming a step structure. Thereafter, a polysilicon layer is formed over the first insulating layer, and then a global ion implantation operation is performed. Next, a photoresist layer is formed over the polysilicon layer, and then a connector pattern is defined using a microlithographic process. Thereafter, the polysilicon layer is anisotropically etched to form a spacer on the sidewall of the trench. Subsequently, a second ion implantation is performed to adjust the resistance of the connector. Finally, microlithographic and etching processes are used to remove the unwanted portions of the polysilicon spacer and exposing the polysilicon spacer structure and the polysilicon connector structure.

Abstract: A semiconductor resistor element that is able to remove the effect of an electric potential change of a wiring conductor is provided. This element includes a first semiconductor resistor region formed in a surface area of a substructure, a second semiconductor resistor region electrically connected to a first end of the first resistor region, a third semiconductor resistor region electrically connected to a second end of the first resistor region. The first resistor region has a first doping concentration. The second resistor region has a second doping concentration higher than the first doping concentration. The third resistor region has a third doping concentration equal to the second doping concentration. The second and third resistor regions serve as a pair of terminals of the semiconductor resistor element. The second and third resistor regions may be contacted with or apart from the respective ends of the first resistor region.

Abstract: A linearized resistor for integrated circuits combines an N-type diffused resistor and a P-type diffused resistor. In one embodiment, the N-type and P-type diffused resistors are connected in series. In another embodiment, the N-type and P-type diffused resistors are connected in parallel. Two or more linearized resistors of the present invention may be used in IC circuits, such as voltage dividers, inverting amplifiers, single-ended operational amplifiers, and single-ended differential operational amplifiers. Linearized resistors of the present invention can be designed to have voltage coefficients smaller than conventional IC resistors having a single diffused resistor. As such, linearized resistors of the present invention can be designed to provide more uniform resistance over their operating voltage range than conventional IC resistors.

Abstract: A resistor ladder network may be formed with a reduced space on a semiconductor substrate by patterning a plurality of layers of resistive polycrystalline silicon films spaced by insulating layers. Such a device includes a first insulating film formed on a semiconductor substrate, one or more serial-connected first resistors formed in a first polycrystalline silicon film provided on the semiconductor substrate via the first insulating film, a second insulating film provided on the first polycrystalline silicon film, one or more series-connected second resistors formed in a second polycrystalline silicon film provided apart from the first polycrystalline silicon film via the second insulating film, the second polycrystalline silicon film being connected to the first polycrystalline silicon film. A third insulating film is provided over the second polycrystalline silicon film, and metal wires provided on a surface of the second polycrystalline silicon film via contact holes formed in the third insulating film.

Abstract: A p-type well and an n-type well surrounding the p-type well are formed in a p-type semiconductor substrate under a field insulating film. A polysilicon resistance film is formed on the field insulating film simultaneously with a floating gate formed in a memory cell region. A polycide conductive film is formed on a interlayer insulating film simultaneously with an auxiliary bit line formed in the memory cell region, and the polycide conductive film is connected to the resistance film by a contact formed in a via hole. A wiring line formed on an interlayer insulating film is connected to the polycide conductive film by a contact formed in a via hole penetrating the interlayer insulating film. The two via holes are formed at positions corresponding to regions in the p-type well. A negative voltage is applied to the wiring line, and the potential of a predetermined point on the resistance film is measured.

Abstract: A method of forming an SRAM cell includes, a) providing a pair of pull-down gates having associated transistor diffusiion regions operatively adjacent thereto, one of the diffusion regions of each pull-down gate being electrically connected to the other pull-down gate; b) providing a pair of pull-up resistor nodes for electrical connection with a pair of respective pull-up resistors, the pull-up nodes being in respective electrical connection with one of the pull-down diffusion regions and the other pull-down gate; c) providing a first electrical insulating layer outwardly of the reistor nodes; d) providing a pair of contact openings, with respective width, through the first insulating layer to the pair of resistor nodes; e) providing a second electrical insulating layer over the first layer and to within the pair of contact openings to a thickness which is less than one-half the open widths; f) anisotropically etching the second electrical insulating layer to define respective electrical insulating annulus s

Abstract: In a SOI structure according to the invention, a substrate region directly adjacent and underlying the buried oxide layer is doped with a dopant having a conductivity type opposite that of the substrate. This produces a junction between the doped layer and the substrate. Appropriately biasing this junction creates a depletion layer, which effectively extends the width of the buried oxide layer deep into the substrate, thereby reducing parasitic capacitance in the SOI structure, particularly for inductors, interconnects, and other passive circuit elements. Reducing parasitic capacitance reduces associated substrate losses and RC propagation delays. These benefits become increasingly important at high frequencies encountered in RF wireless communication and high speed digital applications.

Abstract: An integrated circuit, including a resistor having multiple, series-connected resistor segments formed over multiple tubs of semiconductor material of a first polarity in a semiconductor substrate of the opposite polarity. The resistor is implemented with multiple bootstrapping in the sense that all tubs are coupled to a node of the circuit whose potential changes, in response to a changing input signal, in a direction so as to pull the potential at one end of the resistor in a desired direction. Each resistor segment can be formed over a different one of the tubs, or there are more segments than tubs (e.g., more than one segment formed over one of the tubs or at least one segment having no tub under it). In preferred embodiments, the circuit is a high-speed cascode amplifier (or other amplifier), the resistor is a gain-setting resistor coupled to the top rail, and the tubs are coupled to the amplifier's output.

Abstract: This invention discloses a memory cell that has a first polysilicon, which functions as a gate. The memory cell further includes a first TEOS oxide layer overlying the first polysilicon and a plurality of via-1 openings exposing the first polysilicon therein. The memory cell further includes a patterned second polysilicon layer overlying the first TEOS oxide layer and filling the via-1 openings thus contacting the gate wherein the patterned second polysilicon containing dopant ions for functioning as a connector for the memory cell. The memory cell further includes a second TEOS oxide layer overlying the connector includes a plurality of via-2 openings for exposing the connector therein. The memory cell further includes a silicide barrier layer disposed in the via-2 openings.

Abstract: High-resistance polysilicon layers applied in 4T SRAM memory cells serving as loads, are manufactured by a simple method according to the invention. In the small-scale 4T SRAM memory cell process, it is not possible to fabricate traditional polysilicon loads manufactured by the prior art with a desired high degree of resistance. As a result, the miniaturization of 4T SRAM memory cells has been limited. However, in the method according to the invention, the lengths of polysilicon loads are greatly increased without increasing the sizes of corresponding memory cells, thereby efficiently increasing the resistance of the polysilicon loads. Therefore, this method according to invention can completely eliminate any limitation to the small-scale 4T SRAM memory cell process caused by the manufacture of the polysilicon loads as described above.

Abstract: An aluminum gate for a thin film transistor is fabricating by implanting ions into the exposed surface of the aluminum gate. The ions are preferably selected from the group consisting of nitrogen, carbon, oxygen and boron ions. A composite layer of aluminum and the implanted ions thereby formed at the exposed surface of the aluminum layer. Gates for thin film transistors, including an aluminum layer and a composite layer of aluminum and another element at the surface thereof can suppress hillocks in the aluminum gate which may be caused by compressive stresses during subsequent fabrication steps. The composite layer can have a low resistance and can allow a direct contact with an indium tin oxide conductive layer.

Abstract: A semiconductor device comprises a reference voltage device for outputting a constant voltage, a voltage dividing device receptive of the constant voltage for dividing the constant voltage and outputting different currents, a digital signal processing device receptive of the different currents outputted by the voltage dividing device and outputting voltages, and a voltage amplifying device receptive of at least a ground voltage and one of the voltages outputted by the digital signal processing device and outputting a signal produced by amplifying the voltage of the digital signal processing device.

Abstract: A static RAM has a low resistive contact film disposed in direct contact with a storage node of a memory cell and the gate electrode of a driver transistor in a through-hole, and in direct contact with an end portion of a high-resistance load. An accurate and stable resistance can be obtained for the high-resistance load without raising the contact resistance between the storage node and the gate electrode of the driver transistor.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: The invention encompasses integrated circuits and SRAM cells. In one aspect, the invention includes an integrated circuit comprising: a) an electrically insulative pillar extending substantially vertically outward of an underlying layer, the pillar having opposing substantially vertical side surfaces and a top, the pillar being taller than it is wide; b) a resistor comprising a layer of material which extends along both pillar vertical surfaces and over the top of the pillar; c) a first node in electrical connection with the resistor on one side of the insulative pillar; and d) a second node in electrical connection with the resistor on the other side of the insulative pillar.

Abstract: A resistive structure formed on an integrated circuit substrate is disclosed. The structure includes a plurality of resistive elements serially connected. Each resistive element comprises a forward biased semiconductor junction and a reverse biased semiconductor junction. The resistive value of each resistive element can be varied with a preferred range being from about 500 megohms to about 5 gigaohms. In fabrication, the multiple resistive elements are electrically and physically simultaneously formed and are connected in series to obtain higher resistive values. The disclosed resistive structure allows very high resistances to be obtained using very little planar surface area.

Abstract: The inventive SRAM cell has a poly-load resistor which comprises a thick supply voltage (Vcc) interconnect, a thick driver interconnect on a thin load resistance region which is electrically connected to both interconnects. The novel poly-load resistor overcomes the problem of lateral diffusion from the interconnect regions into the load region. The resulting SRAM cell has a low Vcc interconnect resistance.

Abstract: A three dimensional polysilicon resistor and a method by which the three dimensional polysilicon resistor is manufactured. A semiconductor substrate has formed upon its surface an insulating layer. The insulating layer has a minimum of one aperture formed at least partially through the insulating layer. A polysilicon layer is formed upon the insulating layer and formed conformally into the aperture(s) within the insulating layer. The polysilicon layer is then patterned to form a resistor which includes the portion of the polysilicon layer which resides within the aperture(s).

Abstract: Integrated circuit memory devices having improved supply line connections utilize preexisting semiconductor regions (e.g., N-type well regions) in a semiconductor substrate as interconnect regions between thin polysilicon supply lines and metal supply lines. A semiconductor substrate is provided having a region of first conductivity type semiconductor therein extending to a face thereof. This region of first conductivity type may be formed in a peripheral circuit portion of the substrate. A memory device, such as an SRAM device, is also preferably provided adjacent the face of the substrate, in a memory cell portion of the substrate. The memory device contains at least one polysilicon load element therein having a first resistivity. A polysilicon supply line is also electrically connected in series between the polysilicon load element and the region of first conductivity type.

Abstract: The invention relates to a polysilicon resistor made by forming a film of polysilicon doped with an impurity on a dielectric film on a semiconductor substrate and patterning the polysilicon film. An object of the invention is to provide a polysilicon resistor which has a low resistance value and occupies a small area. A slot is formed in the dielectric film and is filled with the polysilicon film. The dielectric film and the patterned polysilicon film are overlaid with a second dielectric film, and a pair of contact windows are opened in the second dielectric film such that each contact window is partly over an end section of the slot. A plurality of parallel slots can be formed in the first dielectric film to further lower the resistance value or to further reduce the area of the patterned polysilicon film. As an alternative, at least one slot is formed in the substrate and is filled with a polysilicon film after depositing a dielectric film on the substrate surface including the surfaces in the slot(s).

Abstract: A non-volatile memory device includes a substrate having memory cell and peripheral circuit regions thereof. A non-volatile memory cell gate on a memory cell region of the substrate includes a floating gate on the substrate, a first insulating gate on the floating gate opposite the substrate, and a control gate on the first insulating layer opposite the floating gate. A resistor layer is provided on a peripheral circuit region of the substrate, and the second insulating layer is provided on the resistor layer opposite the substrate. In addition, a capping layer is provided on the second insulating layer opposite the resistor layer wherein a contact hole is defined by the second insulating layer and the capping layer thereby exposing a portion of the resistor layer. Related methods are also discussed.

Abstract: A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors having transistor gates formed of a polysilicon layer and resistors formed of the same polysilicon layer. In accordance with a second embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors, a dielectric layer overlying the NMOS transistors, and polysilicon resistors passing through the dielectric layer to connect the NMOS transistors to a first metal layer. The dielectric layer, deposited on the NMOS transistors, defines holes exposing drain regions in the NMOS transistors. A polysilicon layer is deposited on the dielectric layer to fill the holes, and the excess polysilicon is removed.

Abstract: A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions.

Abstract: A power IC is provided which facilitates applying a high voltage to the gate electrode of the MOS semiconductor element for the power output of the power IC to break down defects around the gate oxide film in a short time thereby screening the power ICs efficiently. A gate terminal for testing is led out from the gate electrode of the MOS type semiconductor element for the power output of the power and the screening test is conducted by applying a high voltage to the gate terminal for testing. The expected bad influence of the applied high voltage on the control circuit is avoided by the level shift means or the switching means switched off only during the screening test and short-circuited after the test is over.

Abstract: A barrier layer impedes hydrogen diffusion into polysilicon resistors in circuits in which the resistor resistivity is sensitive to hydrogen diffusion into the resistors. The barrier layer extends laterally throughout the whole integrated circuit except for contact areas in which circuit elements overlying the barrier layer contact conductive elements underlying the barrier layer. The barrier layer includes a layer of polysilicon or amorphous silicon. In some embodiments, the barrier layer includes multiple layers of polysilicon or amorphous silicon that are separated by thin layers of silicon dioxide. In some embodiments, the barrier layer is formed between the polysilicon resistor and PECVD silicon nitride passivation which contains atomic hydrogen.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Abstract: A method of fabricating a polycrystalline silicon thin-film transistor having two symmetrical lateral resistors is disclosed. Two sub-gates are formed along with a gate in the gate metal or polysilicon layer of the thin-film transistor. The two sub-gates that are located symmetrically on the two sides of the gate have equal distances to the gate. One sub-gate is near the drain of the thin film transistor and the other near the source. Two sections in the polycrystalline silicon layer of the thin film transistor are blocked by the two sub-gates and no impurity material is doped. The two undoped sections form the symmetrical lateral resistors of this invention. The lateral resistor near the drain decreases the electric field in the nearby depletion area when the thin-film transistor is switched off. The current leakage is reduced.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: A polysilicon interconnect is formed on a microelectronic circuit substrate for conducting signals from a driver to a non-polycrystalline silicon contact which has higher impedance than the interconnect. A plurality of electronic "speed bumps" are spaced along the interconnect for disturbing or disrupting signals propagating along the interconnect toward the contact and thereby reducing undesirable back reflection and ringing. The speed bumps can include capacitance altering elements in the form of dielectric strips, or resistance altering elements in the form of low resistance doped areas or high resistance amorphous areas. The speed bumps can include first and second elements having different values of capacitance or resistance which are spaced along the interconnect in alternating relation.

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

Abstract: A method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises formation of a polysilicon 1 layer on said semiconductor substrate. The polysilicon 1 layer is patterned and etched. An interpolysilicon layer is formed over the polysilicon 1 layer, patterned and etched forming an opening through the interpolysilicon layer exposing a contact area on the surface of the polysilicon 1 layer. A SIPOS layer forms a resistor material over the interpolysilicon layer in contact with the polysilicon 1 layer through the opening. A load resistor mask is formed over a load resistor region to be formed in the SIPOS layer, and ions are implanted in the remainder of the SIPOS layer not covered by the load resistor mask to convert the remainder of the SIPOS layer from a resistor into an interconnect structure integral with a load resistor in the load resistor region.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: A base insulator film comprised of a silicon oxide film or the like is formed on the surface of a silicon substrate, and a non-doped polysilicon film (resistor layer) is selectively formed on the base insulator film by thermal CVD. A first silicon oxide film and a BPSG film are sequentially formed on the entire surfaces of the base insulator film and the polysilicon film. Then, two openings which reach the polysilicon film are formed in the BPSG film and the first silicon oxide film, and an impurity is selectively doped into the surface of the polysilicon film through those openings. As a result, a high-resistance section is formed in the polysilicon film between the two openings. Then, the openings are filled with metal layers, and then metal wires to be connected to the metal layers are formed on the surface of the BPSG film.

Abstract: A resistive structure formed on an integrated circuit substrate is disclosed. The structure includes a plurality of resistive elements serially connected. Each resistive element comprises a forward biased semiconductor junction and a reverse biased semiconductor junction. The resistive value of each resistive element can be varied with a preferred range being from about 500 megohms to about 5 gigaohms. In fabrication, the multiple resistive elements are electrically and physically simultaneously formed and are connected in series to obtain higher resistive values. The disclosed resistive structure allows very high resistances to be obtained using very little planar surface area.

Abstract: A high power resistor is formed of a wafer of silicon captured between two molybdenum electrodes. A P-I-N diode of ring shape or wafer shape is concentric with a silicon resistor and has surfaces which are coplanar with the silicon resistor to form a device having an integrated diode and resistor.

Abstract: A method of forming an SRAM cell includes, a) providing a pair of pull-down gates having associated transistor diffusion regions operatively adjacent thereto, one of the diffusion regions of each pull-down gate being electrically connected to the other pull-down gate; b) providing a pair of pull-up resistor nodes for electrical connection with a pair of respective pull-up resistors, the pull-up nodes being in respective electrical connection with one of the pull-down gate diffusion regions and the other pull-down gate; c) providing a first electrical insulating layer outwardly of the resistor nodes; d) providing a pair of contact openings, with respective widths, through the first insulating layer to the pair of resistor nodes; e) providing a second electrical insulating layer over the first layer and to within the pair of contact openings to a thickness which is less than one-half the open widths; f) anisotropically etching the second electrical insulating layer to define respective electrical insulating ann

Abstract: An apparatus and method are provided for bypassing the emitter ballast resistors of a power transistor, thereby increasing transistor gain. In a power transistor of the interdigitated type, bypassing the emitter ballast resistors requires bypassing each individual ballast resistor with a capacitor in parallel. Bypassing is therefore done on the silicon chip. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, an emitter ballast resistor formed on the silicon die, and a bypass capacitor formed on the silicon die and connected in parallel with the emitter ballast resistor. The resistor may be a diffused resistor, and the capacitor may be a metal-on-polysilicon capacitor.

Abstract: In a semiconductor device adapted to be driven while being cooled in operation and having one input/output terminal to which an element to be protected is connected, a protection circuit consists of a protection element electrically connected between the input/output terminal and a semiconductor substrate. This protection element has no polarity in a current-to-voltage characteristic but has a negative temperature coefficient of resistivity. The protection element exhibits a low resistance at a room temperature but becomes insulative or exhibits a high resistance at an operating temperature of the semiconductor device.