Abstract: An N.sup.- -type epitaxial layer is formed on a P-type semiconductor substrate. A P-type region is formed in the N.sup.- -type epitaxial layer. First and second N.sup.- -type layer islands, isolated by the P-type region, are formed in the N.sup.- -type epitaxial layer. An N.sup.+ +-type contact region is formed in a surface region of the first N.sup.- -type layer island. A pad electrode is formed above the first N.sup.- -type layer island with an oxide film interposed therebetween. A polysilicon layer serving as a resistor is formed above the second N.sup.- -type layer island with the oxide film interposed therebetween. A first conductive layer for electrically connecting the polysilicon layer with the N.sup.+ -type contact region is formed on the polysilicon layer, the N.sup.+ -type contact region and the oxide film. A second conductive layer for electrically connecting the polysilicon layer with a stable high-potential power source is formed on the oxide film and the polysilicon layer.

Abstract: In a semiconductor polycide resistive element having a first region of polysilicon of one conductivity type and second regions of polysilicon of opposite conductivity type, with silicide overlying the polysilicon but not the first region, the edges of the silicide are spaced apart from the boundaries between the opposite conductivity types.

Abstract: In a semiconductor device, an undoped polysilicon layer on the uppermost layer is used as a resistor having a high resistance without any patterning. A metal wiring layer formed on this resistor is connected to a conductive layer formed below the resistor via a contact hole extending through the high resistor device. In addition, by oxidizing an end portion, exposed in the contact hole, of the resistor, an oxide film is interposed between the high resistor device and the metal wiring layer to attain electrical insulation therebetween. In this manner, the resistor is formed of the undoped polysilicon layer by using a multilayered polysilicon structure including the undoped polysilicon layer. Therefore, the integration degree can be increased, and at the same time, a stepped portion accompanying the multilayered silicon structure is relaxed to improve the flatness of the surface and prevent poor step coverage or bridging of an upper wiring layer.

Abstract: A static random access memory (SRAM) device and a manufacturing method thereof are provided. In the SRAM memory device, a first active region of annular shape and a second active region bisecting the annulus are repeatedly formed over the whole cell array. Thus, since the contact hole for connecting the power line to the active region can be formed larger without increasing the cell size, contact resistance can be decreased. Also, the manufacturing method can be simplified since just one gate oxide layer formation process is needed.

Abstract: An emitter switched thyristor (EST) has improved turn-off withstand capability without deteriorating its on-voltage. The EST obtains a potential drop through a resistor disposed between the main electrode and the base region and facilitates uniformly recovering the reverse-blocking ability of the PN junction, in contrast to the ESTs of the prior art which obtain the potential drop by the current in Z-direction for latching up the thyristor from the IGBT mode. The present EST may be formed also in a horizontal device or a trench structure.

Abstract: A semiconductor device comprises a silicon semiconductor substrate and an insulating film formed on a surface of the silicon semiconductor substrate. One of a surface of the silicon semiconductor substrate or a surface of the insulating film is provided with at least one step portion. A polycrystalline silicon layer is formed uniformly on at least a side surface of the step portion and a top surface of the insulating film. The polycrystalline silicon layer which is formed on the side surface of the step portion comprises a resistance element, and a portion of the polycrystalline silicon layer which is formed on the top surface of the insulating film is doped with an impurity to form a conductive element. By this construction, the area occupied by the load devices on the semiconductor substrate is effectively reduced, thereby increasing the packing density of the semiconductor device.

Abstract: An integrated circuit structure contains both highly resistive regions and highly conductive interconnect regions in a single layer of polycrystalline silicon. The resistive regions have a smaller cross section than the interconnect regions as a result of partial oxidation. Their thickness and width are reduced from that of the interconnect regions. The partial oxidation leaves an oxide region, derived from polycrystalline silicon, on both the top and sides of the resistive regions.

Abstract: A digital potentiometer adapted for and connected to and interacting directly with a plurality of external switches. Specifically, the various wiper points of a semiconductor resistor array are selected, for each channel of an audio amplification device according to various switch selections. The method and apparatus disclosed also makes priority determinations if more than one external switch is selected at the same time according to which switch was selected first.

Abstract: A polysilicon gate resistor consists of a plurality of parallel polysilicon strips extending from gate finger to gate pad. Different numbers of parallel strips can be selected during manufacture by using different contact masks.

Abstract: In a preferred embodiment, a diffused leakage resistor of a high value between approximately 200K ohms and 5M ohm is formed proximate to an MOS power transistor on the same silicon chip. The manufacturer of the chip has the option, using a mask, to connect or not connect the dedicated leakage resistor between the transistor's source and gate during the fabrication of the chip. The resistor is formed using the same masking steps already used to form the MOS transistor. To increase the sheet resistivity (ohms per square) of the resistor, a novel method is used to cause the effective width of the diffused resistor to be substantially narrower than the actual drawn width dimension on the mask. Also using this novel method, the concentration and depth of the dopants forming the resistor diffused region are less than that of the source and drain regions. The resulting resistor will thus have a much higher sheet resistivity than is achieved using conventional methods.

Abstract: A precision resistor, on a semiconductor substrate, formed by using two polysilicon stripes to mask the oxide etch (and ion implantation) which forms a third conductive stripe in a moat (active) area of the substrate. The sheet resistance R.sub.p and a patterned width W.sub.p of the polysilicon stripes and the patterned width W.sub.M and sheet resistance R.sub.M, are related as R.sub.p W.sub.p =2R.sub.M W.sub.M. By connecting the three stripes in parallel, a net resistance value is achieved which is independent of linewidth variation.

Abstract: A voltage programmable link structure reduces parasitic capacitance by using ion implantation. The voltage programmable link structure includes a first conductive element placed over a substrate. A transformable insulator is deposited over the first conductive element. The transformable insulator material is deposited with an ion implanted layer. A second conductive element is deposited over the ion implanted layer. An electrical path is formed between the first and second conductive elements by applying a voltage between the elements across at least one region of the insulator, such that the insulating material is transformed and rendered conductive to form an electrical signal path.

Abstract: A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).

Abstract: An improved configuration of a capacitor formed with FET technology and a resistor and/or conductor is provided. In this configuration a capacitor is formed in which the diffusion zone of the substrate is used as one plate of the capacitor and what would normally be the gate electrode of an FET is used as the other plate of the capacitor, with the two plates being separated by a conventional thin dielectric gate oxide layer. An insulator, such as silicon dioxide overlays the gate electrode, and electrical connections to the gate electrode and diffusion zone are made through the insulator to allow the two plates of the capacitor to be connected to various devices or components as required. The top surface of this insulation layer is also used to form metal resistors. Depending on the value of required resistance, a second insulating layer may be used and a second level of metal used to connect segments of the resistors formed on the first layer of metal to form a longer resistor.

Abstract: A static-type memory cell includes a flip-flop circuit formed with a pair of N-channel type MOS transistors for driving provided in a semiconductor substrate and a pair of P-channel type MOS transistor as load elements provided in the upper layer of the pair of driving N-channel type MOS transistors and formed with thin film transistors. The gate electrodes of the pair of P-channel type MOS transistor are load elements and are formed of polycrystalline silicon layers containing 2 to 45 atoms % of oxygen for maintaining high resistance in the P-channel type MOS transistor and thereby provide satisfactory resistance against soft errors.

Abstract: An insular shaped polycrystalline silicon film is formed by adhering its entire bottom face to the surface of a insulation film which is formed on the main face of a silicon substrate. A resistance element which contains designated impurities is formed in the central part of the polycrystalline silicon film. A non-doping region which essentially does not contain impurities and is adheres to all the sides of the resistance element, is positioned on the peripheral region except for the central part of the polycrystalline silicon film. By performing heat treatment when a non-doping amorphous silicon pattern is formed on the insulating film, the amorphous silicon pattern is convened to a non-doping polycrystalline silicon pattern. By using this method, a semiconductor device which has only small variances in its resistance value, which provides more efficient heat radiation, and which enables higher integration of a silicon substrate can be obtained.

Abstract: A semiconductor device is disclosed that can effectively prevent a change in the resistance ratio of polysilicon resistor films when a plasma nitride film is formed above a plurality of polysilicon resistor films. The semiconductor device has metal interconnection layers 5a and 5b formed above polysilicon resistor films 3a and 3b, respectively. The ratio of the overlapping area of the polysilicon resistor film 3a and the metal interconnection layer 5a is set to be substantially equal to that of the polysilicon resistor film 3b and the metal interconnection layer 5b.

Abstract: A semiconductor device includes a resistor network having a plurality of trimming polysilicon resistors. The polysilicon resistors have the same width and different lengths and can be selectively fused according to the value of current which is caused to flow therein. The resultant resistance of the resistor network is changed by selectively fusing the polysilicon resistors. The output characteristic of the semiconductor device can be adjusted by changing the resultant resistance.

Abstract: Dielectrically isolated trench fill material is used for the formation of one or more isolated resistor elements within respective ones of a plurality of dielectrically isolated island components in which circuit devices are formed, or in adjacent substrate material. A respective island may have a plurality of trench strip resistor devices, which may have the same or differing resistor values depending upon their geometries or doping concentrations. In addition, the resistor-containing architecture may include one or more conductive cross-unders each defined by a respective cross-under trench strip. A cross-under trench strip contains conductive material, such as heavily doped polysilicon, as opposed to lightly doped polysilicon of the resistor fill material.

Abstract: A resistor structure (10) having a heating element (35) and a resistor (32), and a method of trimming the resistor (32). The heating element (35) is separated from the resistor (32) by a layer of dielectric material (19). The resistor (32) has a layer of resistive material (23) on an etch control layer (22). The resistor (32) is trimmed by providing current pulses (62) through the heating element (35). Heat generated by the current pulses flows to the resistor (32) and anneals or trims the resistor (32). A resistor trimming variable, e.g. a voltage across resistor contacts (30, 31), is monitored and the current pulses are modulated in accordance with the value of the resistor trimming variable (63). The trimming step is terminated when the desired resistance value of the resistor (32) is attained.

Abstract: An integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.

Abstract: A resistor circuit (and structure) 10 is disclosed herein. A first resistor 14 has a first temperature coefficient of resistance and is coupled to a second resistor 16 which has a second temperature coefficient of resistance, typically opposite to the first temperature coefficient of resistance. The resistors 14 and 16 are coupled together (e.g., in series or in parallel) to create a total resistor with a predetermined (e.g., substantially zero) temperature coefficient of resistance.

Abstract: Apparatus for improving ON/OFF switching in high speed digital circuitry is disclosed. The present invention includes apparatus for altering the impedance or capacitive loading of the interconnect. Some embodiments reduce back reflections by raising the impedance of the interconnect to be closer to that of the contact, or raising the capacitive loading, and others improve the culprit-victim problem by filtering out the highest frequency components of the pulse on the culprit interconnect. For the back reflection problem, the apparatus for altering can be formed of elements for altering the capacitance or, alternatively the resistance, of the interconnect. For the culprit-victim problem, the apparatus for altering includes elements which alter the effective capacitance or resistance of the culprit interconnect.

Abstract: A semiconductor device provides for shielding of resistance elements as well as other elongated passive or active components formed in the structure by diffusion of impurities into a polycrystalline silicon layer or a semiconductor substrate and a conductor is formed on an upper surface of the resistance element having a resistance value lower than that of the formed resistance element. Also, the conductor is formed so as to hold a fixed potential value. This structure prevents an invasion or infiltration of impurities which causes a variation in the resistance value of the resistance element. Further, the conductor functions as shielding from noise from a signal line in close proximity to the resistance element or from external noise by means of fixing the conductor at a fixed potential value thereby maintaining the stability of the resistance value of the resistance element.

Abstract: In a semiconductor device, a signal delay element is configured by using resistance and capacitance components included in a region except regions where logic elements for a gate array exist, and the signal delay element is inserted between a logic element for outputting signals and logic elements for receiving the signals and connected to these logic elements. A placing and wiring apparatus for producing the semiconductor device is disclosed.

Abstract: Semicondctor devices having a curved P-N junction in an active area of the device and an edge passivation region extending from the active area to an edge region of the device include an electrically resistive ribbon that spirals outwardly from the active area to the edge of the device so that a voltage difference between the active area and the edge region is spread along the length of the ribbon. The ribbon may take the form of a linear resistor or may include plural diodes. The distance between radially overlapping portions of the spiralling ribbon and the cross-sectional area of the ribbon may be varied to spread the equipotential lines in the device so as to reduce the effect of the curved P-N junctions on the breakdown voltage of the device.

Abstract: An integrated circuit terminator for a SCSI bus with resistors made of laser-blowable fuses in an array and a reference voltage source made with a bandgap generator and a two stage amplifier including a dummy isolation stage for providing symmetrical mismatch currents.

Abstract: The memory ratio is improved and the data holding ability on reading data is enhanced by providing a resistive element between an access transistor and a flip-flop, which form a memory cell of a static memory. Even if the threshold voltage of the access transistor is lowered, the memory cell ratio can be increased. Accordingly, the minimum operating voltage can be lowered and the operating margin for a power source voltage can be increased and simultaneously with this, the soft error immunity can be enhanced. Since the memory cell ratio of the semiconductor memory of the present invention is enhanced by the resistive element, the necessity to preset a lower current drive ability of the access transistor for a drive transistor is decreased. As a result of this, the size of the memory cell can be decreased. Further, the current consumed by the memory cell is decreased by the resistive element.

Abstract: A transistor structure incorporates a polysilicon layer which is doped with N-type dopants and is used as an emitter ballast resistor in an array of NPN transistors. In one embodiment, the polysilicon layer is also used as a diffusion source to form N-type emitter regions within a deep and high resistivity P-well, which acts as a relatively high value base ballast resistor for the transistor. In another embodiment, a standard base is used, contributing little base ballast resistance. A buried collector region carries collector current. Preferably, the emitter regions are formed as oblong strips. P-type base contact regions, also generally formed as oblong strips, are formed in the surface of this P-well parallel to the emitter regions. The dimensions of the base contact regions may be varied in order to achieve a constant base-emitter voltage along the entire length of each emitter strip.

Abstract: A polyemitter structure having a thin interfacial layer deposited between the polysilicon emitter contact and the crystalline silicon emitter, as opposed to a regrown SiO.sub.x layer, has improved reproducibility and performance characteristics. A n-doped hydrogenated microcrystalline silicon film can be used as the deposited interfacial film between a crystalline silicon emitter and a polycrystalline silicon contact.

Abstract: A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench.

Abstract: A thin film integrated circuit resistor is disclosed that is substantially linear at applied voltages greater than 100 volts. The integrated circuit resistor comprises a substrate, a plurality of resistive blocks electrically connected in series, a shield associated with each resistive block, and passivation means for isolating the substrate from the resistive blocks and the shields, and for isolating the shields from the resistive blocks except where they are electrically connected. Each shield substantially surrounds its associated resistive block with conductive material, and each shield is electrically connected to its resistive block such that each shield is at a potential of some point along the length of its associated resistive block.

Abstract: A polysilicon layer is provided with a p-type impurity, and masked with an oxide mask to define a p-type region of the polysilicon layer. A second impurity is then provided into first unmasked regions of the polysilicon layer. A second oxide mask is deposited and anisotropically etched to form spacers adjacent to the first oxide mask. The spacers define two diffusion barrier regions of the polysilicon layer adjacent to the p-type region. An n-type impurity is then provided into second unmasked regions of the polysilicon layer to form two n-type regions adjacent the diffusion barrier regions. The diffusion barrier regions prevent cross diffusion of the p-type and the n-type impurities within the polysilicon layer, while also being of sufficient dimensions to permit normal p/n operations.

Abstract: A multi-emitter type semiconductor device having multiple transistors coupled in parallel which utilize a common substrate. Between a selected emitter electrode and a base contact, a stabilizing resistive region is formed in the common substrate. In order to reduce the parasitic effects due to this region an additional emitter ballast resistor may be formed on the surface of an insulating layer over the substrate. This supplemental resistor formed on the insulating layer is made from polycrystalline silicon. Alternatively, the supplemental resistor can be combined with the resistance of the stabilizing region in a single resistor located on the surface of the insulating layer.

Abstract: A linear and symmetrical gigaohm resistive load structure for an integrated circuit is implemented using a thin film accumulation mode MOSFET configured as a split gate symmetrically off device. Preferably, the resistive load structure comprises two thin film accumulation mode field effect transistors connected in series with a common node and separate gate electrodes. The thin film devices are provided with undoped or lightly doped polysilicon channel regions to provide a desired gigaohm resistance value. By connecting each of the two gate electrodes to the respective source terminals, a two terminal gigaohm resistor structure is produced in which one of the devices is always in the high impedance OFF state regardless of the terminal voltages. The split gate structure allows the integration of the device with minimal metallization interconnect and only two terminals.

Abstract: A self-aligned vertical intrinsic resistance for use in semiconductor devices is developed. The self-aligned vertical intrinsic resistance may be used in a variety of designs, such as functioning as a pullup device in integrated circuits and more specifically for use as a pullup resistor in SRAM devices. The vertical positioning of the intrinsic resistance not only takes up less die space but also allows for a simple process to construct the resistance by eliminating a photomask step that is normally required prior to implanting an intrinsic resistance used in conventional fabrication processes.

Abstract: A method including covering the area to be laser trimmed with a first insulative layer having a thickness sufficiently thin that a layer can trim the area through the first insulative layer. An etch stop is formed on the first insulative layer over the area to be trimmed and covered with a second insulative layer. A portion of the second insulative layer is etched to expose the etch stop and a portion of the etch stop is then removed to expose a portion of the first insulative layer and laser trimming is conducted through the exposed first insulative layer. The etch stop is part of a first level of interconnects made of the same material and simultaneously with the etch stop. The area to be trimmed is part of a second level of contacts that interconnect another second material.

Abstract: Herein disclosed is a vertical-type field effect transistor having a parallel connection of a diode and a resistor between the gate bonding pad and the gate electrode of the transistor to adjust the switching speed of the transistor without changing the other properties of the transistor.

Abstract: A polycrystalline silicon layer 9 for a base leading electrode is formed on an element forming region divided by an element isolating layer which is formed by burying a BPSG film 8 in a groove. A depression generated on the element isolating layer is filled with a PSG film 11 which is formed as a part of an interlayer insulating film on the surface of the device including the polycrystalline silicon layer 9 by the spin-coating method so that the upper surface of the device is flattened. A polycrystalline silicon layer 13 is provided on the element isolating layer as a resistor layer so that the resistor layer is disposed between the adjacent transistors. The area of a circuit block is reduced to achieve a high integration and reduction in parasitic capacitance. This enables the high speed operation.

Abstract: A class of layout patterns for variable resistors and integrated circuits where the resistance is varied by varying a wiping point on a resistor line; contact is not made into the resistor line itself, but instead all contacts are made only to tabs which extend out from the resistor line. Preferred embodiments use a meander resistor line made of polysilicon within a silicon integrated circuit. Simple processing mask modifications can be used to change the geometry of the meander line to vary the resistance. The wiping point is digitally selected.

Abstract: An integrated semiconductor circuit includes a substrate, an epitaxial layer having transistor base regions, a first and a second (11) insulating oxide layer, and a protective layer. The first oxide layer carries heavily doped polycrystalline layers, including an electric contact layer, a screening layer and a connecting layer. The connecting layer electrically connects the screening layer to the epitaxial layer, through the electric contact layer. The screening layer prevents the occurrence of inversion and parasite components in the epitaxial layer between the base regions. The polycrystalline layer arrangement is simple and can be produced in a common process step. The arrangement is able to withstand high temperatures and enables the second insulating layer to be readily applied.

Abstract: A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.

Abstract: A semiconductor device provided with a polycrystalline silicon resistor containing an impurity in a high concentration and having a resistance adjusted by a current conduction therethrough at a current density of a threshold value or more, which comprises: a polycrystalline silicon resistor containing a first impurity having a negative value of a temperature coefficient of resistance in a high impurity concentration region of said polycrystalline silicon resistor and a second impurity having a positive value of a temperature coefficient of resistance in a high impurity concentration region of the polycrystalline silicon resistor. A process for producing same is also disclosed.

Abstract: A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.