Abstract: Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a buffer layer of the semiconductor device. For instance, a semiconductor device includes a buffer layer disposed on a substrate, a channel layer disposed on the buffer layer, and a buried resistor disposed within the buffer layer. The buffer and channel layers may be formed of compound semiconductor materials such as III-V compound semiconductor materials. Utilizing the buffer layer of a compound semiconductor structure to form buried resistors provides a space-efficient design with increased integration density since the resistors do not have to occupy a large amount of space on the active surface of a semiconductor integrated circuit chip.

Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.

Abstract: It is possible to suppress a change in a resistance value caused by a potential of a semiconductor substrate 10 near a resistance element layer 13, a power line passing on or above the resistance element layer, or a signal line, without generating useless current or a distortion in a signal. A first conductive layer 15 biased by the potential of a first electrode 11 and a second conductive layer 16 biased by the potential of a second electrode 12 cover below the resistance element layer equally. A change in the resistance value caused by a potential difference between the resistance element layer and a neighboring semiconductor substrate 14 is cancelled by the first conductive layer and the second conductive layer covering at least one of above and below the resistance element layer with both ends biased, so the change in the resistance value is suppressed.

Abstract: In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate.

Abstract: A nonvolatile memory device having two or more resistors and methods of forming and using the same. A nonvolatile memory device having two resistance layers, and more particularly, to a nonvolatile memory device formed and operated using a resistance layer having memory switching characteristics and a resistance layer having threshold switching characteristics. The nonvolatile semiconductor memory device may include a lower electrode; a first resistance layer having at least two resistance characteristics formed on the lower electrode, a second resistance layer having threshold switching characteristics formed on the first resistance layer, and an upper electrode formed on the second resistance layer.

Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

Abstract: A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current path through the first region is determined by a portion of a doping boundary between the first region and the second region.

Abstract: A phase change memory device and, more particularly, to a phase change memory cell array suitable for the implementation of a high-density memory device. The phase change memory cell array includes a first access transistor pair and a second access transistor pair formed on a semiconductor substrate to be adjacent to each other while each of the first and second access transistor pairs having a common drain, phase change resistance elements formed on source regions of the access transistors, respectively, and a semiconductor region formed on the same plane as the common drains to electrically connect the common drains of the first and second transistor pairs. The phase change memory cell array and the memory device of are suitable for the implementation of a high-density semiconductor device, and capable of improving the reliability of a contact forming process by securing a sufficient space for the contact forming process.

Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a polysilicon resistor film formed on the first insulating film; a second insulating film formed on the resistor film; a high heat conductor film consisting of a highly heat-conducting material formed on the second insulating film; and a pair of terminal wirings formed on the second insulating film and connected to the resistor film, in which a thickness T3 of the second insulating film is thinner than a thickness T2 of the resistor film.

Abstract: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

Abstract: A semiconductor device having a semiconductor resistance element is capable of suppressing a variation in characteristics of the semiconductor resistance element due to an acceptor concentration which is difficult to control, thereby stably improving the yield of a semiconductor integrated circuit using the semiconductor device. The device includes an n-type semiconductor resistance region formed in the surface of a compound semiconductor substrate, and a p-type buried region formed between the n-type semiconductor resistance region and a substrate region 21S of the compound semiconductor substrate. An acceptor of the p-type buried region is set to be higher than an acceptor concentration in the substrate region and lower than a donor concentration in the n-type semiconductor resistance region, whereby the effect of the acceptor concentration in the substrate on the semiconductor resistance region can be avoided.

Abstract: A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.

Abstract: A monolithic sensor includes a reference channel and at least one sensing channel. Each sensing channel has an oscillator and a counter driven by the oscillator. The reference channel and the at least one sensing channel being formed integrally with a substrate and intimately nested with one another on the substrate. Thus, the oscillator and the counter have matched component values and temperature coefficients. A frequency determining component of the sensing oscillator is formed integrally with the substrate and has an impedance parameter which varies with an environmental parameter to be measured by the sensor. A gating control is responsive to an output signal generated by the reference channel, for terminating counting in the at least one sensing channel at an output count, whereby the output count is indicative of the environmental parameter, and successive ones of the output counts are indicative of changes in the environmental parameter.

Abstract: Based on a relationship between cutting-and-removing amounts for partly cutting out the stub of the pattern line and impedances of the matching circuit, a cutting-and-removing amount for adjusting the impedance to a target value is determined by simulation or by comparison operation of an impedance measured value with information stored in a database. Then, based on the determined cutting-and-removing amount, the stub of the pattern line is partly cut and removed so that the impedance is adjusted to the target value.

Abstract: A layered capacitor device with high capacitance per unit area is realized by alternating in the vertical direction first layers (FL1, FL2, FL3, FL4, FL5) and second layers (SL1, SL2, SL3, SL4). A first layer (FL2) consists of horizontally alternating electrically conducting tracks (T2,2; T2,3) and electrically insulating tracks, whereas a second layer includes of electrically insulating material, e.g. an oxide. In this way top-bottom capacitors (CTB) and side-wall capacitors (CSW) are constituted that are parallel coupled to form the layered capacitor device. In a preferred embodiment of the invention, this parallel coupling is realized by conductively interconnecting diagonally neighboring electrically conducting tracks (T1,2; T2,3).

Abstract: The continuing miniaturization of integrated circuits leads to a demand for ever higher resistance values. In conventional diffused resistors or poly resistors, an increase in the resistance value also means an increase in the surface area. Such resistors, moreover, are highly dependent on the doping concentration and sensitive to temperature changes. A resistor according to the invention comprises a resistor region 18 with a length and doping concentration which are chosen such that an electric field is applied at which velocity saturation of charge carriers takes place in the envisaged range of operation. The connection regions are connected to the resistor region via rectifying junctions 21, 22. In a specific embodiment, these junctions are formed by pn junctions, so that the resistor has, for example, an npn shape.

Abstract: An IC is constructed with deep layers preventing current flow due to parasitic transistors formed within the IC. Reverse current in case of voltage source polarity reversal is prevented by means of the reverse bias diodes formed by the addition of a P+ ring, and N+ well, for the embodiment disclosed.

Abstract: On a semiconductor substrate, a thin film resistor and a metal wiring for electrically extracting the thin film resistor are formed via a firth interlayer insulator. A second interlayer insulator covering the thin film resistor and the metal wiring is formed on the first insulation layer. By removing the portion of the second interlayer insulator above the thin film resistor by etching, the insulator above the thin film resistor is provided thinner thickness. A heat radiating metal layer is formed on the second interlayer insulator having the thinner thickness.

Abstract: A semiconductor integrated circuit device is provided with, in a land formed on a semiconductor substrate, a plurality of resistor layers constituted by semiconductor layers of a conductive type reverse to that of the land, and two of the plurality of the resistor layers are connected in series between a supply voltage and a reference potential. The land of the reference potential side resistor layer of the resistor layers connected in series is formed separately from the lands of the other resistor layers, and a voltage lower than a voltage applied to the other resistor layers is applied to the reference potential side resistor layer.

Abstract: A thin film integrated circuit resistor is disclosed that is substantially linear at applied voltages greater than 100 volts. The integrated circuit resistor comprises a substrate, a plurality of resistive blocks electrically connected in series, a shield associated with each resistive block, and passivation means for isolating the substrate from the resistive blocks and the shields, and for isolating the shields from the resistive blocks except where they are electrically connected. Each shield substantially surrounds its associated resistive block with conductive material, and each shield is electrically connected to its resistive block such that each shield is at a potential of some point along the length of its associated resistive block.

Abstract: Liquid cleaning preparations for hard surfaces containing(a) 0.5 to 40% by weight, preferably 5 to 20% by weight, of a surfactant or a surfactant mixture;(b) 0.01 to 1% by weight, preferably 0.05 to 0.5% by weight, of cleaning enhancer;(c) 0 to 6% by weight, preferably 1.0 to 6% by weight, of at least one organic and/or inorganic builder;and up to a total of 100% by wiehgt, based on the total weight, of water, and optionally, one or more of solubilizers (solvents, hydrotropes), preservatives, antimicrobial agents, viscosity regulators, pH regulators, perfumes, and dyes. Component (b) is a mixture of (i) at least one polyacrylamide and (ii) at least one highly polyethoxylated monofunctional or polyfunctional alkanol.