Combined With Bipolar Transistor Patents (Class 257/539)
  • Patent number: 9698749
    Abstract: An impedance matching device is presented. The device includes an input terminal configured to receive a radio frequency signal, and an output terminal configured to couple to an amplifier. The device includes an impedance prematch network coupled to the input terminal and the output terminal. The impedance prematch network includes a first inductor, such as a first wire bond. The device includes a resonator structure including a second inductor, such as a wire bond, inductively coupled to the first inductor.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 4, 2017
    Assignee: NXP USA, INC.
    Inventor: Nick Yang
  • Patent number: 9603551
    Abstract: An inductive respiration sensor (10) comprises an inductive transducer (12) and sensing circuitry. The sensing circuitry comprises a transimpedance amplifier, TIA, (14), the sense input (16) of which is operatively connected to the inductive transducer. The TIA is configured to drive a current from its output (20) into the sense input such that the voltage on the sense input follows the voltage applied to the reference input (18) and to cause a voltage on the output indicative of the current. The TIA comprises a first (34) and a second (30) transistor. The collector or drain and the emitter or source of the first transistor are operatively connected between the sense input and the output of the TIA. The emitter or source of the second transistor is connected to the reference input, the collector or drain of the second transistor is connected to the base or gate of the first transistor, and the base or gate of the second transistor is connected to the sense input.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: March 28, 2017
    Assignee: IEE International Electronics & Engineering S.A.
    Inventor: Laurent Lamesch
  • Patent number: 8975663
    Abstract: There is provided a semiconductor device such that it is possible to average the temperatures of a plurality of semiconductor chips simply by providing gate resistors. The semiconductor device includes a semiconductor module wherein a plurality of circuit substrates on which are mounted one or more semiconductor chips having a gate terminal and a gate resistor connected to the gate terminal are disposed in parallel, wherein the disposition distance of the gate resistor from the semiconductor chip is set based on the temperature of the semiconductor chip.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: March 10, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yujin Okamoto
  • Patent number: 8896093
    Abstract: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 25, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Shekar Mallikararjunaswamy, Madhur Bobde
  • Patent number: 8866194
    Abstract: A semiconductor device (npn bipolar transistor) includes an n-type collector layer, a base layer constituted by a p+ diffusion layer, a SiGe layer and a p-type silicon film, an n-type emitter layer and a charge transport prevention film formed between the n-type collector layer and the n-type emitter layer and having an effect as a potential barrier with respect to either electrons or holes.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shinya Naito, Hideaki Fujiwara, Toru Dan
  • Patent number: 8847350
    Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Chieh Lin, Kuoyuan (Peter) Hsu, Wei-Li Liao, Yun-Han Chen, Chen-Ming Hung
  • Patent number: 8816436
    Abstract: A fin resistor and method of fabrication are disclosed. The fin resistor comprises a plurality of fins arranged in a linear pattern with an alternating pattern of epitaxial regions. An anneal diffuses dopants from the epitaxial regions into the fins. Contacts are connected to endpoint epitaxial regions to allow the resistor to be connected to more complex integrated circuits.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8786024
    Abstract: A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: July 22, 2014
    Assignees: Yoshitaka Sugawara, Fuji Electric Co., Ltd.
    Inventor: Yoshitaka Sugawara
  • Publication number: 20140167218
    Abstract: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Inventors: Shekar Mallikarjunaswamy, Madhur Bobde
  • Patent number: 8648386
    Abstract: A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: February 11, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Wing-Chor Chan, Shyi-Yuan Wu
  • Publication number: 20130264682
    Abstract: A transistor includes: a semiconductor substrate; a first electrode on the semiconductor substrate and having first and second portions; a second electrode on the semiconductor substrate and spaced apart from the first electrode; a control electrode on the semiconductor substrate and disposed between the first electrode and the second electrode; and a first heat sink plate joined to the second portion of the first electrode without being joined to the first portion of the first electrode.
    Type: Application
    Filed: February 11, 2013
    Publication date: October 10, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoshinobu Sasaki, Hitoshi Kurusu
  • Publication number: 20130153959
    Abstract: An allowable current amount of a ballast resistance is increased without increasing the width of the ballast resistance. At least one of resistances included in a ballast resistance has a first resistance and a second resistance. The first resistance extends in a first direction (X direction in FIG. 1) in which current flows in a protection element. The second resistance element is coupled in parallel to the first resistance element and extends in the first direction. The second resistance element and the first resistance element are located on the same straight line.
    Type: Application
    Filed: November 3, 2012
    Publication date: June 20, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: RENESAS ELECTRONICS CORPORATION
  • Patent number: 8466535
    Abstract: The spikes in current and voltage that result from the failure of a galvanic dielectric layer are safely contained by a galvanic isolation fuse that pops and forms and open circuit between a high-voltage die and a low-voltage die in response to the failure of the galvanic dielectric layer.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: June 18, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French, Ann Gabrys, Martin Fallon
  • Patent number: 8421189
    Abstract: An apparatus includes an electrostatic discharge (ESD) protection device. In one embodiment, the protection device electrically coupled between a first node and a second node of an internal circuit to be protected from transient electrical events. The protection device includes a bipolar device or a silicon-controlled rectifier (SCR). The bipolar device or SCR can have a modified structure or additional circuitry to have a selected holding voltage and/or trigger voltage to provide protection over the internal circuit. The additional circuitry can include one or more resistors, one or more diodes, and/or a timer circuit to adjust the trigger and/or holding voltages of the bipolar device or SCR to a desired level. The protection device can provide protection over a transient voltage that ranges, for example, from about 100 V to 330V.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: April 16, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Edward Coyne
  • Publication number: 20130049067
    Abstract: A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsin-Liang Chen, Wing-Chor Chan, Shyi-Yuan Wu
  • Publication number: 20130032863
    Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 7, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Marie Denison, Sameer Pendharkar, Philip L. Hower, John Lin, Robert A. Neidorff
  • Publication number: 20120286396
    Abstract: An apparatus includes an electrostatic discharge (ESD) protection device. In one embodiment, the protection device electrically coupled between a first node and a second node of an internal circuit to be protected from transient electrical events. The protection device includes a bipolar device or a silicon-controlled rectifier (SCR). The bipolar device or SCR can have a modified structure or additional circuitry to have a selected holding voltage and/or trigger voltage to provide protection over the internal circuit. The additional circuitry can include one or more resistors, one or more diodes, and/or a timer circuit to adjust the trigger and/or holding voltages of the bipolar device or SCR to a desired level. The protection device can provide protection over a transient voltage that ranges, for example, from about 100 V to 330V.
    Type: Application
    Filed: May 11, 2011
    Publication date: November 15, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventor: Edward Coyne
  • Patent number: 8203197
    Abstract: Thermal communication of matched transistors formed in lower electrical resistance subregions of first and second active substrate regions is provided by thermally conductive members formed to extend over isolation regions between higher electrical resistance subregions of the first and second regions. In one form, thermal communication is done, with or without contacts, through insulating layers to metal layers formed over the substrate. In another form, thermal communication is done through a polysilicon layer formed over the substrate.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: June 19, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Leland Scott Swanson, Gregory E. Howard
  • Publication number: 20120074505
    Abstract: Techniques related to 3D integrated circuits formed on a single wafer are disclosed. According to one embodiment, an integrated circuit comprises a first device forming a first projection area on a wafer and a second device forming a second projection area on the wafer. The first projection area overlaps with the second projection area partially or completely. The area being shared between the two devices refers to the partial or complete overlapping of the projection areas of the two devices. In one embodiment, two or more devices in different layers of the integrated circuit or two or more devices at different depths in a same layer of the integrated circuit may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced.
    Type: Application
    Filed: December 5, 2011
    Publication date: March 29, 2012
    Inventors: Zhao Wang, Wenbo Tian, Hang Yin
  • Patent number: 8138574
    Abstract: A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Chung Hon Lam, Bipin Rajendran
  • Patent number: 8125051
    Abstract: A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: February 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Chuang, Kong-Beng Thei, Chiung-Han Yeh, Mong-Song Liang, Hou-Ju Li, Ming-Yuan Wu, Tzung-Chi Lee
  • Patent number: 8084829
    Abstract: The invention relates to a semiconductor device (10) comprising a semiconductor body (1) with a high-ohmic semi-conductor substrate (2) which is covered with a dielectric layer (3, 4) containing charges, on which dielectric layer one or more passive electronic components (20) comprising conductor tracks (20) are provided, wherein, at the location of the passive elements (20), a region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), as a result of which the conductivity of an electrically conducting channel induced in the device (10) by the charges is limited at the location of the region (5). According to the invention, the region (5) is formed by deposition and comprises a semi-insulating material. As a result, the device (10) has a very low high-frequency power loss because the inversion channel is formed in the semi-insulating region (5).
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: December 27, 2011
    Assignee: NXP B.V.
    Inventors: Wibo D. Van Noort, Petrus H. C. Magnee, Lis K. Nanver, Celine J. Detcheverry, Ramon J. Havens
  • Publication number: 20110248382
    Abstract: A method is disclosed for forming vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a width below the minimum lithographical resolution F of the lithographic technique employed. In an embodiment, the pillar array features have a dimension of approximately F/2, though this dimension could be reduced down to other values compatible with embodiments of the invention. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.
    Type: Application
    Filed: December 30, 2008
    Publication date: October 13, 2011
    Inventors: Fabio Pellizzer, Marcello Mariani, Giorgio Servalli
  • Patent number: 7952164
    Abstract: The semiconductor device includes a resistor cell that includes a diffused layer resistor, a P-well contact and an N-well contact. The diffused layer resistor is arranged on a semiconductor substrate and is formed by a diffused layer. The P-well contact surrounds an outer rim of the diffused layer resistor and is formed by another diffused layer. The N-well contact is arranged surrounding the outer rim of the P-well contact and is formed by a further diffused layer. Both the P-well and N-well contacts are partitioned into contact portions. Control electrode layer portions are arranged between neighboring contact sections of the P-well contact so the contact sections of the P-well contact and the control electrode layer portions alternate. Control electrode layer portions are arranged between neighboring contact sections of the N-well contact so that the contact sections of the N-well contact and the control electrode layer portions alternate with one another.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: May 31, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuhiro Yoshida
  • Patent number: 7855421
    Abstract: An embedded memory required for a high performance, multifunction SOC, and a method of fabricating the same are provided. The memory includes a bipolar transistor, a phase-change memory device and a MOS transistor, adjacent and electrically connected, on a substrate. The bipolar transistor includes a base composed of SiGe disposed on a collector. The phase-change memory device has a phase-change material layer which is changed from an amorphous state to a crystalline state by a current, and a heating layer composed of SiGe that contacts the lower surface of the phase-change material layer.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: December 21, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung-Yun Lee, Sangouk Ryu, Sung Min Yoon, Young Sam Park, Kyu-Jeong Choi, Nam-Yeal Lee, Byoung-Gon Yu
  • Patent number: 7847373
    Abstract: A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: December 7, 2010
    Inventors: Agostino Pirovano, Augusto Benvenuti, Fabio Pellizzer, Giorgio Servalli
  • Publication number: 20100253423
    Abstract: Methods and apparatus according to various aspects of the present invention may operate in conjunction with a resistor formed of a lightly-doped P-type region formed in a portion of a lightly-doped N-type semiconductor well extending on a lightly-doped P-type semiconductor substrate, the well being laterally delimited by a P-type wall extending down to the substrate, the portion of the well being delimited, vertically, by a heavily-doped N-type area at the limit between the well and the substrate and, horizontally, by a heavily-doped N-type wall. A diode may be placed between a terminal of the resistor and the heavily-doped N-type wall, the cathode of the diode being connected to said terminal.
    Type: Application
    Filed: July 4, 2008
    Publication date: October 7, 2010
    Inventors: Serge Pontarollo, Dominique Berger
  • Publication number: 20100193909
    Abstract: Thermal communication of matched transistors formed in lower electrical resistance subregions of first and second active substrate regions is provided by thermally conductive members formed to extend over isolation regions between higher electrical resistance subregions of the first and second regions. In one form, thermal communication is done, with or without contacts, through insulating layers to metal layers formed over the substrate. In another form, thermal communication is done through a polysilicon layer formed over the substrate.
    Type: Application
    Filed: April 12, 2010
    Publication date: August 5, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Leland Scott Swanson, Gregory E. Howard
  • Patent number: 7768004
    Abstract: In a semiconductor device including a semiconductor substrate and an electrode pad formed over the semiconductor substrate, at least one of test element is formed in a region of the semiconductor substrate beneath the electrode pad. The test element is electrically isolated from upper conductive layers outside of the region and the electrode pad.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: August 3, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hideomi Shintaku
  • Patent number: 7763921
    Abstract: The present invention provides a semiconductor device which is characterized as follows. The semiconductor device includes: an interlayer insulating film formed above a semiconductor substrate and provided with a hole above an impurity diffusion region; a conductive plug formed in the hole and electrically connected to the impurity diffusion region; a conductive oxygen barrier film formed on the conductive plug and the interlayer insulating film around the conductive plug; a conductive anti-diffusion film formed on the conductive oxygen barrier film; and a capacitor that has a lower electrode which is formed on the conductive anti-diffusion film and which exposes platinum or palladium on the upper surface, a capacitor dielectric film made of a ferroelectric material, and an upper electrode. The conductive anti-diffusion film is made of a non-oxide conductive material for preventing the diffusion of the constituent element of the capacitor dielectric film.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: July 27, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 7723817
    Abstract: The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface. This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.
    Type: Grant
    Filed: May 29, 2006
    Date of Patent: May 25, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Hiroshi Kanemaru, Naoki Kumagai, Yuichi Harada, Yoshihiro Ikura, Yoshiaki Minoya
  • Patent number: 7656002
    Abstract: The present invention relates to a microelectronic device having a bipolar epitaxial structure that provides at least one bipolar transistor element formed over at least one field effect transistor (FET) epitaxial structure that provides at least one FET element. The epitaxial structures are separated with at least one separation layer. Additional embodiments of the present invention may use different epitaxial layers, epitaxial sub-layers, metallization layers, isolation layers, layer materials, doping materials, isolation materials, implant materials, or any combination thereof.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: February 2, 2010
    Assignee: RF Micro Devices, Inc.
    Inventors: Curtis A. Barratt, Michael T. Fresina, Brian G. Moser, Dain C. Miller, Walter A. Wohlmuth
  • Patent number: 7555829
    Abstract: Electro-thermal trimming of thermally-trimmable resistors is used to trim one or more of the plurality of resistors in or associated with an analog electric circuit. The TCR of each of a subset of a plurality of electro-thermally-trimmable resistors can be trimmed independently from the resistance in order to adjust the output parameter of an analog electric circuit without changing other parameters that would be affected by a change in resistance.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: July 7, 2009
    Assignee: Microbridge Technologies Inc.
    Inventors: Oleg Grudin, Leslie M. Landsberger, Gennadiy Frolov
  • Patent number: 7554173
    Abstract: A semiconductor device accurately monitoring temperature of a semiconductor chip even in a noisy environment, while not requiring a highly accurate detection circuit. A PTC element is bonded onto an IGBT chip. Then, a constant current flows from a constant current source through the PTC element, and an output voltage of the PTC element is detected by a voltage monitor. When output voltage increases, a voltage applied to a gate electrode by a detection circuit is decreased. Since the PTC element is directly arranged on the IGBT chip, the temperature of the IGBT chip can be monitored with high accuracy. Further, since the change in output voltage of the PTC element per 1° C. is large, a highly accurate detection circuit is not necessary, thereby allowing accurate monitoring of the temperature of the IGBT chip even in a noisy environment.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: June 30, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takashi Inaguchi, Takeshi Ohi, Katsuhiko Fukuhara, Naoshi Yamada, Yoshitsugu Inaba, Takao Mitsuhashi
  • Publication number: 20090032906
    Abstract: An electro static discharge device includes a semiconductor body. The semiconductor body includes a first surface, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged on the first semiconductor region and a third semiconductor region of the first conductivity type. The third semiconductor region is isolated from the first semiconductor region by the second semiconductor region. A resistor structure is arranged in the semiconductor body and comprises at least one trench structure. The resistor structure is arranged at least in the second semiconductor region and provides a high-resistance electrical connection between a first portion and a second portion of the second semiconductor region.
    Type: Application
    Filed: July 30, 2007
    Publication date: February 5, 2009
    Applicant: Infineon Technologies Austria AG
    Inventors: Thomas Ostermann, Nicola Vannucci
  • Publication number: 20090001517
    Abstract: One embodiment relates to a circuit. In this circuit, a first semiconductor device with a first geometry is associated with a first region of a semiconductor body within a first isolation structure. A second semiconductor device with a geometry that matches the first geometry is associated with a second region of the semiconductor body within a second isolation structure. A member, which spans the semiconductor body between the first region and the second region, thermally couples the first region to the second region while retaining electrical isolation therebetween. Other circuits and methods are also disclosed.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 1, 2009
    Inventors: Leland Scott Swanson, Gregory E. Howard
  • Patent number: 7420228
    Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm?3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: September 2, 2008
    Assignee: Infineon Technologies AG
    Inventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
  • Patent number: 7350292
    Abstract: A method for affecting an impedance of a portion of an electrical circuit loop in an electrical circuit apparatus includes providing an electrical circuit apparatus having at least a portion of an electrical circuit loop including at least one of at least one trace and at least one via, and providing a layer of magnetic material disposed adjacent at least one of the trace and the via. The trace and the via are operatively connected together to provide electrical communication. Dielectric material is disposed in an operative relationship adjacent at least one of the trace and the via. The layer of magnetic material is disposed in operative relationship near at least one of the trace and the via to affect the impedance of at least one of the trace, the via and the portion of the circuit loop formed by the trace and the via.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: April 1, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Michael J. Tsuk
  • Patent number: 7319254
    Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: January 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hwa Kwak, Byung-Seo Kim
  • Patent number: 7282759
    Abstract: A memory device may include a plurality of resistance nodes. The resistance nodes may be connected serially in a NAND or AND structure, by a plurality of metal plugs. The metal plugs may have a lower resistance. A control device corresponding to each resistance node may control the resistance devices. Each control device may be connected to a bit line and a word line. The bit line may be connected to the metal plugs via a corresponding switch device.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: October 16, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-joo Kim, Yoon-dong Park
  • Patent number: 7208814
    Abstract: A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current path through the first region is determined by a portion of a doping boundary between the first region and the second region.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: April 24, 2007
    Assignee: Infineon Technologies AG
    Inventor: Stefan Pompl
  • Patent number: 7135755
    Abstract: An electric motor drive system is disclosed which includes a required number of motor driver circuits connected one to each motor armature coil. Fabricated in the form of an integrated circuit, each such motor driver circuit has a parasitic transistor unavoidably created between two neighboring transistors. The parasitic transistor would become conductive when the driver circuit output had a negative potential, adversely affecting the driver circuit operation. An additional transistor is provided in one embodiment of the invention in order to inhibit such action of the parasitic transistor. Becoming conductive when the driver circuit output goes negative, the additional transistor prevents conduction through the parasitic transistor. Another parasitic transistor is intentionally created in another embodiment for the same purpose.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: November 14, 2006
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Daiji Uehara, Hiroaki Nakamura
  • Patent number: 7135756
    Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: November 14, 2006
    Assignees: STMicroelectronics S.r.l., Ovonyx, Inc.
    Inventors: Fabio Pellizzer, Giulio Casagrande, Roberto Bez
  • Patent number: 7136299
    Abstract: A phase change memory device and, more particularly, to a phase change memory cell array suitable for the implementation of a high-density memory device. The phase change memory cell array includes a first access transistor pair and a second access transistor pair formed on a semiconductor substrate to be adjacent to each other while each of the first and second access transistor pairs having a common drain, phase change resistance elements formed on source regions of the access transistors, respectively, and a semiconductor region formed on the same plane as the common drains to electrically connect the common drains of the first and second transistor pairs. The phase change memory cell array and the memory device of are suitable for the implementation of a high-density semiconductor device, and capable of improving the reliability of a contact forming process by securing a sufficient space for the contact forming process.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: November 14, 2006
    Assignee: BeyondMicro Inc
    Inventors: Eu Gene Chu, Ju Ho Mo, Seong Taek Park, Jung Ho Kim, Hyun Yong Lim, Pyeong Han Lee, Ja Choon Jeong
  • Patent number: 7071516
    Abstract: A PMOS transistor (Q2) provided for developing a short circuit between the base and emitter of an N-type IGBT during turn-OFF includes a P diffusion region (5), a P diffusion region (6), and a conductive film (10) and a second gate electrode (15) provided via a gate oxide film (21) on a surface of an N? epitaxial layer (2) between the P diffusion regions (5 and 6). The gate oxide film (21) is formed in a thickness having a gate breakdown voltage higher than the element breakdown voltage of a typical field oxide film and the like.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: July 4, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tomohide Terashima
  • Patent number: 7026690
    Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: April 11, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 6998698
    Abstract: The present invention provides a memory cell having a variable resistor as a memory element, and also provides a memory device comprising the memory cells. The variable resistor is made of a thin-film material (for example, PCMO) or the like having a perovskite structure. So the memory cell can operate at a low voltage and can be highly integrated. The memory cell MC is formed of a combination of a current controlling device and a variable resistor. A field-effect transistor, diode or bipolar transistor is used as the current controlling device. The current controlling device is connected in series with the current path of the variable resistor so as to control a current flowing through the variable resistor.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: February 14, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Koji Inoue, Koji Hamaguchi
  • Patent number: 6984870
    Abstract: A high-speed cross-point switch is built on a preferably silicon substrate and uses bipolar transistor switching elements. Preferably, the bipolar transistors are SiGe bipolar junction transistors. Intersecting conductive input and output microstrips are preferably thinned at their intersections to reduce shunt capacitance between the coupled lines. It is also preferred that the input buffer be connected in cascode fashion with the switching transistors in order to create an amplification stage. The signal and its inverse are carried on balanced microstrip pairs in order to reduce electromagnetic field strength at the center of the balanced line pairs thereby improving isolation between two crossing balanced pairs.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: January 10, 2006
    Assignee: M/A-COM, Inc.
    Inventor: Noyan Kinayman
  • Patent number: 6967406
    Abstract: A layout method of a semiconductor integrated circuit is provided which improves characteristics of the circuit by giving hierarchical structure of interconnections regularity. A pair of emitter followers is disposed symmetrically with respect to a center line of a differential amplifier. Thus, interconnections within a circuit block and a ground wiring can be made with a single metal layer, since an area where the interconnections cross with each other is eliminated. Herewith cross talk due to the intersection of the interconnections can be resolved. Also, the interconnections between the differential amplifier and the emitter follower circuits can be made equal in length. It is possible to assign a second metal layer to interconnections between circuit blocks and a third metal layer to a power supply so that characteristics of the semiconductor integrated circuit are improved.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: November 22, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Masahiro Shiina
  • Patent number: 6965132
    Abstract: According to a disclosed embodiment, an etch stop layer is fabricated on top of a base. An amorphous layer is then formed on top of the etch stop layer. An opening is then etched in the amorphous layer and the etch stop layer. The opening is etched with an opening width substantially equal to a critical dimension. The opening with opening width substantially equal to a critical dimension is then filled with a polycrystalline emitter. The resulting polycrystalline emitter has an emitter width substantially equal to the critical dimension. Moreover, a polycrystalline emitter structure can be fabricated, in which the critical dimension, i.e. the emitter width, is precisely controlled. The result is a polycrystalline emitter structure which is substantially as small as the resolution that the photolithography process would allow.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 15, 2005
    Assignee: Newport Fab, LLC
    Inventor: Klaus F. Schuegraf