Abstract: An apparatus is described. The apparatus according to an embodiment includes a voltage dividing resistor circuit formed on a semiconductor substrate and including first and second resistors and first and second selector switches. The first and second resistors and the first and second selector switches are arranged with one of first and second layouts. The first layout is such that the first and second selector switches are placed between the first and second resistors. The second layout is such that the first and second resistors are placed between the first and second selector switches.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region. The body region and the doped isolation barrier have a common conductivity type. The body region is electrically isolated from the doped isolation barrier within the core device area. The doped isolation barrier and the isolation contact region are not electrically tied to one another such that the doped isolation barrier is biased at a different voltage level than the isolation contact region.

Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90?atan(?)) degrees.

Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90?a tan(1/3)) degrees.

Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90-atan(?)) degrees.

Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.

Abstract: Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.

Abstract: An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses 20 and 22 in the mesa 14. The size of recesses 20and 22 can be used to tune the value of the electrical resistance between contacts 16 and 18.

Abstract: An electric discharge device includes a bipolar transistor configuration comprising a base, an emitter, and a collector. At least one pinched resistor is formed in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown.

Abstract: A semiconductor device has a semiconductor substrate, a first insulating film disposed on the semiconductor substrate, and groups of resistors made of polycrystalline silicon and disposed on the first insulating film. At least some of the groups of resistors include at least one dummy resistor made of polycrystalline silicon. A second insulating film is disposed on the resistors and on the at least one dummy resistor of the resistor groups. First metal portions are disposed in respective contact holes disposed in the second insulating film for connecting respective portions of the resistors in the respective resistor groups. Second metal portions are disposed on the second insulating film and over the resistors and the at least one dummy resistor in the respective resistor groups.

Abstract: An electric discharge device includes a bipolar transistor configuration comprising a base, an emitter, and a collector. At least one pinched resistor is formed in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown.

Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

Abstract: A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current path through the first region is determined by a portion of a doping boundary between the first region and the second region.

Abstract: A phase change memory device and, more particularly, to a phase change memory cell array suitable for the implementation of a high-density memory device. The phase change memory cell array includes a first access transistor pair and a second access transistor pair formed on a semiconductor substrate to be adjacent to each other while each of the first and second access transistor pairs having a common drain, phase change resistance elements formed on source regions of the access transistors, respectively, and a semiconductor region formed on the same plane as the common drains to electrically connect the common drains of the first and second transistor pairs. The phase change memory cell array and the memory device of are suitable for the implementation of a high-density semiconductor device, and capable of improving the reliability of a contact forming process by securing a sufficient space for the contact forming process.

Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a polysilicon resistor film formed on the first insulating film; a second insulating film formed on the resistor film; a high heat conductor film consisting of a highly heat-conducting material formed on the second insulating film; and a pair of terminal wirings formed on the second insulating film and connected to the resistor film, in which a thickness T3 of the second insulating film is thinner than a thickness T2 of the resistor film.

Abstract: A resin-sealed semiconductor device is provided which allows unwanted air to be bled out steadily and readily from the space defined between the resistor of a plate-like shape and the insulating substrate in the resin sealing step. The resin-sealed semiconductor device includes a resistor of a plate-like form anchored at both ends to the upper main surface of a substrate thereof. A space is provided between the resistor and the substrate. The primary components including the resistor mounted on the substrate are sealed with a curing resin material. In particular, the resistor has an aperture provided in a portion thereof, which is opposite to the substrate and defines the space with the substrate, for communication between the space and the upper side of the resistor.

Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract: The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.

Abstract: A semiconductor device having a semiconductor resistance element is capable of suppressing a variation in characteristics of the semiconductor resistance element due to an acceptor concentration which is difficult to control, thereby stably improving the yield of a semiconductor integrated circuit using the semiconductor device. The device includes an n-type semiconductor resistance region formed in the surface of a compound semiconductor substrate, and a p-type buried region formed between the n-type semiconductor resistance region and a substrate region 21S of the compound semiconductor substrate. An acceptor of the p-type buried region is set to be higher than an acceptor concentration in the substrate region and lower than a donor concentration in the n-type semiconductor resistance region, whereby the effect of the acceptor concentration in the substrate on the semiconductor resistance region can be avoided.

Abstract: The invention relates to an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is increased through the use of coatings and films of ferromagnetic materials such as magnetic metals, alloys, and oxides. The inductor is compatible with integrated circuit manufacturing techniques and eliminates the need in many systems and circuits for large off chip inductors. A sense and measurement coil, which is fabricated on the same substrate as the inductor, provides the capability to measure the magnetic field or flux produced by the inductor. This on chip measurement capability supplies information that permits circuit engineers to design and fabricate on chip inductors to very tight tolerances.

Abstract: In a semiconductor substrate, at least one diffusion region exists between resistors on an element isolation layer, and the resistors and the diffusion regions are arranged such that all distances between the respective resistors and the diffusion regions around the corresponding resistors are equal.

Abstract: An n-well resistor device and its method of fabrication. The n-well resistor device of the present invention comprises a first n-type region and a second n-type region formed in an n-type silicon region. A gate dielectric layer formed on said n-type silicon region. A polysilicon gate formed on said gate dielectric.

Abstract: The current-limiting device 1 includes a silicon substrate 2 having surfaces opposite to each other, and two electrodes 3 deposited respectively on the opposite surfaces of the silicon substrate. The silicon substrate 2 is of a three-layered structure including an N− layer 4 of a low impurity density and an N+ layers 5 of a high impurity density formed respectively on opposite surfaces of the N− layer 4. The electrodes 3, are deposited on an outer surface of each of the N+ layers 5 remote from the N− layer 4. The constant current substantially flows in the current-limiting device 1 if the applied voltage is higher than a predetermined value.

Abstract: An electrical resistor integrated in an integrated semiconductor circuit to have a useful resistor with two spaced-apart useful resistor terminal contact regions and a useful resistor region of semiconductor material located therebetween; and an auxiliary resistor having two spaced-apart auxiliary resistor terminal contact regions and an auxiliary resistor region located therebetween.

Abstract: A ballasting resistor incorporating therein an H-shaped gate structure reduces a current therethrough by utilizing a pinching effect. The ballasting resistor is formed on a silicon-on-insulator substrate and includes a pair of N+ regions, a P− body region formed between the NM regions, and a pair of P+ nodes connected to the P− body region. The P− body region resides under the gate structure, which includes a thin dielectric layer formed on the P− body region and a conductive layer formed on the dielectric layer. The ballasting resistor is biased in such a manner that the P-N junctions are reverse-biased to pinch down the cross-sectional area of the current path provided inside the P− body region between the nodes as an applied voltage increases. The ballasting resistor has a MOS transistor-like structure; and, therefore, electrostatic discharge protection can be provided for the conventional SOI MOS circuits without requiring additional processing steps.

Abstract: A semiconductor device comprises a depletion-type NMOS transistor having a source region, a drain region connected to a power supply line, and a gate electrode connected to a ground line. An enhancement-type NMOS transistor has a source connected to the ground line, a drain connected in series with the source of the depletion-type MOS transistor between the power supply line and the ground line to define an output terminal, and a gate electrode connected directly to the output terminal.

Abstract: According to the present invention, a semiconductor device, and method for producing the same, is provided comprising: a resistance component formed in a component active region enclosed by a component separating-insulating layer on a semiconductor base; one pair of first diffusion layers containing a high concentration of impurities which are provided at both ends of the component active region; silicide layer adhering to a first diffusion layer; second diffusion layer containing a low concentration of impurities which is provided in the component active region between the pair of first diffusion layers; wherein a first diffusion layer and silicide layer comprise the terminal areas of the resistance component, and the second diffusion layer comprises a resistance member area of the resistance component.

Abstract: A film device provided with a resistance-adjustable resistive element comprises a base film, a resistive element, a conductive circuit pattern wherein the resistive element is formed on and connected to the conductive circuit pattern, and a corrective layer formed so as to partially cover the resistive element. The resistance of the resistive element is corrected by the corrective layer formed on the resistive element.

Abstract: A resistor having a diffused impurity region in a semiconductor substrate, an insulated gate surrounding and defining the resistor, and a pair of separated conductive contacts to the diffused region within the boundary of the insulated gate for applying and receiving current passing through the resistor.

Abstract: An insulated gate bipolar transistor (IGBT) element has a current detection function. An impurity-diffused area is formed at an area different from a unit cell area on the surface of the element. The current detection is performed by detecting a voltage drop due to carriers flowing in the lateral resistance of the impurity-diffused area. For example, in an n-channel IGBT, electrons are injected from a source electrode through an n-type source layer and the channel to an n-type drain layer at the cell when the unit cell is in an on-state. The pn junction at the drain side is forwardly biased to inject holes from the p-type drain layer to the n-type drain layer. At this time, the electrons also flow to the lower side of the p-type impurity-diffused area provided as the detection portion. Thus, the hole injection occurs at this portion. These surplus holes are discharged through the p-type layer of the detection portion to the source electrode.

Abstract: The invention relates to a thermistor, primarily intended for temperature measurement. The thermistor comprises at least two thermistor plates (14-17) on a carrier (10), adjacent to each other and connected in series. The plates are separated from each other by a preferably elongated gap (18) and the upper surfaces of said plates are largely covered by upper electrode surfaces (24-26). The thermistor plates (14-17) are arranged within a limited area of the carrier (10) so that the maximum aggregate area of the thermistor plates (14-17) is constant, whereas the size of each individual thermistor surface is variable by displacement of the position of the gap(s) (18) within the said limited area of the carrier (10), for adjustment of the total resistance of the thermistor to different values. The invention also relates to a procedure for manufacturing a thermistor.

Abstract: A monolithic integrated power transistor chip includes a plurality of transistor cells arranged in two opposite and mutually spaced rows. Each cell has emitter- and collector connection spots arranged side-by-side and connected to corresponding branch conductors directed by rows of connection points extending along opposite edges on the upper surface of the chip.