Abstract: A semiconductor device such as a Schottky diode is provided which includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.

Abstract: A semiconductor device has a semiconductor substrate, a field insulating film disposed on a surface of the semiconductor substrate, a base insulating film disposed on a surface of the field insulating film, and a resistor disposed on the base insulating film. The resistor is formed of a polycrystalline silicon film and has a resistance region and electrode lead-out regions disposed at both ends of the resistance region. A portion of the base insulating film below the resistance region projects with respect to portions of the base insulating film below the electrode lead-out regions so that a height difference occurs therebetween. The resistance region has a thickness thinner than that of each of the electrode lead-out regions.

Abstract: The invention relates to a semiconductor device (10) comprising a semiconductor body (1) with a high-ohmic semi-conductor substrate (2) which is covered with a dielectric layer (3, 4) containing charges, on which dielectric layer one or more passive electronic components (20) comprising conductor tracks (20) are provided, wherein, at the location of the passive elements (20), a region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), as a result of which the conductivity of an electrically conducting channel induced in the device (10) by the charges is limited at the location of the region (5). According to the invention, the region (5) is formed by deposition and comprises a semi-insulating material. As a result, the device (10) has a very low high-frequency power loss because the inversion channel is formed in the semi-insulating region (5).

Abstract: The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions is performed by simply modifying the standard mask of the MOS process using a logic operation layer with no extra mask required.

Abstract: In a method of manufacturing a semiconductor device, a first oxide film is formed in a convex shape on a field insulating film, a polycrystalline silicon film is formed on the first oxide film, and impurities are introduced into the polycrystalline silicon film. The polycrystalline silicon film into which the impurity is introduced is patterned so that a portion above the convex-shaped first oxide film becomes a resistance region of the resistor. A second oxide film is then formed on the patterned polycrystalline silicon film followed by the formation of a third oxide film on the second oxide film. The third oxide film and parts of the second oxide film and the polycrystalline silicon film are then removed to form a planarized surface including surface portions of the second oxide film and the polycrystalline silicon film.

Abstract: A semiconductor memory device according to an embodiment of the present invention includes a resistance element which is constructed with a first conductor which extends in a first direction and is connected to a first contact; a second conductor which extends in said first direction and is connected to a second contact; and a first insulation film which exists between said first conductor and said second conductor, said first insulation film also having an opening in which a third conductor which connects said first conductor and said second conductor is arranged.

Abstract: The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

Abstract: A semiconductor device may include a resistance pattern including a resistance material on a substrate. The resistance pattern may include first and second spaced apart base elements, a bridge element, and first, second, third, and fourth extension elements. The first and second base elements may be substantially parallel, and the bridge element may be connected between respective center portions of the first and second spaced apart base elements. The first and second extension elements may be connected to opposite ends of the first base element and may extend toward the second base element, and the third and fourth extension elements may be connected to opposite ends of the second base element and may extend toward the first base element. Related methods are also discussed.

Abstract: A semiconductor device has a semiconductor substrate, a first insulating film disposed on the semiconductor substrate, and groups of resistors made of polycrystalline silicon and disposed on the first insulating film. At least some of the groups of resistors include at least one dummy resistor made of polycrystalline silicon. A second insulating film is disposed on the resistors and on the at least one dummy resistor of the resistor groups. First metal portions are disposed in respective contact holes disposed in the second insulating film for connecting respective portions of the resistors in the respective resistor groups. Second metal portions are disposed on the second insulating film and over the resistors and the at least one dummy resistor in the respective resistor groups.

Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

Abstract: A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current path through the first region is determined by a portion of a doping boundary between the first region and the second region.

Abstract: A phase change memory device and, more particularly, to a phase change memory cell array suitable for the implementation of a high-density memory device. The phase change memory cell array includes a first access transistor pair and a second access transistor pair formed on a semiconductor substrate to be adjacent to each other while each of the first and second access transistor pairs having a common drain, phase change resistance elements formed on source regions of the access transistors, respectively, and a semiconductor region formed on the same plane as the common drains to electrically connect the common drains of the first and second transistor pairs. The phase change memory cell array and the memory device of are suitable for the implementation of a high-density semiconductor device, and capable of improving the reliability of a contact forming process by securing a sufficient space for the contact forming process.

Abstract: A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first side of the first heating element is adjacent to a first portion of the insulator layer. The first heating element is adapted to be selectively activated to generate thermal energy to heat the first portion of the insulator layer and anneal a trapped electrical charge from the first portion of the insulator layer.

Abstract: The manufacturing process comprises the steps of growing epitaxially a first layer from a semiconductor material substrate, forming in the first layer a first and a second buried region spaced from one another and having conductivity of the type opposite that of the first layer; growing epitaxially on the first layer a second layer of semiconductor material having the same type of conductivity as the first layer; forming in the second layer a trench extending in depth beyond the buried regions, arranged between the buried regions, and having, in plan view, a frame shape; forming an oxide layer covering the lateral walls and the base wall of the trench; and filling the remaining part of the trench with an isolating material.

Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range ?40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.

Abstract: A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.

Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a polysilicon resistor film formed on the first insulating film; a second insulating film formed on the resistor film; a high heat conductor film consisting of a highly heat-conducting material formed on the second insulating film; and a pair of terminal wirings formed on the second insulating film and connected to the resistor film, in which a thickness T3 of the second insulating film is thinner than a thickness T2 of the resistor film.

Abstract: Isolated metal structures (110), (140) are formed adjacent to terminated metal lines (100), (130) that are connect by a via (120). The isolated structures (110), (140) act to suppress the stress created in the terminated metal lines (100), (130) during thermal cycling.

Abstract: A method of forming an isolating wall in a semiconductor substrate of a first conductivity type, including the steps of boring in the substrate separate recesses according to the desired isolating wall contour; filling the recesses with a material containing a dopant of the second conductivity type; and performing an anneal step so that regions of the second conductivity type diffused from neighboring recesses join. A first series of recesses is formed from the upper surface and a second series of recesses is formed from the lower surface. The recesses have a substantially rectangular section, the large dimension of which is perpendicular to the alignment of the recesses and a depth smaller than or equal to the half-thickness of the substrate.

Abstract: A SOI semiconductor device comprises a resistor body which is formed of a top semiconductor layer in a SOI substrate having an embedded dielectric film and the top semiconductor layer formed on the embedded dielectric film and which is dielectrically isolated by an insulating film, wherein a resistance value of the resistor body is set to be a predetermined value by the concentration of impurities contained in the top semiconductor layer and by the dimension of the resistor body.

Abstract: Methods and apparatus are provided for plasma doping and ion implantation in an integrated processing system. The apparatus includes a process chamber, a beamline ion implant module for generating an ion beam and directing the ion beam into the process chamber, a plasma doping module including a plasma doping chamber that is accessible from the process chamber, and a wafer positioner. The positioner positions a semiconductor wafer in the path of the ion beam in a beamline implant mode and positions the semiconductor wafer in the plasma doping chamber in a plasma doping mode.

Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range −40C to +85C. Furthermore, the temperature variation at room temperature (˜25C) can be reduced to nearly zero.

Abstract: The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.

Abstract: A semiconductor device having a semiconductor resistance element is capable of suppressing a variation in characteristics of the semiconductor resistance element due to an acceptor concentration which is difficult to control, thereby stably improving the yield of a semiconductor integrated circuit using the semiconductor device. The device includes an n-type semiconductor resistance region formed in the surface of a compound semiconductor substrate, and a p-type buried region formed between the n-type semiconductor resistance region and a substrate region 21S of the compound semiconductor substrate. An acceptor of the p-type buried region is set to be higher than an acceptor concentration in the substrate region and lower than a donor concentration in the n-type semiconductor resistance region, whereby the effect of the acceptor concentration in the substrate on the semiconductor resistance region can be avoided.

Abstract: A semiconductor integrated circuit device comprises an active device and a resistance element formed monolithically on a common substrate wherein the resistance element includes a dummy pattern having a layered structure identical with a layered structure of the active device, and first and second electrodes are provided inside a mesa structure provided for the resistance element with a separation from a sidewall of the mesa structure, the first and second electrodes being formed in correspondence to openings formed in the dummy pattern.

Abstract: A resistor layer (5) is formed on an isolation insulating film (4) selectively formed in a major surface (1S) of a semiconductor substrate (1). An interlayer insulation film (7) covering the resistor layer (5) has first and second plugs (9, 19) buried therein in the form of buried interconnections. The first and second plugs (9, 19) provide connection not only between an end portion of the resistor layer (5) and first and second interconnection layers (8, 18) but also between the end portion of the resistor layer (5) and the major surface (1S) of the semiconductor substrate (1).

Abstract: The present invention is disclosed a microchannel array structure embedded in a silicon substrate and a fabrication method thereof. The microchannel array structure of the present invention is formed deep inside the substrate and has high-density microscopic micro-channels. Besides, going through surface micromachining, physical and chemical properties of the silicon substrate are hardly influenced by the fabrication procedures. With microchannels buried in the substrate, the top of a microchannel array structure becomes flat, minimizing the effect of step height. That way, additional devices such as passive components, micro sensors, micro actuators and electronic devices can be easily integrated onto the microchannel array structure.

Abstract: A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Abstract: A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract: According to the present invention, a semiconductor device, and method for producing the same, is provided comprising: a resistance component formed in a component active region enclosed by a component separating-insulating layer on a semiconductor base; one pair of first diffusion layers containing a high concentration of impurities which are provided at both ends of the component active region; silicide layer adhering to a first diffusion layer; second diffusion layer containing a low concentration of impurities which is provided in the component active region between the pair of first diffusion layers; wherein a first diffusion layer and silicide layer comprise the terminal areas of the resistance component, and the second diffusion layer comprises a resistance member area of the resistance component.

Abstract: A film device provided with a resistance-adjustable resistive element comprises a base film, a resistive element, a conductive circuit pattern wherein the resistive element is formed on and connected to the conductive circuit pattern, and a corrective layer formed so as to partially cover the resistive element. The resistance of the resistive element is corrected by the corrective layer formed on the resistive element.

Abstract: An analog circuit starter current source device with automatic shut-down capability. The device includes a semiconductor substrate (typically p-type) with a deep well region (typically n-type) below its surface, a first surface well region (typically n-type) on the surface of the substrate that circumscribes the deep well region, and a narrow channel region (typically p-type) separating the deep well region from the first surface well region. The device also includes a first contact region for connecting the first surface well region to the analog circuit, and a second contact region for connecting a substrate region above the deep well to the analog circuit. The configuration provides a variable-width vertical resistor current path capable of starting an analog circuit and then being automatically shut-down by application of a potential to the first contact region sufficient to produce a depletion region that pinches-off the narrow channel region.

Abstract: A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.

Abstract: A method and resulting antifuse structure in an integrated circuit include a first metal interconnection layer on a first insulating layer over the substrate of the integrated circuit, a second insulating layer over the first metal interconnection layer. The second insulating layer has a via therein and a programming layer is located in the via. Such programming layer includes a first region on the first metal interconnection layer which is removed from sides of the second insulating layer in the via, and a second region on the sides of the second insulating layer via. The first region has substantially a first thickness, the second region has substantially a second thickness which is greater than the first thickness. Upon programming the antifuse structure, a conducting link forms in the first region of the programming layer.

Abstract: A thin film resistor on a semiconductor device may be laser trimmed while reducing the influence of film thickness of a passivation film formed on the thin film resistor. An underlying oxide film consisting of a BPSG film and a silicon oxide film is formed on an Si substrate. A silicon oxide film and a silicon nitride film are formed on the underlying film as a passivation film, and a silicon oxide film is formed on this assembly. The silicon oxide film contributes to controlling a variation of the laser energy absorption rate of a thin film resistor due to an uneven thickness of the silicon nitride film. Thus, it is possible to stabilize adjustment of the resistance value of the thin film resistor with a laser.

Abstract: An operational amplifier, of a type which comprises a differential cell transconductor input stage (2) incorporating a current mirror (5) provided with a pair of degenerative resistors (R9,R10) and a gain stage (7), driven directly by a transistor (Q12) of said mirror (5), has each degenerative resistor (R9,R10) formed within an epitaxial well wherewith a parasitic diode (D1,D2) is associated. Each diode (D1,D2) is connected in parallel with its corresponding resistor (R9,R10) to prevent the transistor (Q12) which drives the gain stage (7) from becoming saturated.

Abstract: Generally, and in one form of the invention a semiconductor device is presented comprising: a transistor comprising an emitter finger and a base finger; and a ballast impedance connected to the base finger. Other devices and methods are also disclosed.