With Impurity Other Than Hydrogen To Passivate Dangling Bonds (e.g., Halide) Patents (Class 257/56)
  • Patent number: 9502048
    Abstract: The present technology provides adaptive noise reduction of an acoustic signal using a sophisticated level of control to balance the tradeoff between speech loss distortion and noise reduction. The energy level of a noise component in a sub-band signal of the acoustic signal is reduced based on an estimated signal-to-noise ratio of the sub-band signal, and further on an estimated threshold level of speech distortion in the sub-band signal. In various embodiments, the energy level of the noise component in the sub-band signal may be reduced to no less than a residual noise target level. Such a target level may be defined as a level at which the noise component ceases to be perceptible.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: November 22, 2016
    Assignee: Knowles Electronics, LLC
    Inventors: Mark Every, Carlos Avendano
  • Patent number: 8878176
    Abstract: A thin-film transistor with a fluorinated channel and fluorinated source and drain regions and methods of fabrication are provided. The thin-film transistor includes: a substrate; a semiconductor active layer of fluorine-doped metal-oxide formed on the substrate; fluorine-doped source and drain regions disposed adjacent to the semiconductor active layer; a gate electrode disposed over the semiconductor active layer, configured to induce a continuous conduction channel between the source and drain regions; and a gate dielectric material separating the gate electrode and the channel.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: November 4, 2014
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Man Wong, Hoi Sing Kwok, Zhi Ye
  • Patent number: 8866245
    Abstract: We introduce a new technology for Manufactureable, High Power Density, High Volume Utilization Nuclear Batteries. Betavoltaic batteries are an excellent choice for battery applications which require long life, high power density, or the ability to operate in harsh environments. In order to optimize the performance of betavoltaic batteries for these applications or any other application, it is desirable to maximize the efficiency of beta particle energy conversion into power, while at the same time increasing the power density of an overall device. Various devices and methods to solve the current industry problems and limitations are presented here.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: October 21, 2014
    Assignee: Widetronix, Inc.
    Inventors: Michael Spencer, Mvs Chandrashekhar, Chris Thomas
  • Patent number: 8664115
    Abstract: A passivation layer is formed on inlaid Cu for protection against oxidation and removal during subsequent removal of an overlying metal hardmask. Embodiments include treating an exposed upper surface of inlaid Cu with hydrofluoric acid and a copper complexing agent, such as benzene triazole, to form a passivation monolayer of a copper complex, etching to remove the metal hardmask, removing the passivation layer by heating to at least 300° C., and forming a barrier layer on the exposed upper surface of the inlaid Cu.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 4, 2014
    Inventors: Christin Bartsch, Susanne Leppack
  • Patent number: 8624246
    Abstract: A display device and a method of manufacturing the same. In one embodiment, a display device includes a substrate having a pixel region, a transistor region and a capacitor region, a transistor arranged within the transistor region of the substrate and a capacitor arranged within the capacitor region of the substrate, wherein the capacitor includes a lower electrode arranged on the substrate, a gate insulating layer arranged on the lower electrode and an upper electrode arranged on the gate insulating layer and overlapping the lower electrode, the upper electrode includes a first conductive layer and a second conductive layer arranged on the first conductive layer, wherein the first conductive layer is opaque.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Chun-Gi You
  • Patent number: 8604484
    Abstract: A display device includes a switching device, a first pixel electrode, a dielectric layer and a second pixel electrode. The switching device is provided on the lower substrate. The organic layer pattern is disposed on the lower substrate. The organic layer pattern includes a plurality of stepped portions in a pixel region. The first pixel electrode is disposed on the organic layer pattern in the pixel region. The dielectric layer is disposed on the first pixel electrode. A plurality of the second pixel electrodes is disposed on the dielectric layer. The second pixel electrodes are partially superimposed over the first pixel electrode. Non-uniform vertical fields may be minimized by the morphology of the first pixel electrode, so that the display device may have excellent brightness and transmittance.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: December 10, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hyun-Chul Kim
  • Patent number: 8378348
    Abstract: A semiconductor device 101 includes: a substrate 1; an active layer 4 provided on the substrate 1 and including a channel region 4c, and a first region 4a and a second region 4b that are respectively located on opposite sides of the channel region 4c; first and second contact layers 6a and 6b respectively in contact with the first and second regions 4a and 4b of the active layer 4; a first electrode 7 electrically coupled to the first region 4a via the first contact layer 6a; a second electrode 8 electrically coupled to the second region 4b via the second contact layer 6b; and a gate electrode 2 provided such that a gate insulating layer 3 is interposed between the gate electrode 2 and the active layer 4, the gate electrode 2 being configured to control a conductivity of the channel region 4c. The active layer 4 contains silicon. The semiconductor device further includes an oxygen-containing silicon layer 5 between the active layer 4 and the first and second contact layers 6a, 6b.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: February 19, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuichi Saito, Masao Moriguchi, Akihiko Kohno
  • Patent number: 8378352
    Abstract: An organic light-emitting display device and a method of manufacturing the organic light-emitting display device are disclosed. The organic light-emitting display device includes a bottom capacitor electrode that is formed over the same plane as an active layer of a thin film transistor and includes a semiconductor doped with ion impurities, a pixel electrode, and a top capacitor electrode formed over the same plane as a gate electrode, wherein a contact hole entirely exposing the pixel electrode and the top capacitor electrode is formed.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: February 19, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yul-Kyu Lee, Chuy-Gi You, Sun Park, Jong-Hyun Park, Dae-Woo Kim
  • Patent number: 8329500
    Abstract: Provided is a method of manufacturing a photovoltaic device using a Joule heating-induced crystallization method. The method includes: forming a first conductive pattern on a substrate; forming a photoelectric conversion layer on the substrate having the first conductive pattern; and crystallizing at least part of the photoelectric conversion layer by applying an electric field to the photoelectric conversion layer, wherein the photoelectric conversion layer includes a first amorphous semiconductor layer containing first impurities, a second intrinsic, amorphous semiconductor layer, and a third amorphous semiconductor layer containing second impurities.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: December 11, 2012
    Assignees: Samsung Display Co., Ltd., Samsung SDI Co., Ltd.
    Inventors: Byoung-Kyu Lee, Se-Jin Chung, Byoung-June Kim, Czang-Ho Lee, Myung-Hun Shin, Min-Seok Oh, Ku-Hyun Kang, Yuk-Hyun Nam, Seung-Jae Jung, Min Park, Mi-Hwa Lim, Joon-Young Seo
  • Patent number: 8227872
    Abstract: Example embodiments relate to a heterojunction diode, a method of manufacturing the heterojunction diode, and an electronic device including the heterojunction diode. The heterojunction diode may include a first conductive type non-oxide layer and a second conductive type oxide layer bonded to the non-oxide layer. The non-oxide layer may be a Si layer. The Si layer may be a p++ Si layer or an n++ Si layer. A difference in work functions of the non-oxide layer and the oxide layer may be about 0.8-1.2 eV. Accordingly, when a forward voltage is applied to the heterojunction diode, rectification may occur. The heterojunction diode may be applied to an electronic device, e.g., a memory device.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-hwan Kim, Young-bae Kim, Seung-ryul Lee, Young-soo Park, Chang-jung Kim, Bo-soo Kang
  • Patent number: 8212252
    Abstract: An object of the present invention is to provide a new light-emitting device with the use of an amorphous oxide. The light-emitting device has a light-emitting layer existing between first and second electrodes and a field effect transistor, of which the active layer is an amorphous.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: July 3, 2012
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Tohru Den, Tatsuya Iwasaki, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 8168974
    Abstract: A novel field-effect transistor is provided which employs an amorphous oxide. In an embodiment of the present invention, the transistor comprises an amorphous oxide layer containing electron carrier at a concentration less than 1×10?18/cm3, and the gate-insulating layer is comprised of a first layer being in contact with the amorphous oxide and a second layer different from the first layer.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: May 1, 2012
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Masafumi Sano, Katsumi Nakagawa, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 8143620
    Abstract: Systems and methods for adaptively classifying audio sources are provided. In exemplary embodiments, at least one acoustic signal is received. One or more acoustic features based on the at least one acoustic signal are derived. A global summary of acoustic features based, at least in part, on the derived one or more acoustic features is determined. Further, an instantaneous global classification based on a global running estimate and the global summary of acoustic features is determined. The global running estimates may be updated and an instantaneous local classification based, at least in part, on the one or more acoustic features may be derived. One or more spectral energy classifications based, at least in part, on the instantaneous local classification and the one or more acoustic features may be determined. In some embodiments, the spectral energy classification is provided to a noise suppression system.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: March 27, 2012
    Assignee: Audience, Inc.
    Inventors: Stephen Malinowski, Carlos Avendano
  • Patent number: 7875529
    Abstract: Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to the second wafer to form at least one CMOS device. Another embodiment includes a number of DRAM capacitors formed on a first wafer and support circuitry associated with the DRAM capacitors formed on a second wafer, with the first wafer being bonded and electrically coupled to the second wafer to form a number of DRAM cells. Another embodiment includes a first wafer having a number of vertical transistors coupled to a data line and a second wafer having amplifier circuitry associated with the number of vertical transistors, with the first wafer being bonded and electrically coupled to the second wafer.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: January 25, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Paul A. Farrar, Arup Bhattacharyya, Hussein I. Hanafi, Warren M. Farnworth
  • Patent number: 7872259
    Abstract: An object of the present invention is to provide a new light-emitting device with the use of an amorphous oxide. The light-emitting device has a light-emitting layer existing between first and second electrodes and a field effect transistor, of which the active layer is an amorphous.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: January 18, 2011
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Tohru Den, Tatsuya Iwasaki, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 7868325
    Abstract: Semiconductor wafer of monocrystalline silicon contain fluorine, the fluorine concentration being 1·1010 to 1·1016 atoms/cm3, and is free of agglomerated intrinsic point defects whose diameter is greater than or equal to a critical diameter. The semiconductor wafers are produced by providing a melt of silicon which is doped with fluorine, and crystallizing the melt to form a single crystal which contains fluorine within the range of 1·1010 to 1·1016 atoms/cm3, at a growth rate at which agglomerated intrinsic point defects having a critical diameter or larger would arise if fluorine were not present or present in too small an amount, and separating semiconductor wafers from the single crystal.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: January 11, 2011
    Assignee: Siltronic AG
    Inventor: Wilfried von Ammon
  • Patent number: 7868326
    Abstract: A novel field-effect transistor is provided which employs an amorphous oxide. In an embodiment of the present invention, the transistor comprises an amorphous oxide layer containing electron carrier at a concentration less than 1×10?18/cm3, and the gate-insulating layer is comprised of a first layer being in contact with the amorphous oxide and a second layer different from the first layer.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: January 11, 2011
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Masafumi Sano, Katsumi Nakagawa, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 7863518
    Abstract: A photovoltaic device capable of improving output characteristics is provided. This photovoltaic device comprises a crystalline semiconductor member, a substantially intrinsic first amorphous semiconductor layer formed on the front surface of the crystalline semiconductor member and a first conductivity type second amorphous semiconductor layer formed on the front surface of the first amorphous semiconductor layer, and has a hydrogen concentration peak in the first amorphous semiconductor layer. Thus, the quantity of hydrogen atoms in the first amorphous semiconductor layer is so increased that the hydrogen atoms increased in quantity can be bonded to dangling bonds of silicon atoms forming defects in the first amorphous semiconductor layer for inactivating the dangling bonds.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: January 4, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Akira Terakawa, Toshio Asaumi
  • Patent number: 7863611
    Abstract: Semiconductor devices and circuits with use of transparent oxide film are provided. The semiconductor device having a P-type region and an N-type region, wherein amorphous oxides with electron carrier concentration less than 1018/cm3 is used for the N-type region.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: January 4, 2011
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Katsumi Abe, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 7693360
    Abstract: On the back surface of a transparent plate having a light extracting part for outputting lights to the outside, an electrode for wiring, and an electrode for an electromagnetic shield, an optical device is flip-chip mounted right under the light extracting part, an a driver IC is flip-chip mounted at a desired position with metal bumps. When currents driving the optical device flow from the driver IC according to an electric logical signal from the outside, an optical signal is emitted from the optical device, and is output to the outside through the light extracting part. The light extracting part may be provided with a light coupling material or an optical axis converter.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: April 6, 2010
    Assignee: NEC Corporation
    Inventors: Takanori Shimizu, Takara Sugimoto, Jun-ichi Sasaki, Kazuhiko Kurata
  • Patent number: 7525131
    Abstract: Disclosed is a photoelectric surface including: a first group III nitride semiconductor layer that produces photoelectrons according to incidence of ultraviolet rays; and a second group III nitride semiconductor layer provided adjacent to the first group III nitride semiconductor layer and made of a thin-film crystal having c-axis orientation in a thickness direction, the second group III nitride semiconductor layer having an Al composition higher than that of the first group III nitride semiconductor layer.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: April 28, 2009
    Assignees: National University Corporation Shizuoka University, Hamamatsu Photonics K.K.
    Inventors: Masatomo Sumiya, Shunro Fuke, Tokuaki Nihashi, Minoru Hagino
  • Patent number: 7492988
    Abstract: Planar AWG circuits and systems are disclosed that use air trench bends to increase planar circuit compactness.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: February 17, 2009
    Inventors: Gregory P. Nordin, Yongbin Lin, Seunghyun Kim
  • Patent number: 7352044
    Abstract: A solar battery 10 comprises a metal electrode layer 12, a pin junction 100, and a transparent electrode layer 16 which are successively laminated on a substrate 11 such as a silicon substrate. The pin junction 100 comprises an n-layer 13, an i-layer 14, and a p-layer 15 which are laminated in succession. The i-layer 14 is formed by amorphous iron silicide (FexSiy:H) containing hydrogen atoms. In the i-layer 14, at least a part of the hydrogen atoms contained therein terminate dangling bonds of silicon atoms and/or iron atoms, so that a number of trap levels which may occur in an amorphous iron silicide film can be eliminated, whereby the i-layer 14 exhibits a characteristic as an intrinsic semiconductor layer.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: April 1, 2008
    Assignees: TDK Corporation, Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroshi Yamada, Hisao Morooka, Kazuo Nishi
  • Patent number: 7335950
    Abstract: To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region 145 having a P-type behavior more potential than that of a drain region 146 is arranged between a channel forming region 134 and the drain region 146 in the P-channel type thin film transistor whereby the P-channel type thin film transistor having the low OFF characteristic can be provided and a low concentration impurity region 136 is arranged between a channel forming region 137 and a drain region 127 in the N-channel type thin film transistor whereby the N-channel type thin film transistor having the low OFF characteristic and where deterioration is restrained can be provided.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: February 26, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Satoshi Teramoto
  • Patent number: 7279370
    Abstract: A thin film transistor array substrate device includes a gate line formed on a substrate, a data line crossing the gate line with a gate insulating pattern position therebetween, a thin film transistor at a crossing of the gate line and the data line, a pixel electrode formed at a pixel region defined by the crossing of the gate line and the data line and connected to the thin film transistor, a gate pad part having a lower gate pad electrode connected to the gate line and an upper gate pad electrode connected to the lower gate pad electrode, a data pad part having a lower data pad electrode connected to the date line and an upper data pad electrode connected to the lower data pad electrode, and a passivation film pattern formed at a region besides the region including the pixel electrode, the upper data pad electrode, and the upper gate pad electrode, wherein the pixel electrode is formed on the gate insulating pattern of the pixel region exposed by the passivation film pattern.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: October 9, 2007
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Byoung Ho Lim, Hyun Sik Seo, Heung Lyul Cho, Hong Sik Kim
  • Patent number: 7214971
    Abstract: A semiconductor light-receiving device has a substrate including upper, middle and lower regions in its front side. A p-type layer on the lower region has a top surface including a portion on a level with the middle region. An electrode covers at least part of the boundary between the portion of the p-type layer and the middle region. An n-type layer on the p-type layer has a top surface including a portion on a level with the upper region. Another electrode covers at least part of the boundary between the portion of the n-type layer and the upper region.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: May 8, 2007
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Minoru Niigaki, Kazutoshi Nakajima
  • Patent number: 7202511
    Abstract: Electromagnetic energy is detected with high efficiency in the spectral range having wavelengths of about 1–2 microns by coupling an absorber layer having high quantum efficiency in the spectral range having wavelengths of about 1–2 microns to an intrinsic semiconducting blocking region of an impurity band semiconducting device included in a solid state photon detector.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: April 10, 2007
    Assignee: DRS Sensors & Targeting Systems, Inc.
    Inventors: Maryn G. Stapelbroek, Henry H. Hogue, Arvind I. D'Souza
  • Patent number: 7145175
    Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: December 5, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Tomoaki Atsumi, Atsuo Isobe
  • Patent number: 7115925
    Abstract: An active pixel includes a a photosensitive element formed in a semiconductor substrate. A transfer transistor is formed between the photosensitive element and a floating diffusion and selectively operative to transfer a signal from the photosensitive element to the floating diffusion. The floating diffusion is formed from an n-type implant with a dosage in the range of 5e13 to 5e14 ions/cm2. Finally, an amplification transistor is controlled by the floating diffusion.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: October 3, 2006
    Assignee: OmniVision Technologies, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 7112545
    Abstract: The surface of a semiconductor material, e.g., gallium arsenide, is passivated by irradiating the surface with ultra-short laser pulses, until a stable passive surface is achieved. The passive surface so prepared is devoid of a superficial oxide layer.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: September 26, 2006
    Assignee: The Board of Trustees of the University of Arkansas
    Inventors: Tarak A. Railkar, Ajay P. Malshe, William D. Brown
  • Patent number: 7102185
    Abstract: An interline transfer type image sensing device that can be operated at high speed and with low image smear is described. The device incorporates a refractory metal layer which is used for both a light shield over the vertical charge transfer region and as a wiring layer for low resistance strapping of poly crystalline silicon (polysilicon) gate electrodes for the vertical charge transfer region. Plugs provided by a separate metallization layer connect the refractory light shield to the polysilicon gate electrode. These plugs allow high temperature processing after refractory light shield patterning for improved sensor performance without degradation of the polysilicon gate electrode or the refractory lightshield layer.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: September 5, 2006
    Assignee: Eastman Kodak Company
    Inventors: David N. Nichols, David L. Losee, Christopher Parks
  • Patent number: 7038238
    Abstract: A semiconductor device including a conductive substrate or a first conductive layer formed on the substrate, a non-single-crystal semiconductor layer member is disposed on the conductive substrate or the conductive layer, the non-single-crystal semiconductor layer member having at least one intrinsic, non-single-crystal semiconductor layer, and a second conductive layer disposed on the non-single-crystal semiconductor layer. The intrinsic non-single-crystal semiconductor layer contains sodium and oxygen in very low concentrations where each concentration is 5×1018 atoms/cm3 or less.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: May 2, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6984847
    Abstract: An organic electroluminescent device includes first and second substrates facing and spaced apart from each other; a gate line on an inner surface of the first substrate; a semiconductor layer over the gate line, the semiconductor layer overlying a surface of the first substrate; a data line crossing the gate line; a data ohmic contact layer under the data line, the data ohmic contact layer having the same shape as the data line; a power line parallel to, or substantially parallel to, and spaced apart from the data line, the power line including the same material as the gate line; a switching thin film transistor connected to the gate line and the data line, the switching thin film transistor using the semiconductor layer as a switching active layer; a driving thin film transistor connected to the switching thin film transistor and the power line, the driving thin film transistor using the semiconductor layer as a driving active layer; a connection pattern connected to the driving thin film transistor, the co
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: January 10, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Jae-Yong Park, Kwang-Jo Hwang
  • Patent number: 6930326
    Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: August 16, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Tomoaki Atsumi, Atsuo Isobe
  • Patent number: 6831333
    Abstract: To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region 145 having a P-type behavior more potential than that of a drain region 146 is arranged between a channel forming region 134 and the drain region 146 in the P-channel type thin film transistor whereby the P-channel type thin film transistor having the low OFF characteristic can be provided and a low concentration impurity region 136 is arranged between a channel forming region 137 and a drain region 127 in the N-channel type thin film transistor whereby the N-channel type thin film transistor having the low OFF characteristic and where deterioration is restrained can be provided.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: December 14, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Satoshi Teramoto
  • Patent number: 6815805
    Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: November 9, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Ronald A. Weimer
  • Publication number: 20040144977
    Abstract: A semiconductor wafer is made of a silicon substrate wafer and an epitaxial silicon layer deposited thereon. The substrate wafer has a specific resistance of 0.1 to 50 &OHgr;cm, an oxygen concentration of less than 7.5*1017 atcm−3 and a nitrogen concentration of 1*1013 to 5*1015 atcm−3. The epitaxial layer is 0.2 to 1.0 &mgr;m thick and has a surface on which fewer than 30 LLS (localized light scattering) defects which are greater in size than 0.085 &mgr;m can be detected. A method for producing the semiconductor wafer has a sequence of steps for providing the substrate wafer with the aforementioned features; heating the substrate wafer in a deposition reactor to a deposition temperature of at least 1120° C.; and depositing the epitaxial layer thereon with a thickness of 0.2 to 1.0 &mgr;m, immediately after the deposition temperature has been reached.
    Type: Application
    Filed: January 13, 2004
    Publication date: July 29, 2004
    Applicant: WACKER SILTRONIC GESELLSCHAFT FUR HALBLEITERMATERIALIEN AG
    Inventors: Reinhard Schauer, Markus Blietz, Wilfried von Ammon, Rudiger Schmolke
  • Patent number: 6734499
    Abstract: An insulated gate field effect transistor comprises a non-single-crystalline semiconductor layer formed on a substrate, a gate electrode is formed on a portion of the surface of said semiconductor layer, and a gate insulating film is disposed between said gate electrode and said semiconductor layer. A non-single-crystalline channel region is defined within said semiconductor layer just below said gate electrode. A source region and a drain region are transformed from and defined within said semiconductor layer immediately adjacent to said channel region in an opposed relation, said source and drain regions being crystallized to a higher degree than that of said channel region by selectively irradiating portions of said semiconductor layer using said gate electrode as a mask.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: May 11, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6716664
    Abstract: A functional device free from cracking and having excellent functional characteristics, and a method of manufacturing the same are disclosed. A low-temperature softening layer (12) and a heat-resistant layer (13) are formed in this order on a substrate (11) made of an organic material such as polyethylene terephthalate, and a functional layer (14) made of polysilicon is formed thereon. The functional layer (14) is formed by crystallizing an amorphous silicon layer, which is a precursor layer, with laser beam irradiation. When a laser beam is applied, heat is transmitted to the substrate (11) and the substrate (11) tends to expand. However, a stress caused by a difference in a thermal expansion coefficient between the substrate (11) and the functional layer (14) is absorbed by the low-temperature softening layer (12), so that no cracks and peeling occurs in the functional layer (14). The low-temperature softening layer (12) is preferably made of a polymeric material containing an acrylic resin.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: April 6, 2004
    Assignee: Sony Corporation
    Inventors: Akio Machida, Dharam Pal Gosain, Setsuo Usui
  • Patent number: 6670657
    Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: December 30, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Olivier Menut, Yvon Gris
  • Patent number: 6639264
    Abstract: A method for passivating surface states in an integrated circuit structure having a gate conductor with a gate dielectric layer. The method comprises the step of fabricating a solid state source of fluorine in close proximity to the gate dielectric layer. In addition, an integrated circuit structure is provided. The structure comprises a substrate having a gate dielectric layer on the substrate and a gate conductor on the substrate above the gate dielectric layer. The gate conductor further comprises an edge and a solid state source of fluorine in close proximity to the gate dielectric layer.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: October 28, 2003
    Assignee: International Business Machines Corporation
    Inventor: Stephen K. Loh
  • Publication number: 20030173565
    Abstract: A method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed in the substrate is hydrogen and optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be done after deposition of a metal layer, or at other process steps as desired.
    Type: Application
    Filed: March 14, 2003
    Publication date: September 18, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Thomas A. Figura, J. Brett Rolfson
  • Patent number: 6593164
    Abstract: A cyano process of introducing cyano ions (CN−) into an amorphous silicon layer is performed after the amorphous silicon layer has been formed over a substrate or after the layer has been exposed to light. For example, the substrate is immersed in an aqueous solution containing potassium cyanide (KCN) in a vessel. The cyano process eliminates factors (e.g., weak bonds, defects, and centers of recombination) of decrease in photoconductivity of the as-deposited amorphous silicon thin film, which are identifiable in the as-deposited film. As a result, the photoconductivity of the amorphous silicon layer is already higher than usual from the beginning and will hardly decrease even upon exposure to light.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: July 15, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hikaru Kobayashi, Hideomi Koinuma
  • Patent number: 6503771
    Abstract: A semiconductor device including a conductive substrate or a first conductive layer formed on the substrate, a non-single-crystal semiconductor layer member is disposed on the conductive substrate or the conductive layer, the non-single-crystal semiconductor layer member having at least one intrinsic, non-single-crystal semiconductor layer, and a second conductive layer disposed on the non-single-crystal semiconductor layer. The intrinsic non-single-crystal semiconductor layer contains sodium and oxygen in very low concentrations where each concentration is 5×1018 atoms/cm3 or less.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: January 7, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6492659
    Abstract: To fabricate a crystalline semiconductor film with controlled locations and sizes of the crystal grains, and to utilize the crystalline semiconductor film in the channel-forming region of a TFT in order to realize a high-speed operable TFT. A translucent insulating thermal conductive layer 2 is provided in close contact with the main surface of a substrate 1, and an insular or striped first insulating layer 3 is formed in selected regions on the thermal conductive layer. A second insulating layer 4 and semiconductor film 5 are laminated thereover. The semiconductor film 5 is first formed with an amorphous semiconductor film, and then crystallized by laser annealing. The first insulating layer 3 has the function of controlling the rate of heat flow to the thermal conductive layer 2, and the temperature distribution difference on the substrate 1 is utilized to form a single-crystal semiconductor film on the first insulating layer 3.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: December 10, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Publication number: 20020171082
    Abstract: A two-step chlorination/alkylation technique used to introduce alkyl groups, —CnH2n+1 (n=1-6), functionally onto single-crystal, (111)-oriented, n-type Si surfaces. H-terminated Si photoanodes were unstable under illumination in contact with an aqueous 0.35 M K4Fe(CN)6-0.05 MK3Fe(CN)6 electrolyte. Such electrodes displayed low open-circuit voltages and exhibited a pronounced time-dependent deterioration in their current density vs potential characteristics due to anodic oxidation. In contrast, Si surfaces functionalized with —CH3 and —C2H5 groups displayed significant improvements in stability while displaying excellent electrochemical properties when used as photoelectrodes in the aqueous Fe(CN)63−/4− electrolyte.
    Type: Application
    Filed: May 4, 1999
    Publication date: November 21, 2002
    Inventor: NATHAN LEWIS
  • Publication number: 20020153563
    Abstract: There is provided a method of fabricating a silicon-on-insulator substrate, including the steps of (a) forming a silicon substrate at a surface thereof with an oxygen-containing region containing oxygen at such a concentration that oxygen is not precipitated in the oxygen-containing region in later mentioned heat treatment, (b) forming a silicon oxide film at a surface of the silicon substrate, (c) implanting hydrogen ions into the silicon substrate through the silicon oxide film, (d) overlapping the silicon substrate and a support substrate each other so that the silicon oxide film makes contact with the support substrate, and (e) applying heat treatment to the thus overlapped silicon substrate and support substrate to thereby separate the silicon substrate into two pieces at a region into which the hydrogen ions have been implanted, one of the two pieces remaining on the silicon oxide film as a silicon-on-insulator active layer.
    Type: Application
    Filed: March 3, 2000
    Publication date: October 24, 2002
    Inventor: Atsushi Ogura
  • Publication number: 20020134981
    Abstract: Provided is a technique of effectively removing a metallic element that has catalytic action in terms of the crystallization of a semiconductor film and remains in a semiconductor film obtained using the metallic element. With the technique of the present invention, to remove a catalytic element used to crystallize a semiconductor film having an amorphous structure, gettering is completed by forming a region or a semiconductor film, to which a rare gas element is added, and by having the catalytic element move to the formed region or semiconductor film.
    Type: Application
    Filed: January 28, 2002
    Publication date: September 26, 2002
    Inventors: Osamu Nakamura, Masayuki Kajiwara, Shunpei Yamazaki, Hideto Ohnuma
  • Patent number: 6433269
    Abstract: A cyano process of introducing cyano ions (CN−) into an amorphous silicon layer is performed after the amorphous silicon layer has been formed over a substrate or after the layer has been exposed to light. For example, the substrate is immersed in an aqueous solution containing potassium cyanide (KCN) in a vessel. The cyano process eliminates factors (e.g., weak bonds, defects, and centers of recombination) of decrease in photoconductivity of the as-deposited amorphous silicon thin film, which are identifiable in the as-deposited film. As a result, the photoconductivity of the amorphous silicon layer is already higher than usual from the beginning and will hardly decrease even upon exposure to light.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: August 13, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hikaru Kobayashi, Hideomi Koinuma
  • Patent number: RE43819
    Abstract: A thin film transistor array substrate device includes a gate line formed on a substrate, a data line crossing the gate line with a gate insulating pattern position therebetween, a thin film transistor at a crossing of the gate line and the data line, a pixel electrode formed at a pixel region defined by the crossing of the gate line and the data line and connected to the thin film transistor, a gate pad part having a lower gate pad electrode connected to the gate line and an upper gate pad electrode connected to the lower gate pad electrode, a data pad part having a lower data pad electrode connected to the date line and an upper data pad electrode connected to the lower data pad electrode, and a passivation film pattern formed at a region besides the region including the pixel electrode, the upper data pad electrode, and the upper gate pad electrode, wherein the pixel electrode is formed on the gate insulating pattern of the pixel region exposed by the passivation film pattern.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 20, 2012
    Assignee: LG Display Co., Ltd.
    Inventors: Byoung Ho Lim, Hee Chun Boo, legal representative, Hyun Sik Seo, Heung Lyul Cho, Hong Sik Kim