Abstract: A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes three or more bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and a diode connected in series with the three or more bipolar transistors and one of the first and second nodes. Each of the three or more bipolar transistors includes a collector comprising collector components, an emitter comprising emitter components, and a base structure comprising a substrate region or an active region. The emitter components are alternately located with respect to the collector components. The substrate region or the active region surrounds the collector components and the emitter components. Other embodiments are also described.

Abstract: In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.

Abstract: The present disclosure provides one embodiment of a SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters. The pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel.

Abstract: A semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, said portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein t

Abstract: Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.

Abstract: A bipolar transistor having an upper surface, comprises a multilevel collector structure formed in a base region of opposite conductivity type and having a first part of a first vertical extent coupled to a collector contact, an adjacent second part having a second vertical extent a third part of a third vertical extent and desirably of a depth different from a depth of the second part, coupled to the second part by a fourth part desirably having a fourth vertical extent less than the third vertical extent. A first base region portion overlies the second part, a second base region portion separates the third part from an overlying base contact region, and other base region portions laterally surround and underlie the multilevel collector structure. An emitter proximate the upper surface is laterally spaced from the multilevel collector structure. This combination provides improved gain, Early Voltage and breakdown voltages.

Abstract: In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.

Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.

Abstract: A semiconductor device according to embodiments of the invention includes an n?-type drift region; a p-type base region formed selectively in the surface portion of the drift region; an n+-type emitter region and a p+-type body region, both formed selectively in the surface portion of base region; and an n-type shell region between the drift region and the base region, a shell region surrounding the entire region below base region. The shell region is doped more heavily than the drift region. The shell region contains an n-type impurity at an effective impurity amount of 8.0×1011 cm ?2 or smaller. A drift region exhibits a resistivity low enough to prevent the depletion layer expanding from collector region, formed on the back surface of the drift region, toward a shell region from reaching the shell region.

Abstract: A bipolar transistor at least includes a semiconductor substrate including an N? epitaxial growth layer and a P? silicon substrate, an N+ polysilicon layer, a tungsten layer, two silicide layers, a base electrode, an emitter electrode, and a collector electrode. The N+ polysilicon layer formed on the semiconductor substrate is covered with one of the silicide layers. The tungsten layer that is formed on the silicide layer is covered with the other silicide layer.

Abstract: A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.

Abstract: The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7).

Abstract: A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.

Abstract: A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.

Abstract: A nanometer-scale post structure and a method for forming the same are disclosed. More particularly, a post structure, a light emitting device using the structure, and a method for forming the same, which is capable of forming a nanometer-scale post structure having a repetitive pattern by using an etching process, are disclosed. The method includes forming unit patterns on a substrate by use of a first material, growing a wet-etchable second material on the substrate formed with the unit patterns, and wet etching the substrate having the grown second material.

Abstract: An integrated circuit including a memory cell includes a vertical bipolar select device including a base and an emitter. The memory cell includes a resistive memory element coupled to the emitter and a buried metallized word line contacting the base.

Abstract: A bipolar transistor has a base with an epitaxial base layer and a raised base connection region which in a lateral direction in parallel relationship with the substrate surface encloses the emitter which is surrounded by a spacer of insulating material. The epitaxial base layer is raised in a heightwise direction perpendicularly to the substrate surface. An emitter of a T-shaped cross-sectional profile is separated laterally from the outer base portion by a spacer of insulating material. Its vertical bar of the T-shape adjoins with its lower end the inner base portion.

Abstract: Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure includes a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further includes a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.

Abstract: Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure comprises a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further comprises a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.

Abstract: A layout structure for a CMOS circuit comprises a transistor layer forming P-type transistors 11 and 21 and N-type transistors 12 and 22, and a resistor layer which includes a resistor 13 formed to have a predetermined length and to make plural appropriate portions or the entire of the resistor along a direction of the length satisfy a mask rule necessary for providing VIAs, the resistor being connected to appropriate connecting portions of the P-type transistors and the N-type transistors through the VIAs by metal wires 31 formed of a metal layer, and the resistor having a predetermined circuit resistance which can be set based on the positions of the appropriate connecting portions.

Abstract: A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

Abstract: A bipolar transistor having enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film as a mask to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront each other, and an increase in resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have enhanced characteristics.

Abstract: The present invention is generally directed to bipolar transistors with geometry optimized for device performance and various methods of making same. In one illustrative embodiment, the device includes a substrate, an intrinsic base region formed in the substrate, a continuous emitter region formed within the intrinsic base region, the emitter region having a plurality of substantially hexagonal shaped openings defined therein, and a plurality of extrinsic base regions formed in the substrate, wherein each of the extrinsic base regions is positioned within an area defined by one of the plurality of substantially hexagonal shaped openings.

Abstract: A method of fabricating a semiconductor device uses selective epitaxial growth (SEG), by which leakage current generation is minimized using lateral SEG growth in case a contact intrudes a shallow track isolation feature. The method includes steps of forming a sidewall spacer on a gate, selectively growing an epitaxial layer in a lateral direction relative to the sidewall spacer and the gate, and forming a contact on the epitaxial layer.

Abstract: A bipolar transistor of the present invention comprises a collector layer made of an n-type semiconductor and an emitter layer made of an n-type semiconductor provided on this collector layer. A gate layer for injecting p-type carriers (holes) into the emitter layer is provided on the emitter layer. A p-type carrier retaining layer is formed between the collector layer and the emitter layer. The p-type carrier retaining layer temporarily retains the p-type carriers that are injected from the gate layer into the emitter layer and diffused in the emitter layer and reach the p-type carrier retaining layer. The bipolar transistor has a structure whose performance is not influenced by sheet resistance of the base layer, and is able to exhibit a high current gain even in a high-frequency region.

Abstract: The intrinsic base region of a bipolar transistor is formed to avoid a chemical interaction between the chemicals used in a chemical mechanical polishing step and the materials used to form the base region. The method includes the step of forming a trench in a layer of epitaxial material. After this, a base material that includes silicon and germanium is blanket deposited, followed by the blanket deposition of a layer of protective material. The layer of protective material protects the base material from the chemical mechanical polishing step.

Abstract: The gist of the present invention is as follows: In a monolithic microwave integrate circuit (MMIC) using a heterojunction bipolar transistor (HBT), via holes are respectively formed from the bottom of the MMIC for the emitter, base and collector. Of the via holes, one is located so as to face the HBT. The respective topside electrodes for the other via holes located so as not to face the HBT are provided in contact with the MMIC substrate.

Abstract: A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in a collector region 13 is formed on the surface of the semiconductor substrate 1; and a base semiconductor layer 14B is formed in contact with the collector region through the first opening 51. The base semiconductor layer 14B is formed such that the edge thereof extends onto the first insulating layer 31.

Abstract: The present invention is a modified darlington phototransistor wherein a phototransistor is coupled to a Bipolar Junction Transistor (BJT). This design provides a high sensitivity and a fast response and effectively increases the gain of the photocurrent. This circuit is particularly will suited for the readily available CMOS and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) processes prevalent today.

Abstract: Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base structures, comprising a carbide layer situated between first and second oxide layers. The carbide layer provides an etch stop for etching the overlying oxide layer, and the underlying oxide layer provides an etch stop for etching the carbide layer to form an emitter-base contact opening.

Abstract: According to the present invention, a metal and a barrier material, such as copper and a tantalum-based barrier material, are effectively removed from the wafer edge and especially from the bevel by using an etchant that comprises a diluted mixture of hydrofluoric acid and nitric acid. The method is compatible with currently available etch modules for removing metal from the wafer edge, wherein, depending on the hardware specifics, copper, barrier material and dielectric material may be removed in a single etch step, or a first etch step may be performed substantially without any nitric acid so as to avoid the formation of nitric oxides. In this way, the formation of instable layer stacks may be substantially avoided, thereby reducing the risk of material delamination from the substrate edge.

Abstract: An epitaxial base bipolar transistor comprising an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on the semiconductor surface; a raised extrinsic base on the surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein said insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in said single crystal substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to said substrate surface, wherein said emitter to base surface height difference is less than 20% of said emitter junction depth is provided as well as methods for fabricating the same.

Abstract: A non-uniform depth base-emitter junction, with deeper junction at the lateral portions of the emitter, preferably coupled with a recessed and raised extrinsic base, bipolar transistor, and a method of making the same. The bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a recessed and raised extrinsic base layer formed on the silicon germanium layer, and a silicon pedestal on which an emitter layer is formed. The emitter has non-uniform depths into the base layer.

Abstract: A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.

Abstract: A transistor and method for making the same are disclosed. The transistor is constructed from a collector layer, a base layer, and an emitter layer in a stacked arrangement. The emitter layer is etched to form a mesa on an etched surface, the mesa having a top surface that includes a portion of the emitter layer and an emitter contact and sides joining the top surface with the etched surface. First and second protective layers are then deposited over the emitter contact and etched surface and the portions of these layers that overlie the etched surface are removed. The first protective layer is then preferentially etched thereby undercutting a portion of the first protective layer on the sides of the mesa and creating an overhanging portion of the second protective layer that is utilized to align the deposition of the base contacts.

Abstract: A transistor and method for making the same are disclosed. The transistor is constructed from a collector layer, a base layer, and an emitter layer in a stacked arrangement. The emitter layer is etched to form a mesa on an etched surface, the mesa having a top surface that includes a portion of the emitter layer and an emitter contact and sides joining the top surface with the etched surface. First and second protective layers are then deposited over the emitter contact and etched surface and the portions of these layers that overlie the etched surface are removed. The first protective layer is then preferentially etched thereby undercutting a portion of the first protective layer on the sides of the mesa and creating an overhanging portion of the second protective layer that is utilized to align the deposition of the base contacts.

Abstract: Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base structures, comprising a carbide layer situated between first and second oxide layers. The carbide layer provides an etch stop for etching the overlying oxide layer, and the underlying oxide layer provides an etch stop for etching the carbide layer to form an emitter-base contact opening.

Abstract: A method is provided for improving edge terminations in a semiconductor device while maintaining breakdown voltage of said semiconductor device at or near its theoretical limit. The method comprises: employing ion-implantation to create a compensated region around the semiconductor device, followed by wet chemical etching to form a mesa on the order of 0.2 to 0.3 &mgr;m. The method provides a simple but novel approach to fabricate edge terminations in semiconductor devices in general and in devices employing p-n junctions such as in a GaAs heterojunction bipolar transistor (HBT) to achieve near-ideal electrical characteristics at the device edge. Instead of traditional edge beveling techniques such as those involving grinding, sandblasting, or mesa-etching using masks, the technique disclosed herein utilizes ion-implantation to create a compensated region around the device and wet chemical etching to make a shallow mesa.

Abstract: A transistor with a novel compact layout is provided. The transistor has an emitter layout having a track with a first feed point and a second feed point whereby current flows through both the first feed point and the second feed point. A base terminal, a collector terminal, and an emitter terminal are provided. When in operation, current flows from the collector terminal to the emitter terminal based on the amount of current provided to the base terminal. A sub-collector layer is formed on a substrate. A collector layer is formed on the sub-collector layer. A base pedestal is formed on the collector layer. A base contact for coupling to the base terminal and an emitter is formed on the base pedestal. An emitter contact for coupling to the emitter terminal is formed on the emitter. A collector contact for coupling to the collector terminal is deposited in a trench that is formed in the collector layer and the sub-collector layer.

Abstract: The invention includes a bipolar transistor construction having a collector region, emitter region, and base region extending within a semiconductive material substrate. The construction further comprises separate access regions associated with the base region, emitter region and collector region, respectively. An n-type doped connecting region is comprised by the collector region and extends beneath the emitter and base regions. A p-type doped location is comprised by the base region and extends beneath the emitter region and above the n-type doped connecting region. An n-type doped intermediate location is within the emitter region and between the p-type doped location and the emitter access region. The invention also includes methods of forming bipolar transistors.

Abstract: A semiconductor amplifier includes collector straps that form air bridges over a set of transistors and make parallel electrical connections between the collectors of the transistor and collector contact pad. Base straps establish base bias and electrically connect a dc current source with bases of the transistors through resistive elements.

Abstract: An emitter of a heterojunction bipolar transistor has a double-layer protrusion formed of a first emitter layer and a second emitter layer and protruded outside an external base region. The protrusion of 50 nm in total thickness is enough to prevent damage during formation of the protrusion by etching or during later fabricating processes. Penetration of moisture through damaged places is eliminated. A base ohmic electrode is continuously formed on the first and second emitter layers on the external base region up to the protrusion. Thus, the protrusion is reinforced so as to be further hard to damage. By ensuring a large area for the base ohmic electrode, an alignment margin can be taken during formation of a base lead electrode.

Abstract: Various embodiments of a novel transistor layout having improved electrical and heat dissipation characteristics are disclosed. Several embodiments include various intrinsic components contoured to the shape of the emitter. The various intrinsic components may include a collector layer center portion, a collector contact, a base pedestal, and/or a base contact. Additional embodiments include improved heat dissipation within single transistors. Still further embodiments include improved heat dissipation across a plurality of transistors.

Abstract: In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.

Abstract: A semiconductor device includes a semiconductor substrate, an electrode disposed on an upper surface of the substrate, and a transistor element disposed on the upper surface of the substrate. The transistor element continuously surrounds the electrode and includes a plurality of contacts that are electrically connected to the electrode. Additionally, the transistor element compactly surrounds the electrode with a threshold distance.

Abstract: According to one embodiment, a semiconductor device including a base, an emitter, and an emitter contact on top of the emitter is disclosed. For example, the semiconductor device can be a silicon-germanium heterojunction bipolar transistor, in which the base is formed from epitaxially deposited silicon-germanium, the emitter is formed from polycrystalline silicon, and the emitter contact is formed as a borderless contact on top of the emitter. The base includes a link base region, an extrinsic base region, and an intrinsic base region. For example, the intrinsic base region can be the region of the base in which the base-emitter junction is formed by out-diffusion of dopants from the emitter. The extrinsic base can be a low resistance region formed by implantation doping to provide a low resistance electrical path from a base contact to the intrinsic base region through the extrinsic base and link base regions. A disclosed structure also includes a link spacer.

Abstract: In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.

Abstract: A monolithically integrated semiconductor device comprises: a hetero-junction bipolar transistor having at least an electrode contact layer which contacts directly with at least one of collector, base and emitter electrodes; and at least a passive device having at least a passive device electrode and at least a resistive layer, wherein the electrode contact layer and the resistive layer comprise the same compound semiconductor layer.