Abstract: A semiconductor device includes: a semiconductor layered structure including a predetermined mesa portion, formed on a semiconductor substrate; a support member formed so as to bury the mesa portion; and an interconnection layer formed on a top surface of the semiconductor layered structure so as to extend over a top surface of the support member. The interconnection layer is in contact with only a top surface of the mesa portion without being in contact with a bottom surface of the mesa portion. The top surface of the support member has a smoothed profile, and the top surface of the mesa portion and the smoothed top surface of the support member are in substantially the same plane.

Abstract: A resistive area 7 is formed selectively on a semi-insulating substrate 1, and ohmic electrodes 10 are formed on both ends of the resistive area. Then a photo resist 14 having an opening 13 between the electrodes 10 is so formed as not completely across the resistive area 7. A desirable resistance value is thus obtained by removing the resistance area 7 by etching through the opening 13 gradually.

Abstract: A transistor with a novel compact layout is provided. The transistor has an emitter layout having a track with a first feed point and a second feed point whereby current flows through both the first feed point and the second feed point. A base terminal, a collector terminal, and an emitter terminal are provided. When in operation, current flows from the collector terminal to the emitter terminal based on the amount of current provided to the base terminal. A sub-collector layer is formed on a substrate. A collector layer is formed on the sub-collector layer. A base pedestal is formed on the collector layer. A base contact for coupling to the base terminal and an emitter is formed on the base pedestal. An emitter contact for coupling to the emitter terminal is formed on the emitter. A collector terminal for coupling to the collector contact is deposited in a trench that is formed in the collector layer and the sub-collector layer.

Abstract: A number of npn and pnp bipolar transistors is formed in a single chip of silicon, so that some of the transistors have a greater frequency response than others. The higher frequency transistors have their emitters located closer to the collectors, by positioning a collector, or emitter, of a transistor in a recessed portion of the surface of the chip. The recess is formed in an accurate and controlled manner by locally oxidizing the silicon surface, and subsequently removing the oxide to leave the recess.

Abstract: Large composite structures are produced using a vacuum assisted resin transfer molding process. The structures incorporate cores, which may be hollow cells or foam blocks. A plurality of cores, each of which may be wrapped with a fiber material, is arranged in a layer on a mold with a fiber material arranged to form face skins. The assembly is sealed under a vacuum bag to a mold surface. One or more main feeder conduits are provided in communication with a resin distribution network of smaller channels which facilitates flow of uncured resin into and through the fiber material. The resin distribution network may comprise a network of grooves formed in the surfaces or the cores and/or rounded corners of the cores. The network of smaller channels may also be provided between the vacuum bag and the fiber material, either integrally in the vacuum bag or via a separate distribution medium.

Abstract: An improved bipolar transistor (202) has an increased Early voltage and can be integrated on a semiconductor die with MOS transistors (201) and other types of devices to form an integrated circuit (200). A p-type base region (240) is disposed in an n-type collector region (252). An n-type emitter region (244) is disposed within the base region, and a p-type enhancement region (250) is formed to extend under the emitter region to a depth greater than the base depth. The improved bipolar transistor can be fabricated without significantly affecting the operation of other devices on the integrated circuit.

Abstract: A heterojunction bipolar transistor has a mesa including collector 604, base 603, and emitter 602 layers. The mesa has first and second sidewalls 606. An improved heat dissipation structure comprises a layer of electrically insulative and thermally conductive material 607 disposed on one of the sidewalls. A thermal path metal 600 is electrically connected to the emitter 602 and is disposed on the layer of electrically insulative and thermally conductive material 607. The thermal path metal 600 extends from the emitter 602 to the substrate 608 providing for efficient dissipation of heat that is generated by the HBT device.

Abstract: The present invention is directed to an improved deep trench structure, for use in junction devices, which addresses junction breakdown voltage instabilities of the prior art. The primary, or metallurgical, junction where avalanche breakdown occurs is moved away from the surface dielectric into the bulk silicon by adding a lightly doped layer adjacent to the deep trench. A preferred embodiment suitable for isolated structures places the doped layer adjacent to the sidewalls of the deep trench. A second preferred embodiment, suitable for non-isolated structures, places the doped layer adjacent to both the floor and the sidewalls of the trench.

Abstract: A mesa bipolar transistor comprising a collector layer formed on a surface of a substrate, a base layer disposed on the substrate so as to be joined to the collector layer, an emitter layer disposed on the base layer is further provided with a sub base layer comprising at least one of a polysilicon layer containing impurities, a metallic silicide, and a diffused layer formed on the surface of the substrate and being disposed under or on the external base region which is a region of the base layer lateral to that under the emitter layer so that the thickness of the external base region is increased to provide high conductivity.

Abstract: A semiconductor device having the base and collector surrounded by a continuous tungsten filled slot as ground plane. The portion of the tungsten filled slot over the buried layer extends beyond the surface of the buried layer and the portion of the tungsten filled slot not over the buried layer extends beyond the interface between the epitaxial layer and the substrate.

Abstract: This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.

Abstract: A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.

Abstract: A lateral bipolar transistor and method of making the transistor are disclosed. The device is made by etching a trench around a central region of a semiconductor body. An emitter is buried beneath the surface of this central area and contact to it is made via a self-alignment technique. The collector region of the transistor is contacted through the floor of the trench while the base region of the transistor is contacted in a region that surrounds the trench. The described method is compatible with the simultaneous manufacture of FET devices on the same chip.

Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with an elevated emitter structure. An elevation structure raises the BJT emitter above the plane of the base. The elevation structure increases travel distance between a heavily doped base contact region and the emitter and protects against encroachment without increasing the total surface area allocated to the BJT device. A spacer oxide separates the polysilicon base contact and the elevation structure.

Abstract: A process for manufacturing a semiconductor switching device (such as a thyristor device) comprises: etching a face of a semiconductor body to provide islands and channels which define a mesa-contoured surface; diffusing dopant of a first conductivity type through said surface so that the lines of equal concentration of the dopant in said body follow substantially the mesa-contoured surface; and diffusing dopant of a second conductivity type into said islands to form p-n junctions with said dopant of a first conductivity type. The diffusion of said dopant of a first conductivity type is followed by an out-diffusion step so that the dopant concentration of said dopant of a first conductivity type is at a maximum at a depth below said surface.

Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

Abstract: Generally, and in one form of the invention, a microwave heterojunction bipolar transistor suitable for low-power, low-noise and high-power applications having an emitter, a base 50 and a collector 70 is disclosed, wherein the emitter composed of one or more islands 30 of semiconductor material having a wider energy bandgap than the base 50. The islands 30 are formed so that they do not cross any boundaries of the active area 60 of the transistor.Other devices, systems and methods are also disclosed.

Abstract: Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.

Abstract: In a bipolar device, selective epitaxial silicon provides an improved intrinsic-extrinsic base link. A trench physically separates an intrinsic and extrinsic base portion. The trench includes sidewalls having a thin oxide layer formed thereon. The bottom of the trench is exposed during processing. A shallow link between the intrinsic-extrinsic regions of a bipolar transistor base is formed by depositing a heavily boron doped layer of silicon on the exposed portion of the trench. During subsequent processing, including rapid thermal anneal, there is some boron out-diffusion which forms a shallow diffused intrinsic-extrinsic base link.

Abstract: A semiconductor device with a semiconductor body (1) is provided with a first and a second bipolar transistor (T1, T2, respectively) in a cascode configuration, in which the semiconductor body (1) comprises, in that order, a collector region (10) and a base region (11) of the first transistor (T1), a region (12) which forms both an emitter region of the first transistor (T1) and a collector region of the second transistor (T2), a space charge region (13), and a base region (14) and emitter region (15) of the second transistor (T2), while the regions form pn junctions with one another which extend parallel to a main surface (2) of the semiconductor body (1). The base region (14) and the emitter region (15) of the second transistor (T2) adjoin a main surface (3) of the semiconductor body (1).

Abstract: A heterojunction bipolar transistor comprises n.sup.+ -type GaAs collector contact region, an n-type GaAs collector region, a p.sup.+ -type GaAs base region, an n-type AlGaAs emitter region, and an n.sup.+ -type InGaAs emitter contact region, all of which are formed on a semiinsulative GaAs substrate. A heterojunction is formed by the base region and the emitter region. The emitter region is formed in mesa shape by dry etching. Around this mesa, B.sup.+ ion-implanted high-resistance region is formed. The base-emitter Junction is isolated from the ion-implanted region. The heterojunction bipolar transistor therefore has little on-voltage changes.

Abstract: A semiconductor device including a semiconductor substrate, first and second bipolar transistors formed at the major surface of the semiconductor substrate, a Schottky-barrier diode formed on a predetermined area of each of the first and second bipolar transistors, a capacitor formed on each of the first and second bipolar transistors, each capacitor including an insulating layer covering a surface of a respective one of the first and second bipolar transistors, a polysilicon layer formed on the insulating layer in a pattern that extends around the predetermined area, a dielectric film formed covering the polysilicon layer, and a conductive film covering the dielectric film.

Abstract: A hetero junction bipolar transistor provides a contact area an area between an emitter (or collector) electrode and a wiring formed on the electrode that is larger than that of the emitter (or collector). A variation in voltage applied to an emitter (or collector)-base junctions is prevented and a stable operation of the transistor is attained. In addition, when an etching operation is carried out, an insulation film is formed on a side part of a mask. A patterning of the emitter (or collector) is then carried out and thus an emitter (or collector) having a size approximate to that of the mask is formed.

Abstract: Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.

Abstract: A semiconductor device and a method of manufacture thereof by which the device is formed without an epitaxial growth process are provided. The semiconductor device has low circuit resistance and is highly reliable due to a sufficient device strength. Although a base layer or other devices are formed in an N.sup.- type silicon layer, the process of epitaxial growth is eliminated, because the semiconductor substrate (2) consists entirely of the N.sup.- type silicon. Further, the substrate has a bottom recessed part (4) which extends near a base layer (21). A collector electrode (8) is attached to the bottom recessed part (4), allowing collector resistance to be reduced. Moreover, the substrate (2) is not formed thin throughout, partly provided with the bottom recessed part (4). As a result, the resulting semiconductor device holds a sufficient strength.

Abstract: According to the present invention, the hetero junction bipolar transistor (HBT) is provided which includes an emitter layer consisting of a first semiconductor of a first conductive type and being in mesa form; a base layer being in contact with the emitter layer and consisting of a second semiconductor of a second conductive type having a narrower band gap than the first semiconductor; and a collector layer being in contact with the base layer and consisting of a third semiconductor of a first conductive type having a broader band gap than the second semiconductor. In this HBT, a monolayer sulfur film is formed so as to cover the exposed periphery of the heterointerface between the emitter layer and the base layer.

Abstract: A semiconducting component with a Schottky junction with stacked electrodes has a lower electrode forming an emitter or source, a central electrode forming a base or grid and an upper electrode forming either a collector or a drain. Semiconductor material is between the upper electrode and the lower electrode. The central control electrode is in the form of several adjacent conducting fingers. An insulating material is in the region directly below the fingers between the control electrode and the lower electrode, thereby reducing parasitic capacitance between the control electrode and the lower electrode.