With Base Region Having Specified Doping Concentration Profile Or Specified Configuration (e.g., Inactive Base More Heavily Doped Than Active Base Or Base Region Has Constant Doping Concentration Portion (e.g., Epitaxial Base)) Patents (Class 257/592)
  • Patent number: 9577045
    Abstract: In a general aspect, a power semiconductor device can include a collector region disposed on a substrate, the collector region can include n-type silicon carbide (SiC). The power semiconductor device can also include a base region disposed on the collector region. The base region can include p-type SiC doped with gallium. The power semiconductor device can include an emitter region disposed on the base region. The emitter region can include n-type SiC carbide.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: February 21, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Andrei Konstantinov
  • Patent number: 9355972
    Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in <100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: May 31, 2016
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Zhong-Xiang He, Qizhi Liu
  • Patent number: 9306043
    Abstract: A bipolar junction transistor and an operating method and a manufacturing method for the same are provided. The bipolar junction transistor comprises a first doped region, a second doped region and a third doped region. The first doped region has a first type conductivity. The second doped region comprises well regions formed in the first doped region, having a second type conductivity opposite to the first type conductivity, and separated from each other by the first doped region. The third doped region has the first type conductivity. The third doped region is formed in the well regions or in the first doped region between the well regions.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: April 5, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Li-Fan Chen, Wing-Chor Chan, Jeng Gong
  • Patent number: 9240468
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate. The device also includes a bipolar transistor on the semiconductor substrate. The bipolar transistor includes an emitter. The bipolar transistor also includes a base located above the emitter. The bipolar transistor further includes a laterally extending collector located above the base. The collector includes a portion that extends past an edge of the base.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: January 19, 2016
    Assignee: NXP, B.V.
    Inventors: Tony Vanhoucke, Viet Thanh Dinh, Anco Heringa, Dirk Klaassen, Evelyne Gridelet, Jan Willem Slotboom
  • Patent number: 9202900
    Abstract: A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: December 1, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: James W. Adkisson, Kevin K. Chan, David L. Harame, Qizhi Liu, John J. Pekarik
  • Patent number: 9147756
    Abstract: The invention relates to an electronic device with a bipolar transistor having an emitter, a base and a collector. The base has a first region of a first concentration of the first dopant for forming an electrically active region of the base and a second region of a second concentration of the first dopant close to the surface of the base region. The first region is separated from the second region by a region of a third concentration of the first dopant and the third concentration is lower than the first and the second concentration.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: September 29, 2015
    Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Philipp Menz, Berthold Staufer, Yasuda Hiroshi
  • Patent number: 9129836
    Abstract: A circuit includes first, second, third and fourth terminals, and first and second switches. The first switch switches a first signal from the first terminal to the second terminal or from the first terminal to the fourth terminal. The second switch switches a second signal from the third terminal to the second terminal or from the third terminal to the fourth terminal. The first switch comprises a first switching element with a first high-frequency switching transistor connected between the first terminal and the second terminal, and a second switching element with a second high-frequency switching transistor connected between the first terminal and the fourth terminal. The second switch comprises a third switching element with a third high-frequency transistor connected between the third terminal and the second terminal and comprises a fourth switching element with a fourth high-frequency switching transistor connected between the third terminal and the fourth terminal.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: September 8, 2015
    Assignee: Infineon Technologies, AG
    Inventors: Reinhard Losehand, Hans Taddiken, Udo Gerlach
  • Patent number: 9035426
    Abstract: A bipolar junction transistor (BJT) formed using a fin field-effect transistor (FinFET) complimentary metal-oxide-semiconductor (CMOS) process flow is provided. The BJT includes an emitter fin, a base fin, and a collector fin formed on a substrate. The base fin encloses the emitter fin and collector fin encloses the emitter fin. In some embodiments, the emitter fin, base fin, and collector fin have a square shape when viewed from above and are concentric with each other.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh
  • Patent number: 9006864
    Abstract: A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an intrinsic p-type base region of the NPN bipolar junction transistor at a boundary of the intrinsic p-type base region with a dielectric layer over a substrate of the semiconductor device, between an emitter of the NPN bipolar junction transistor and an extrinsic p-type base region of the NPN bipolar junction transistor. The p-type RIDS region has a doping density high enough to prevent inversion of a surface of the p-type RIDS region adjacent to the dielectric layer when trapped charge is accumulated in the dielectric layer, while the intrinsic p-type base region may invert from the trapped charge forming the radiation induced diode structure. The p-type RIDS region is separated from the emitter and from the extrinsic base region by portions of the intrinsic base region.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: James Fred Salzman, Richard Guerra Roybal, Randolph William Kahn
  • Patent number: 9000565
    Abstract: A semiconductor device including a protection device and a protected device, the protection device includes a first semiconductor region of a second conductivity type formed over a substrate, a second semiconductor region of the second conductivity type provided in the first semiconductor region, having a higher impurity concentration than the first semiconductor region, a third semiconductor region of the second conductivity type formed in a surface layer of the second semiconductor region, having a higher impurity concentration than the second semiconductor region, a fourth semiconductor region of the second conductivity type formed in the first semiconductor region and located away from the third semiconductor region, having a higher impurity concentration than the first semiconductor region, a fifth semiconductor region of a first conductivity type formed in the first semiconductor region and electrically short-circuited with the fourth semiconductor region, and a sixth semiconductor region of the first c
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Fujii
  • Patent number: 8981521
    Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: March 17, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Tzu Wang, Pei-Shan Tseng, Tien-Hao Tang
  • Patent number: 8946863
    Abstract: An epitaxial substrate for electronic devices, in which current flows in a lateral direction and of which warpage configuration is properly controlled, and a method of producing the same. The epitaxial substrate for electronic devices is produced by forming a bonded substrate by bonding a low-resistance Si single crystal substrate and a high-resistance Si single crystal substrate together; forming a buffer as an insulating layer on a surface of the bonded substrate on the high-resistance Si single crystal substrate side; and producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate. The resistivity of the low-resistance Si single crystal substrate is 100 ?·cm or less, and the resistivity of the high-resistance Si single crystal substrate is 1000 ?·cm or more.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: February 3, 2015
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Ryo Sakamoto, Tomohiko Shibata
  • Patent number: 8946862
    Abstract: Methods are provided for forming a device that includes merged vertical and lateral transistors with collector regions of a first conductivity type between upper and lower base regions of opposite conductivity type that are Ohmically coupled via intermediate regions of the same conductivity type and to the base contact. The emitter is provided in the upper base region and the collector contact is provided in outlying sinker regions extending to the thin collector regions and an underlying buried layer. As the collector voltage increases part of the thin collector regions become depleted of carriers from the top by the upper and from the bottom by the lower base regions. This clamps the collector regions' voltage well below the breakdown voltage of the PN junction formed between the buried layer and the lower base region. The gain and Early Voltage are increased and decoupled and a higher breakdown voltage is obtained.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8927381
    Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: David L. Harame, Qizhi Liu
  • Patent number: 8871599
    Abstract: Disclosed is an integrated circuit and a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate comprising a pair of isolation regions separated by an active region comprising a collector; forming a base layer stack over said substrate; forming a migration layer having a first migration temperature and an etch stop layer; forming a base contact layer having a second migration temperature; etching an emitter window in the base contact layer, thereby forming cavities extending from the emitter window; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventors: Johannes Josephus Theodorus Marinus Donkers, Petrus Hubertus Cornelis Magnee, Blandine Duriez, Evelyne Gridelet, Hans Mertens, Tony Vanhoucke
  • Patent number: 8835987
    Abstract: An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: September 16, 2014
    Assignee: Cree, Inc.
    Inventor: Qingchun Zhang
  • Patent number: 8829600
    Abstract: Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: September 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kenji Hatori
  • Patent number: 8810005
    Abstract: A bipolar device with an entirely monocrystalline intrinsic base to extrinsic base link-up region. To form the device, a first extrinsic base layer, which is amorphous or polycrystalline, is deposited such that it contacts an edge portion of a monocrystalline section of an intrinsic base layer through an opening in a dielectric layer. A second extrinsic base layer is deposited on the first. An anneal is performed, either before or after deposition of the second extrinsic base layer, so that the extrinsic base layers are monocrystalline. An opening is formed through the extrinsic base layers to a dielectric landing pad aligned above a center portion of the monocrystalline section of the intrinsic base layer. The dielectric landing pad is removed and a semiconductor layer is grown epitaxially on exposed monocrystalline surfaces of the extrinsic and intrinsic base layers, thereby forming the entirely monocrystalline intrinsic base to extrinsic base link-up region.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Renata A. Camillo-Castillo, Peng Cheng, Peter B. Gray, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
  • Patent number: 8791546
    Abstract: A bipolar transistor comprises at least first and second connected emitter-base (EB) junctions having, respectively, different first and second EB junction depths, and a buried layer (BL) collector having a greater third depth. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region overlies the second EB junction location thereby providing its shallower EB junction depth. The BL collector does not underlie the first EB junction and is laterally spaced therefrom by a variable amount to facilitate adjusting the transistor's properties. In other embodiments, the BL collector can underlie at least a portion of the second EB junction. Regions of opposite conductivity type over-lie and under-lie the BL collector, which is relatively lightly doped, thereby preserving the breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: July 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Bernhard H. Grote, Jiang-Kai Zuo
  • Patent number: 8786051
    Abstract: Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, David L. Harame, Qizhi Liu
  • Patent number: 8785945
    Abstract: New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are provided. The SiC BJT can include a collector region, a base region, and an emitter region where the collector region, the base region, and the emitter region are arranged as a stack. The emitter region can form an elevated structure defined by outer sidewalls disposed on the stack. The base region can have a portion interfacing the emitter region and defining an intrinsic base region. The intrinsic base region can include a first portion laterally spaced away from the outer sidewalls of the emitter region by a second portion of the base region that has a dopant dose higher than a dopant dose of the first portion.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: July 22, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Andrei Konstantinov
  • Patent number: 8754484
    Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroshi Yasuda, Berthold Staufer
  • Patent number: 8736023
    Abstract: A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Yanfeng Wang
  • Patent number: 8723295
    Abstract: The present invention makes it possible to inhibit an SOA (Safe Operating Area) in a vertical-type bipolar transistor from narrowing. A p-type base layer 150 includes a first peak, a second peak, and a third peak in an impurity profile in the thickness direction. The first peak is located on the topmost surface side of a semiconductor substrate 100. The second peak is located closer to the bottom face side of the semiconductor substrate 100 than the first peak and higher than the first peak. The third peak is located between the first peak and the second peak.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: May 13, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuki Fukui, Hiroaki Katou
  • Publication number: 20140124895
    Abstract: A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an intrinsic p-type base region of the NPN bipolar junction transistor at a boundary of the intrinsic p-type base region with a dielectric layer over a substrate of the semiconductor device, between an emitter of the NPN bipolar junction transistor and an extrinsic p-type base region of the NPN bipolar junction transistor. The p-type RIDS region has a doping density high enough to prevent inversion of a surface of the p-type RIDS region adjacent to the dielectric layer when trapped charge is accumulated in the dielectric layer, while the intrinsic p-type base region may invert from the trapped charge forming the radiation induced diode structure. The p-type RIDS region is separated from the emitter and from the extrinsic base region by portions of the intrinsic base region.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 8, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: James Fred SALZMAN, Richard Guerra ROYBAL, Randolph William KAHN
  • Patent number: 8710627
    Abstract: An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: April 29, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
  • Patent number: 8686424
    Abstract: Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14?), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 1, 2014
    Assignee: NXP, B.V.
    Inventors: Evelyne Gridelet, Johannes Josephus Theodorus Marinus Donkers, Tony Vanhoucke, Petrus Hubertus Cornelis Magnee, Hans Mertens, Blandine Duriez
  • Patent number: 8669640
    Abstract: An improved device (20) is provided, comprising, merged vertical (251) and lateral transistors (252), comprising thin collector regions (34) of a first conductivity type sandwiched between upper (362) and lower (30) base regions of opposite conductivity type that are Ohmically coupled via intermediate regions (32, 361) of the same conductivity type and to the base contact (38). The emitter (40) is provided in the upper base region (362) and the collector contact (42) is provided in outlying sinker regions (28) extending to the thin collector regions (34) and an underlying buried layer (28). As the collector voltage increases part of the thin collector regions (34) become depleted of carriers from the top by the upper (362) and from the bottom by the lower (30) base regions. This clamps the thin collector regions' (34) voltage well below the breakdown voltage of the PN junction formed between the buried layer (28) and the lower base region (30).
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: March 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8669603
    Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: March 11, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Kunal R. Parekh
  • Patent number: 8664697
    Abstract: To provide a transistor device, which is composed of a compound semiconductor, having a multilayer structure in which a high electron mobility transistor (HEMT) and a heterojunction bipolar transistor (HBT) are overlapped on the same substrate and epitaxial-grown thereon, wherein a band gap energy of an indium gallium phosphide layer (InGaP) included in an epitaxial layer, is set to 1.91 eV or more.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 4, 2014
    Assignee: Hitachi Cable, Ltd.
    Inventors: Takeshi Meguro, Jiro Wada, Yoshihiko Moriya
  • Patent number: 8643146
    Abstract: A carrier is prevented from being stored in a guard ring region in a semiconductor device. The semiconductor device has an IGBT cell including a base region and an emitter region formed in an n? type drift layer, and a p type collector layer arranged under the drift layer with a buffer layer interposed therebetween. A guard ring region having a guard ring is arranged around the IGBT cell. A lower surface of the guard ring region has a mesa structure provided by removing the collector layer.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 4, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hitoshi Uemura
  • Publication number: 20140027776
    Abstract: In accordance with an embodiment of the present invention a transistor is disclosed. The transistor comprises a collector, a base and an emitter, wherein a first end width of the base is larger than a middle width of the base, wherein a first end width of the collector is larger than a middle width of the collector, or wherein a first end width of the emitter is larger than a middle width of the emitter.
    Type: Application
    Filed: September 26, 2013
    Publication date: January 30, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Klaus Diefenbeck
  • Patent number: 8637959
    Abstract: The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: January 28, 2014
    Assignee: Shanghai Hua Hong NEC Electronics
    Inventors: Wensheng Qian, Donghua Liu, Jun Hu
  • Patent number: 8624355
    Abstract: A semiconductor device includes an n-type first guard ring layer provided between an emitter layer and a collector layer on a surface side of a base layer, and having a higher n-type impurity concentration than the base layer, and an n-type second guard ring layer provided between the first guard ring layer and a buried layer, connected to the first guard ring layer and the buried layer, and having a higher n-type impurity concentration than the base layer. The first guard ring layer has an n-type impurity concentration profile decreasing toward the second guard ring layer side, and the second guard ring layer has an impurity concentration profile decreasing toward the first guard ring layer side.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: January 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koji Shirai
  • Patent number: 8623749
    Abstract: In one embodiment, a method includes forming a base region for a transistor using a base mask and forming a contact region to the base region. The contact region is formed in an area that is at least partially outside of the base mask. The method then forms an emitter region in a diffused base region. The base region diffuses outwardly to be formed under the contact region.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: January 7, 2014
    Assignee: Diodes Incorporated
    Inventor: David Neil Casey
  • Patent number: 8609502
    Abstract: In a method of manufacturing a semiconductor device, a semiconductor substrate of a first conductivity type having first and second surfaces is prepared. Second conductivity type impurities for forming a collector layer are implanted to the second surface using a mask that has an opening at a portion where the collector layer will be formed. An oxide layer is formed by enhanced-oxidizing the collector layer. First conductivity type impurities for forming a first conductivity type layer are implanted to the second surface using the oxide layer as a mask. A support base is attached to the second surface and a thickness of the semiconductor substrate is reduced from the first surface. An element part including a base region, an emitter region, a plurality of trenches, a gate insulating layer, a gate electrode, and a first electrode is formed on the first surface of the semiconductor substrate.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: December 17, 2013
    Assignee: DENSO CORPORATION
    Inventors: Masaki Koyama, Yutaka Fukuda
  • Publication number: 20130307122
    Abstract: The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region.
    Type: Application
    Filed: September 24, 2012
    Publication date: November 21, 2013
    Applicant: TSINGHUA UNIVERSITY
    Inventors: Yu-dong Wang, Jun Fu, Jie Cui, Yue Zhao, Zhi-hong Liu, Wei Zhang, Gao-qing Li, Zheng-li Wu, Ping Xu
  • Patent number: 8569865
    Abstract: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: October 29, 2013
    Assignee: Infineon Technologies AG
    Inventor: Matthias Stecher
  • Patent number: 8569840
    Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen
  • Patent number: 8552532
    Abstract: Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., John J. Pekarik, Yun Shi, Yanli Zhang
  • Patent number: 8546230
    Abstract: Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, David L. Harame, Robert K. Leidy, Qizhi Liu
  • Patent number: 8530288
    Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Kunal R. Parekh
  • Patent number: 8525187
    Abstract: An IGBT, which is capable of reducing on resistance by reducing channel mobility, includes: an n type substrate made of SiC and having a main surface with an off angle of not less than 50° and not more than 65° relative to a plane orientation of {0001}; a p type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; an n type well region formed to include a second main surface of the reverse breakdown voltage holding layer; an emitter region formed in the well region to include the second main surface and including a p type impurity at a concentration higher than that of the reverse breakdown voltage holding layer; a gate oxide film formed on the reverse breakdown voltage holding layer; and a gate electrode formed on the gate oxide film. In a region including an interface between the well region and the gate oxide film, a high-concentration nitrogen region is formed to have a nitrogen concentration higher than those of the well region and the gate oxide film.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: September 3, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Keiji Wada, Toru Hiyoshi
  • Patent number: 8525300
    Abstract: The present disclosure provides an ESD protection device. The device contains a bipolar junction transistor device that includes a collector, a base, and an emitter. The collector includes a first doped element and a more heavily doped second doped element disposed over the first doped element. The first and second doped elements each have a first doping polarity. The base is located adjacent to the collector and includes a third doped element having a second doping polarity different from the first doping polarity. A p-n junction is formed between the third doped element and one of the first and second doped elements. The emitter is formed over the base. The emitter includes a fourth doped element having the first doping polarity and forming a p-n junction with the third doped element. The fourth doped element is more heavily doped than the third doped element.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: September 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Yu Kuo, Chi-Kuang Chen
  • Patent number: 8525301
    Abstract: A method for fabricating heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times, is presented. The method comprises acts for fabricating a set of extrinsic layers by depositing a highly-doped p+ layer on a substrate, depositing a masking layer on highly-doped p+ layer, patterning the masking layer with a masking opening, removing a portion of the highly-doped p+ layer and the substrate through the masking opening in the masking layer to form a well, and growing an intrinsic layered device in the well by a combination of insitu etching and epitaxial regrowth, where an intrinsic layer has a thickness selected independently from a thickness of its corresponding extrinsic layer, thus allowing the resulting device to have thick extrinsic base layer (low base resistance) and thin intrinsic base layer (short base transit times) simultaneously.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: September 3, 2013
    Assignee: HRL Laboratories, LLC
    Inventor: Tahir Hussain
  • Patent number: 8525233
    Abstract: A pnp SiGe heterojunction bipolar transistor (HBT) reduces the rate that p-type dopant atoms in the p+ emitter of the transistor out diffuse into a lowly-doped region of the base of the transistor by epitaxially growing the emitter to include a single-crystal germanium region and an overlying single-crystal silicon region.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: September 3, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 8507352
    Abstract: In a method of manufacturing a semiconductor device, a semiconductor substrate of a first conductivity type having first and second surfaces is prepared. Second conductivity type impurities for forming a collector layer are implanted to the second surface using a mask that has an opening at a portion where the collector layer will be formed. An oxide layer is formed by enhanced-oxidizing the collector layer. First conductivity type impurities for forming a first conductivity type layer are implanted to the second surface using the oxide layer as a mask. A support base is attached to the second surface and a thickness of the semiconductor substrate is reduced from the first surface. An element part including a base region, an emitter region, a plurality of trenches, a gate insulating layer, a gate electrode, and a first electrode is formed on the first surface of the semiconductor substrate.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 13, 2013
    Assignee: DENSO CORPORATION
    Inventors: Masaki Koyama, Yutaka Fukuda
  • Patent number: 8502236
    Abstract: A MOSFET, which is capable of reducing on resistance by reducing channel mobility even when a gate voltage is high, includes: an n type substrate made of SiC and having a main surface with an off angle of 50°-65° relative to a {0001} plane; an n type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; a p type well region formed in the reverse breakdown voltage holding layer distant away from a first main surface thereof; a gate oxide film formed on the well region; an n type contact region disposed between the well region and the gate oxide film; a channel region connecting the n type contact region and the reverse breakdown voltage holding layer; and a gate electrode disposed on the gate oxide film. In a region including an interface between the channel region and the gate oxide film, a high-concentration nitrogen region is formed.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: August 6, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Keiji Wada, Toru Hiyoshi
  • Patent number: 8497527
    Abstract: A device comprising a two-dimensional electron gas that includes an active region located in a portion of the electron gas is disclosed. The active region comprises an electron concentration less than an electron concentration of a set of non-active regions of the electron gas. The device includes a controlling terminal located on a first side of the active region. The device can comprise, for example, a field effect transistor (FET) in which the gate is located and used to control the carrier injection into the active region and define the boundary condition for the electric field distribution within the active region. The device can be used to generate, amplify, filter, and/or detect electromagnetic radiation of radio frequency (RF) and/or terahertz (THz) frequencies.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: July 30, 2013
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexei Koudymov, Michael Shur, Remigijus Gaska
  • Patent number: 8487408
    Abstract: A bipolar transistor of the invention has a second base region 116 which is formed in the surface layer of a deep well, placed between a first base region and a sinker, connected to the first base region, has an impurity concentration larger than that of the first base region, and has a depth shallower than that of the first base region; and a buried layer formed in a semiconductor layer, which has the top surface thereof brought into contact with the deep well and the sinker, and has an impurity concentration larger than that of the deep well.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: July 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Shinichi Komatsu