Abstract: A radio frequency electronic filter includes an input, an output, and first and second resonators coupled to the input and the output, with the first resonator including a first voltage tunable dielectric varactor and the second resonator including a second voltage tunable dielectric varactor. The resonators can include a lumped element resonator, a ceramic resonator, or a microstrip resonator. Additional voltage tunable dielectric varactors can be connected between the input and the first resonator and between the second resonator and the output. Voltage tunable dielectric varactors can also be connected between the first and second resonators.

Abstract: A varactor includes a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a metal silicide layer formed on the silicon-germanium base region, a first electrode layer formed to contact the metal silicide layer, and a second electrode layer formed to be electrically connected to the collector contact region.

Abstract: A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

Abstract: A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the gate that has gate voltages above the critical voltage has an inversion layer or conducting channel under the gate. Another portion of the gate has gate voltages below the critical voltage, and thus no channel forms. By varying either the gate voltages or the source voltage, the area of the gate that has a channel under it is varied, varying the channel-to-substrate capacitance. Separate gate arms reduce bias current.

Abstract: A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.

Abstract: A receiver for radio or television signals provided with a high-frequency circuit having a discrete semiconductor component which includes a planar variable capacitance diode and an integrated series resistor formed on a common semiconductor or substrate. The receiver has lower parasitic capacitance and improved data reception, resulting in an increase of the Q factor of the variable capacitance diode and an increase in the circuit performance. The overall circuit loss is also reduced.

Abstract: The linear tuning range of a semiconductor varactor is substantially increased by forming a lightly-doped drain region of a first conductivity type in a semiconductor material of a second conductivity type between a heavily-doped diffusion of the second conductivity type and a lower-plate region of the semiconductor material.

Abstract: A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

Abstract: An object of this invention is to provide a pn-varactor having a small resistance and capable of coinciding with incorporation of a circuit employing LC resonance into an integrated circuit. A dummy gate pattern 4 is formed over a n-well 1 in a semiconductor wafer and then p+ diffusion regions 2, 3 are formed on both sides with the dummy gate pattern 4 as inhibition mask. For the purpose, a control voltage VT higher than potentials of the p+ diffusion regions 2, 3 is applied to the n-well 1. Consequently, both the pn-junction between the n-well 1 and the p+ diffusion region 2 and the pn-junction between the n-well 1 and the p+ diffusion region 3 act as a pn-varactor whose capacity is changed by the control voltage VT. If an end dummy pattern is provided on both sides or around the p+ diffusion regions 2, 3, imbalance in capacity due to deflection in position is prevented.

Abstract: A Micro Electro-Mechanical System (MEMS) varactor (100, 200) having a bottom electrode (116) formed over a substrate (112) and a dielectric material (130) disposed over the bottom electrode (116). A pull-down electrode (122) is formed over spacer (120) and the dielectric material (130). The MEMS varactor (100, 200) is adapted to operate in a stiction mode, with at least a portion of pull-down electrode (122) in contact with dielectric material (130). The MEMS varactor (100, 200) has a high Q, large tuning range, and high sensitivity.

Abstract: An array of nanometric dimensions consisting of two or more arms, positioned side by side, wherein the arms are of such nanometric dimensions that the beams can be moved or deformed towards or away from one another by means of a low voltage applied between the beams, whereby to produce a desired optical, electronic or mechanical effect. At nanometer scale dimensions structures previously treated as rigid become flexible, and this flexibility can be engineered since it is a direct consequence of material and dimensions. Since the electrostatic force between the two arms is inversely proportional to the square of the distance, a very considerable force will be developed with a low voltage of the order of 1-5 volts, which is sufficient to deflect the elements towards or away from one another.

Abstract: A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

Abstract: A variable-capacitance device includes first and second variable-capacitance elements which are connected in parallel to each other. Each of the first and variable-capacitance elements include gate, source and drain regions and operates in response to a control voltage applied to the gate region. The first and second variable-capacitance elements have different levels of threshold values.

Abstract: In a multi-terminal MOS varactor, a floating electrode 8 of a MOS capacitor (Cf) 5 is connected to one of two terminals of each of a plurality of capacitors (C1-Cn) 6-1 through 6-n. To the other terminals (Vg1-Vgn) 9-1 through 9-n of the respective capacitors (C1-Cn) 6-1 through 6-n, control voltages Vg1-Vgn are applied, and a terminal (Vn) 11 of the MOS capacitor (Cf) 5, the terminal being on the side of a well, receives a control voltage. In the multi-terminal MOS varactor with the arrangement above, it is possible to progressively change the valid electrostatic capacity C of the other terminal (Vgj) 9-j of an arbitrary capacitor (Cj) 6-j, by changing the control voltage. Since electrostatic capacity can be progressively changed in this MOS varactor, adopting this MOS varactor to an oscillator enables to control a frequency and sensitivity of the oscillator.

Abstract: A variable capacitor and a memory device employing the same. The variable capacitor includes a first electrode formed above a substrate; a second electrode suspended with respect to the first electrode to be moved back and forth with respect to the first electrode; and an actuator for varying a capacitance. One end of the actuator is connected to the second electrode and mounted with respect to the substrate to move the second electrode with respect to the first electrode in accordance with a voltage signal input through a driving electrode exposed externally. The memory device includes a transistor having a source, a gate, and a drain formed above a substrate, which are spaced apart from each other, a capacitor connected to the source, and an actuator varying a capacitance of the capacitor.

Abstract: A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.

Abstract: The present invention concerns an integrated variable capacitance device comprising at least one membrane (12) forming at least one mobile armature and having at least one principal face facing at least one fixed armature. In accordance with the invention, the membrane has at least one rigidity rib (32) lying in a perpendicular direction to said principal face.

Abstract: A semiconductor device of a pin junction structure, constituted by a quantum-wave interference layers Q1 to Q4 with plural periods of a pair of a first layer W and a second layer B and middle layers (carrier accumulation layers) C1 to C3. The second layer B has wider band gap than the first layer W. Each thicknesses of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of wavelength of quantum-wave of carriers conducted in the i-layer in each of the first layer W and the second layer B existing at the level near the lowest energy level of the second layer B. A &dgr; layer, for sharply varying energy band, is formed at an every interface between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. Then quantum-wave interference layers and carrier accumulation layers are formed in series.

Abstract: A voltage-variable capacitor is constructed from a metal-oxide-semiconductor transistor. The transistor source has at least two contacts that are biased to different voltages. The source acts as a resistor with current flowing from an upper source contact to a lower source contact. The gate-to-source voltage varies as a function of the position along the source-gate edge. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the source has source voltages above the critical voltage and no conducting channel forms under the gate. Another portion of the source has source voltages below the critical voltage, and thus a conducting channel forms under the gate for this portion of the capacitor. By varying either the gate voltage or the source voltages, the area of the gate that has a channel under it is varied, varying the capacitance. Separate source islands eliminate source current.

Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

Abstract: A varactor includes a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a metal silicide layer formed on the silicon-germanium base region, a first electrode layer formed to contact the metal silicide layer, and a second electrode layer formed to be electrically connected to the collector contact region.

Abstract: A perovskite-containing composite material comprising a substrate, an intermediate layer of a first titanium-containing perovskite and a covering layer of a second perovskite, both the first and the second perovskites being quaternary or higher-substituted perovskites. This composite material exhibits a single-phase perovskite covering layer and, consequently, can very suitably be used for the manufacture of electronic components and modules comprising integrated passive components. A description is given of a method of manufacturing said composite material.

Abstract: A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.

Abstract: Non-aqueous electrolytic solutions suitable for anodizing valve metal derivative anodes, methods of anodizing using non-aqueous electrolytic solutions, and capacitors prepared with non-aqueous electrolytic solutions. The non-aqueous electrolytic solution comprises glycerine and at least one soluble salt formed by the neutralization of at least one non-halogen-containing organic or inorganic acid anion with at least one alkali metal, ammonium, or protonated amine cation; wherein the acid anion is derived from an acid having a pKa lower than phosphoric acid.

Abstract: An object of the present invention is to provide a ferroelectric capacitor which shows excellent ferroelectricity. A silicon oxidation layer 4, a lower electrode 12, a ferroelectric layer 8 and an upper electrode 15 are formed on a silicon substrate 2. The lower electrode 12 is made of palladium oxide. Also, the upper electrode 15 is made by palladium oxide. Since palladium oxide prevents leakage of oxygen contained in the ferroelectric layer 8. So that, a ferroelectric capacitor offers excellent ferroelectricity can be realized.

Abstract: Disclosed is an inventive diode which can reduce a stray capacity to improve various characteristics thereof, in which a dielectric layer, a conductive layer and a second dielectric layer are respectively formed by deposition in this order on an upper face of a semiconductor substrate excluding a central portion of an exposed surface of a P-type region. Then, an anode side electrode is formed extending from the exposed surface of the P-type region to the upper face of the second dielectric layer, and is electrically connected with the P-type region. Herein, the conductive layer is formed such that it is isolated from the electrode by the second dielectric layer, is connected with the semiconductor substrate upper face in a location where the dielectric layer has not been formed, and partially resides in a location sandwiched between the electrode and the semiconductor substrate.

Abstract: An integrated adjustable capacitor device and method for making such a device are provided. The adjustable capacitor includes an underlying electrode, a dielectric cavity, an upper electrode, and an etch cavity for removing sacrificial material from the dielectric cavity. The surface of the device is relatively flat due to epitaxal deposition of epi polysilicon and single crystal silicon. The adjustable capacitor system is capable of undergoing CMOS processes without requiring additional steps of covering the capacitor device to protect it and then removing the covering following the CMOS processes.

Abstract: A receiver for radio or television signals provided with a high-frequency circuit comprising a discrete semiconductor component which includes a planar variable capacitance diode formed on a semiconductor substrate of a first doping type with a first doping density n1, on which semiconductor substrate an epitaxial layer of the same doping type with a second doping density n2>n1 is provided, on which epitaxial layer an insulation layer having a first window is provided by means of a first laterally bounded semiconductor region of a second doping type with a doping density n3>n2 in the epitaxial layer below the first window, and a first contact pad which contacts the first laterally bounded semiconductor region via the first window,

Abstract: An electrically tunable device, particularly for microwaves, includes a carrier substrate, conductors, and at least one tunable ferroelectric layer. Between the conductors and the tunable ferroelectric layer, a buffer layer including a thin film structure having a non-ferroelectric material is arranged.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective SiGe epi-silicon growth technology.

Abstract: A varactor comprising a substrate, a first conductor positioned on a surface of the substrate, a second conductor positioned on the surface of the substrate forming a gap between the first and second conductors, a tunable dielectric material positioned on the surface of the substrate and within the gap, the tunable dielectric material having a top surface, with at least a portion of said top surface being positioned above the gap opposite the surface of the substrate, and a first portion of the second conductor extending along at least a portion of the top surface of the tunable dielectric material. The second conductor can overlap or not overlap a portion of the first conductor.

Abstract: The present invention relates to a thin film ferroelectric varactor device (10) comprising a substrate layer (1), a ferroelectric layer structure (12) and an electrode structure (91,92). The ferroelectric layer structure (12) comprises a number of ferroelectric layers (2,4) and a number of intermediate buffer layers (3) arranged in an alternating manner. At least a first (2) and a second (4) layer of said ferroelectric layers have different Curie temperatures, i.e. the dielectric constant of the first ferroelectric layer (12) has a maximum at a temperature which is different from the temperature at which the dielectric constant of the second ferroelectric layer (4) has a maximum.

Abstract: A multilayer ZnO polycrystalline diode that protects against electrostatic discharges, over-current, and voltage surges is provided. The polycrystalline diode includes a block having a plurality of polycrystalline layers in parallel having a first lateral side and a second lateral side. A polycrystalline system is formed by a network of the ZnO diodes. Each diode further includes a plurality of inner electrodes, wherein each inner electrode includes metal and is placed among the plurality of parallel polycrystalline layers, and wherein one end of each inner electrode is placed to alternately terminate at one of the first lateral side and the second lateral side of the block, and wherein the remainder of each inner electrode is surrounded by the parallel polycrystalline layers. A pair of outer electrodes, each including metal and covering each of the first lateral side and the second lateral side of the block are also provided.

Abstract: A method of fabricating a semiconductor device comprises the steps of: (a) forming a mask layer over an upper surface of a semiconductor substrate such that the mask layer has an aperture penetrating the mask layer and having an inclined lateral wall so as to make the aperture inverted taper shaped; (b) forming a first dielectric layer at a first area over the upper surface of the semiconductor substrate within the aperture by sputtering at a first sputtering incidence direction; and (c) forming a first electrode layer at a second area over the upper surface of the semiconductor substrate within the aperture by sputtering at a second sputtering incidence direction which is different from the first sputtering incidence direction.

Abstract: A voltage variable capacitor includes a supporting substrate with a doped layer, an insulating layer positioned on the doped layer, and first, second, and third conductive segments positioned on the insulating layer parallel to the doped layer and spaced from the doped layer by the insulating layer so as to define first, second, and third capacitors. The first, second, and third conductive segments serve as external contacts and the opposed terminals of the first, second, and third capacitors are coupled together through the doped layer. In a preferred embodiment, the substrate is a semiconductor wafer and the doped layer is epitaxially grown. The insulating layer is a high dielectric constant material, such as zirconium titanate or material with a similar dielectric constant and the segments are gold.

Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or “binary” varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value.

Abstract: The method of obtaining the adjustable capacitor permits transforming all types of capacitors (including Electrolytic, Vacuum, Gas, high-voltage capacitors) into adjustable capacitors without moving parts inside capacitors and provides broad ranges of changing the capacity of adjustable capacitors in electric circuits of direct and alternating current and in all types of Marx Generators.

Abstract: A passivation layer is formed by coating a flowable insulating material on the substrate where a thin film transistor and a storage capacitor electrode, and a pixel electrode is formed on the passivation layer. A portion of the passivation layer is etched using the pixel electrode as a mask to make a groove on the thin film transistor, and then a black matrix is formed by filling an organic black photoresist in the groove. To increase the storage capacitance, a portion of the passivation layer is removed or to form a metal pattern on the storage capacitor electrode. A flowable insulating material is used as a gate insulating layer to planarize the substrate. In the case of the etch stopper type thin film transistor, a photo definable material is used as the etch stopper layer to reduce the parasitic capacitance between the gate electrode and the drain electrode.

Abstract: The invention discloses a variable capacitor including a first storage electrode, a second storage electrode, and a variable length means coupled therebetween. The capacitance can be adjusted by varying a dielectric space therebetween according with an electrical input. The method for manufacturing a variable capacitor in an integrated circuit includes the steps of forming a first storage electrode, a first dielectric layer, a second dielectric layer, a pair of contact channels, and a second sacrificial layer. The method further includes forming a third sacrificial layer, a second storage electrode, a resistor pattern, a passivation layer, and etching the third, the second, and the first sacrificial layer for having a dielectric space between the first storage electrode and the second storage electrode.

Abstract: A voltage variable capacitor (10) fabricated on a semiconductor substrate (11) includes a gate structure (62) and a well (22) under the gate structure (62). A heavily doped buried layer (15) and a heavily doped contact region (31) in the semiconductor substrate (11) form a low resistance conduction path from the well (22) to a surface (17) of the semiconductor substrate (11). A multi-finger layout is used to construct the voltage variable capacitor (10). In operation, when a voltage applied across the voltage variable capacitor (10) changes, the width of depletion region in the well (22) changes, and the capacitance of the voltage variable capacitor (10) varies accordingly.

Abstract: A tunable capacitor includes a first capacitor formed from semiconductor material and having a first terminal defining an anode, and a second capacitor integrally formed with the first capacitor from semiconductor material, the second capacitor being operatively coupled in series with the first capacitor, and having a second terminal defining a cathode. The second capacitor is formed as a field effect device or MOSFET configured to provide a depletion region controlled by applying a control voltage to a control terminal of the field effect device. The first capacitor is reverse biased by application of a reverse bias voltage between the anode and the cathode to provide a predetermined capacitance while the control voltage applied to the control terminal of the second capacitor varies the depletion region such that the capacitance of second capacitor is varied independently of the reverse bias voltage.

Abstract: A method of fabricating a semiconductor device comprises the steps of: (a) forming a mask layer over an upper surface of a semiconductor substrate such that the mask layer has an aperture penetrating the mask layer and having an inclined lateral wall so as to make the aperture inverted taper shaped; (b) forming a first dielectric layer at a first area over the upper surface of the semiconductor substrate within the aperture by sputtering at a first sputtering incidence direction; and (c) forming a first electrode layer at a second area over the upper surface of the semiconductor substrate within the aperture by sputtering at a second sputtering incidence direction which is different from the first sputtering incidence direction.

Abstract: The method of fabricating a liquid crystal display device forms a first and second gate electrode on a first and second region, respectively, of a substrate. The first and second gate electrodes each include a non-anodizing metallic layer and at least one anodizing metallic layer. The two metallic layers also have different etching selection ratios. A first insulating layer is formed on the anodizing metallic layer of the first and second gate electrodes, and at least a second insulating layer is formed over the substrate. A thin film transistor structure, which utilizes the first gate electrode as a gate, is formed on the second insulating layer.

Abstract: A voltage variable capacitor (VVC) is made by placing an intercalation compound between two electrodes of a capacitor. The VVC has a reservoir of an intercalant in proximity with the intercalation compound. The two materials are chosen from those known to exhibit the intercalation reaction. The extent of the intercalation reaction is controlled by applying a voltage to the intercalant reservoir and the intercalation compound. A variable capacitor is created by applying a signal to the device and appropriately controlling the .di-elect cons. of the device by using the input control voltages.

Abstract: An area-variable varactor diode is disclosed, in which the capacitance can be arbitrarily varied under an applied bias voltage. The area-variable varactor diode is characterized in that, in order to ensure freedom to designing the epi-layer, to obtain the desired capacitance characteristics, and to facilitate the integration with other elements, a steeply varied depletion layer area is provided through a variation of the surface layout area, and thus, varied capacitance characteristics are obtained. In steeply varying the area of the depletion layer, an etching of the active layer, a selective epi-layer growth, and an ion implantation are carried out or a combination of them is carried out. The capacitance characteristics are varied in accordance with the pattern of the mask, and therefore, a restriction is not imposed on the epi-layer, with the result that an integration with other elements becomes easy.

Abstract: A semiconductor memory is provided wherein two bits of binary information are stored simultaneously in a ferroelectric capacitor by utilizing the positive and negative polarization states of the ferroelectric capacitor for storing a first of the two bits of binary information and by utilizing the capacitive characteristic of the ferroelectric capacitor to simultaneously store a second of the two bits of binary information without altering the polarization of the ferroelectric capacitor. When reading information from the ferroelectric capacitor, the second of the two bits of information is read out first and transferred to a buffer cell, then the first of the two bits of binary information is read and re-written, as desired, and the second of the two bits of information is returned from the buffer cell to the ferroelectric capacitor.

Abstract: A voltage-variable ceramic capacitance device which has a plurality of las in a matching lattice structure and which possesses a symmetric voltage characteristic and a determinable voltage breakdown and has a high resistance to overbiasing or reverse biasing from an applied voltage. The device consists of a carrier substrate layer, a high temperature superconducting metallic layer deposited on the substrate, a thin film ferroelectric deposited on the metallic layer, and a plurality of metallic conductive means disposed on the thin film ferroelectric which are placed in electrical contact with RF transmission lines in tuning devices.

Abstract: A doping profile is disclosed for realizing a varactor diode that exhibits a high breakdown voltage V.sub.BR, e.g.,>100 volts, and a capacitance which has a bi-level characteristic. In particular, the capacitance has a C.sub.max level and a C.sub.min level. The doping profile includes two lightly doped regions and, between them, a third region with higher doping. The doping concentrations and widths of the first two regions substantially set the tuning ratio of C.sub.max /C.sub.min, and the doping concentration and width of the third region substantially sets the transition voltage V.sub.TR between the bi-level capacitances.

Abstract: A lower electrode, a first inorganic insulating film of SiN, and an organic insulating film of polyimide are formed on a GaAs substrate serving as an underlie, in this order. The organic insulating film is selectively etched to form a capacitor opening. A second norganic insulating film covering the surface of the organic insulating film and the bottom and side wall of the capacitor opening, and an upper electrode are formed. As the selective etching of the organic insulating film, wet etching may be used for simplifying manufacturing processes. Alternatively, dry etching may be used for improving etching accuracy. The organic insulating film 4 may be formed by a multi-layer film so that a circuit can be formed across multi-layers, improving the degree of integration.

Abstract: An active matrix liquid crystal display apparatus comprises first and second substrates facing each other through a liquid crystal layer. The first substrate has a plurality of scan bus lines, thin film transistors, display electrodes, and reference potential supplying bus lines, and the second substrate has a plurality of stripe-like data bus lines that face the display electrodes. The display electrode has a compensation capacitor for compensating a potential fluctuation occurring in the display electrode after a gate electrode of the thin film transistor is selected. The capacitance of the compensation capacitor is larger during a compensation period than during a storage period in which the gate electrode of the corresponding thin film transistor is not selected.