Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.

Abstract: A method is disclosed for manufacturing a semiconductor device. The method includes providing a substrate and forming a well region in the substrate by an ion implantation. The method also includes forming, by rapid thermal oxidation and on the substrate having the well region, an oxide layer for repairing the substrate damaged by the ion implantation. Further, the method includes removing the oxide layer and forming a gate oxide layer on the repaired substrate having the well region.

Abstract: Provided are a semiconductor device which can shorten reverse recovery time without increasing leakage current between the drain and the source, and a fabrication method for such semiconductor device.

Abstract: The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.

Abstract: Described herein are semiconductor devices with a threshold voltage (Vt) adjusted through back gate stack engineering to meet performance and power requirements and corresponding back gate stack engineering methods. The semiconductor devices can include a thin SOI region, a thin BOX region and a semiconductor substrate. The threshold voltage can be adjusted in the backside of the semiconductor device through implantation of one or more dopants into the BOX region such that the peak concentration of the one or more dopants is inside the BOX region.

Abstract: The invention relates to a process for producing p-doped silicon layers, especially those silicon layers which are produced from liquid silane-containing formulations. The invention further relates to a substrate coated with a p-doped silicon layer. The invention additionally relates to the use of particular dopants based on boron compounds for p-doping of a silicon layer.

Abstract: Silicon single crystal substrates having uniform resistance, few BMDs in a surface layer and a moderate number of BMDs in a center of thickness of the substrate are formed from Czochralski silicon single crystals. The substrates have a resistivity in the center of a first main surface not lower than 50 ?·cm and a rate of change in resistivity in the first main surface not higher than 3%, an average density of bulk micro defects in a region between the first main surface and a plane at a depth of 50 ?m of less than 1×108/cm3, and an average density of bulk micro defects in a region lying between a plane at a depth of 300 ?m and a plane at a depth of 400 ?m from the first main surface not lower than 1×108 /cm3 and not higher than 1×109 /cm3.

Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.

Abstract: An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5×1019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.

Abstract: A semiconductor device manufacturing method includes exciting plasma, applying RF power onto a target substrate to generate substrate bias and performing an ion implantation plural times by applying the RF power in the form of pulses.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: The present invention relates to a method for preparing, on a silicon wafer, an n+pp+ or p+nn+ structure which includes the following consecutive steps: a) on a p or n silicon wafer (1), which includes a front surface (8) and a rear surface (9), a layer of boron-doped silicon oxide (BSG) (2) is formed on the rear surface (9) by PECVD, followed by a SiOx diffusion barrier (3); b) a source of phosphorus is diffused such that the phosphorus and the boron co-diffuse and in order also to form: on the front surface (8) of the wafer obtained at the end of step a), a layer of phosphorus-doped silicon oxide (PSG) (4) and an n+ doped area (5); and on the rear surface of the wafer obtained at the end of step a), a boron-rich area (BRL) (6), as well as a p+ doped area (7); c) the layers of BSG (2) and PSG (4) oxides and SiOx (3) are removed, the BRL (6) is oxidised and the layer resulting from said oxidation is removed.

Abstract: A process for the formation of at least one aluminum p-doped surface region of an n-type semiconductor substrate comprising the steps: (1) providing an n-type semiconductor substrate, (2) applying and drying an aluminum paste on at least one surface area of the n-type semiconductor substrate, (3) firing the dried aluminum paste, and (4) removing the fired aluminum paste with water, wherein the aluminum paste employed in step (2) includes particulate aluminum, an organic vehicle and 3 to 20 wt. % of glass frit, based on total aluminum paste composition.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: Silicon wafers having a resistivity >6 ?cm and axially uniform resistivity are grown by the Czochralski method from a melt containing boron as the main dopant, an n-type first sub-dopant with a segregation coefficient lower than boron, and a p-type second sub-dopant with a segregation coefficient lower than the first sub-dopant.

Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

Abstract: A coating fluid comprising a boron compound, an organic binder, a silicon compound, an alumina precursor, and water and/or an organic solvent is used to diffuse boron into a silicon substrate to form a p-type diffusion layer. The coating fluid is spin coated onto the substrate to form a uniform coating having a sufficient amount of impurity whereupon a p-type diffusion layer having in-plane uniformity is formed.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming a dielectric film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin; and forming a retrograde doped well structure on the inner walls of the first semiconductor fin and the second semiconductor fin, wherein the inner walls thereof are opposite to each other. Correspondingly, the present invention further provides a semiconductor structure.

Abstract: Disclosed is a phosphorus paste for diffusion that is used in continuous printing of a phosphorus paste for diffusion on a substrate by screen printing. The phosphorus paste for diffusion does not undergo a significant influence of ambient humidity on viscosity and has no possibility of thickening even after a large number of times of continuous printing. The phosphorus paste for diffusion is coated on a substrate by screen printing for diffusion layer formation on the substrate. The phosphorus paste for diffusion includes a doping agent containing phosphorus as a dopant for the diffusion layer, a thixotropic agent containing an organic binder and a solid matter, and an organic solvent. The doping agent is an organic phosphorus compound.

Abstract: A method of fabricating a semiconductor device having reduced plasma-induced damage includes providing a p-type semiconductor substrate. The p-type semiconductor substrate has a front surface including the semiconductor device and a back surface. The method further includes doping the back surface with an n-type dopant to form an n-type semiconductor region before forming metal interconnections on the front surface. The n-type semiconductor region and the p-type semiconductor substrate form a pn junction. The method also includes forming an insulation layer on an exposed surface of the n-type semiconductor region.

Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device. In the method, a substrate portion and a fin portion on the substrate portion are formed. A first silicon oxide film is formed on each side surface of the fin portion. A polysilazane film having an upper surface lower than the upper surface of the first silicon oxide film is formed on each side surface of the first silicon oxide film. The polysilazane film is converted into a silicon oxynitride film. The first silicon oxide film is etched to make the upper surface of the first silicon oxide film not higher than the upper surface of the silicon oxynitride film. A heavily doped semiconductor layer is formed in the fin portion.

Abstract: According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.

Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming the first transistor in the pixel area and the second transistor in the logic area includes performing a first implant process in the pixel area and the logic area, performing a second implant process in the pixel area and the logic area, and performing a third implant process only in the logic area.

Abstract: The embodiments of methods of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate described above enable reducing cross-talk (or blooming) of neighboring. The methods use an oxide implant mask to form a deep doped region and also to form a shallow doped region. In some embodiments, the shallow doped regions are narrower and are formed by depositing a conformal dielectric layer over the oxide implant mask to narrow the openings for implantation.

Abstract: The semiconductor substrate of the present invention contains a semiconductor layer and an impurity diffusion layer containing at least one impurity atom selected from the group consisting of an n-type impurity atom and a p-type impurity atom and at least one metallic atom selected from the group consisting of K, Na, Li, Ba, Sr, Ca, Mg, Be, Zn, Pb, Cd, V, Sn, Zr, Mo, La, Nb, Ta, Y, Ti, Ge, Te, and Lu.

Abstract: Embodiments of the invention include a III-nitride semiconductor layer including a first portion having a first defect density and a second portion having a second defect density. The first defect density is greater than the second defect density. An insulating material is disposed over the first portion. The insulating material is not formed on or is removed from the second portion.

Abstract: Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

Abstract: Methods of forming and tuning a multilayer select device are provided, along with apparatus and systems which include them. As is broadly disclosed in the specification, one such method can include forming a first region having a first conductivity type; forming a second region having a second conductivity type and located adjacent to the first region; and forming a third region having the first conductivity type and located adjacent to the second region and, such that the first, second and third regions form a structure located between a first electrode and a second electrode, wherein each of the regions have a thickness configured to achieve a current density in a range from about 1×e4 amps/cm2 up to about 1×e8 amps/cm2 when a voltage in a selected voltage range is applied between the first electrode and the second electrode.

Abstract: A method for controlling the morphology of deposited silicon on a layer of silicon dioxide and semiconductor devices incorporating such deposited silicon are provided. The method comprises the steps of: providing a layer of silicon dioxide; implanting hydrogen ions into the layer of silicon dioxide by plasma source ion implantation; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.

Abstract: A power semiconductor device and a manufacturing method thereof are provided. The method of manufacturing a power semiconductor device includes the steps: (a) forming a cell structure on a first conductivity type semiconductor substrate; (b) implanting second conductivity type ions onto the rear surface of the first conductivity type semiconductor substrate and activating to form an electrode region; and (c) implanting ions creating first conductivity type with a doping concentration higher than that of the semiconductor substrate and activating to form a high-concentration ion implanted region at a position below the cell structure and on the electrode region. Accordingly, it is possible to form a field stop layer regardless of conditions for forming an electrode region (for example, a P-type collector region) and thus to optimize stable breakdown voltage characteristics and device characteristics.

Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.

Abstract: A unipolar diode with low turn-on voltage includes a subcathode semiconductor layer, a low-doped, wide bandgap cathode semiconductor layer, and a high-doped, narrow bandgap anode semiconductor layer. A junction between the cathode layer and the anode layer creates an electron barrier in the conduction band, with the barrier configured to produce a low turn-on voltage for the diode. A unipolar diode with low turn-on voltage includes an n+ subcathode semiconductor layer, a low-doped, wide bandgap cathode semiconductor layer, and an n+ narrow bandgap anode semiconductor layer. Again, a junction between the cathode layer and the anode layer creates an electron barrier in the conduction band, with the barrier configured to produce a low turn-on voltage for the diode.

Abstract: An object of the present invention is to provide an epitaxial wafer on which dislocation is preventable even when a LSA treatment is performed in device processes. An epitaxial wafer according to the present invention includes a wafer 11 whose nitrogen concentration is 1×1012 atoms/cm3 or more or whose specific resistance is 20 m?·cm or less by boron doping, and an epitaxial layer 12 provided on the wafer 11. On the wafer 11, if a thermal treatment is performed at 750° C. for 4 hours and then at 1,000° C. for 4 hours, polyhedron oxygen precipitates grow predominantly over plate-like oxygen precipitates. Therefore, in the device processes, plate-like oxygen precipitates cannot be easily formed. As a result, even when the LSA treatment is performed after various thermal histories in the device processes, it is possible to prevent the dislocation, which is triggered by oxygen precipitates, from generating.

Abstract: A SiC semiconductor substrate is disclosed which includes a SiC single crystal substrate, a nitrogen (N)-doped n-type SiC epitaxial layer in which nitrogen (N) is doped and a phosphorus (P)-doped n-type SiC epitaxial layer in which phosphorus (P) is doped. The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are laminated on the silicon carbide single crystal substrate sequentially. The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are formed by using two or more different dopants, for example, nitrogen and phosphorus, at the time of epitaxial growth. Basal plane dislocations in a SiC device can be reduced.

Abstract: Provided is a silicon wafer which is stabilized in quality exerting no adverse influence on device characteristics and manufactured by restricting a boron contamination from the environment, and a manufacturing process therefor. Concretely, the silicon wafer is characterized by an attached boron amount thereon being 1×1010 atoms/cm2 or less. In order to manufacture such a wafer as contains a small amount of boron attached on the wafer surface, the wafer is treated in an atmosphere of boron concentration of 15 ng/m3 or less. Boron-less filters and boron adsorbing filters are used as filters in a clean room and the like so as to lower the boron concentration in the atmosphere.

Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

Abstract: A MOSFET includes a silicon carbide substrate, a buffer layer made of silicon carbide formed on the silicon carbide substrate, a drift layer made of silicon carbide of an n conductivity type formed on the buffer layer, a p type body region of a p conductivity type formed in the drift layer to include a main surface of the drift layer opposite to the buffer layer, a source contact electrode formed on the p type body region, and a drain electrode formed on a main surface of the silicon carbide substrate opposite to the buffer layer. A current path region having an impurity concentration higher than that of another region in the drift layer is formed in a region in the drift layer sandwiched between the buffer layer and the body region.

Abstract: Methods of forming and tuning a multilayer select device are provided, along with apparatus and systems which include them. As is broadly disclosed in the specification, one such method can include forming a first region having a first conductivity type; forming a second region having a second conductivity type and located adjacent to the first region; and forming a third region having the first conductivity type and located adjacent to the second region and, such that the first, second and third regions form a structure located between a first electrode and a second electrode, wherein each of the regions have a thickness configured to achieve a current density in a range from about 1×e4 amps/cm2 up to about 1×e8 amps/cm2 when a voltage in a selected voltage range is applied between the first electrode and the second electrode.

Abstract: Various methods and apparatuses involving salt-based compounds and related doping are provided. In accordance with one or more embodiments, a salt-based material is introduced to a semiconductor material, is heated to generate a neutral compound that dopes the semiconductor material. Other embodiments are directed to semiconductor materials with such a neutral compound as an impurity that affects electrical characteristics therein.

Abstract: An undoped semiconductor substrate is doped by applying stress at a side of the undoped semiconductor substrate to release self interstitials in the substrate and implanting chalcogen atoms into the side of the substrate. The substrate is annealed to form a first semiconductor region containing the chalcogen atoms and a second semiconductor region devoid of the chalcogen atoms. The first semiconductor region has a doping concentration higher than the doping concentration of the second semiconductor region. The indiffusion of chalcogen atoms into a semiconductor material in the presence of self interstitials can also be used to form field stop regions in power semiconductor devices.

Abstract: Systems and methods for preparing films comprising metal using sequential ion implantation, and films formed using same, are provided herein. A structure prepared using ion implantation may include a substrate; an embedded structure having pre-selected characteristics; and a film within or adjacent to the embedded structure. The film comprises a metal having a perturbed arrangement arising from the presence of the embedded structure. The perturbed arrangement may include metal ions that coalesce into a substantially continuous, electrically conductive metal layer, or that undergo covalent bonding, whereas in the absence of the embedded structure the metal ions instead may be free to diffuse through the substrate. The embedded structure may control the diffusion of the metal through the substrate and/or the reaction of the metal within the substrate.

Abstract: A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.

Abstract: A device and method for semiconductor fabrication includes forming a buffer layer on a semiconductor substrate and depositing an amorphous elemental layer on the buffer layer. Elements of the elemental layer are diffused through the buffer layer and into the semiconductor layer.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a semiconductor fin located on the semiconductor substrate, and an etch stop layer located between the semiconductor substrate and the semiconductor fin, wherein a lateral sidewall of the semiconductor fin is substantially on the Si {111} crystal plane. Since the semiconductor fin exhibits better surface quality and less crystal defects, it is favorable for manufacturing FINFET.

Abstract: The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.

Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. The device further includes at least one of dopant initiators or dopants localized at an interface between i) the first electrode and the active region, or ii) the second electrode and the active region, or iii) the active region and each of the first and second electrodes.

Abstract: It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration to execute a baking treatment. After a surface layer of the silicon crystal substrate is then polished up to a predetermined amount, a silicon epitaxial layer is grown by a CVD method. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced.

Abstract: A support ring for supporting a monocrystalline silicon semiconductor wafer during a thermal treatment of the semiconductor wafer has outer and inner lateral surfaces and a curved surface extending from the outer lateral surface to the inner lateral surface, this curved surface serving for the placement of the semiconductor wafer. The curved surface has a radius of curvature of not less than 6000 mm and not more than 9000 mm for 300 mm diameter wafers, or a radius of curvature of not less than 9000 mm and not more than 14,000 mm for 450 mm diameter wafers. Use of the support ring during thermal treatment reduces slip and improves wafer nanotopography.

Abstract: A solar cell include a polycrystalline semiconductor substrate of a p-type, an emitter region of an n-type and forming a p-n junction with the polycrystalline semiconductor substrate, a first electrode connected to the emitter region, and a second electrode connected to the polycrystalline semiconductor substrate, wherein the polycrystalline semiconductor substrate has a pure p-type impurity concentration of substantially 7.2×1015/cm3 to 3.5×1016/cm3.

Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.