With Specified Dopant (e.g., Plural Dopants Of Same Conductivity In Same Region) Patents (Class 257/607)
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Patent number: 7361970Abstract: A method for the production of a stop zone in a doped zone of a semiconductor body having a first side and a second side, comprises the following method steps: applying a mask having cutouts to one of the sides of the semiconductor body, irradiating the side having the mask with proton radiation, carrying out a heat treatment method in order to produce hydrogen-induced donors in the semiconductor body.Type: GrantFiled: March 18, 2005Date of Patent: April 22, 2008Assignee: Infineon Technologies AGInventors: Reiner Barthelmess, Anton Mauder, Franz-Josef Niedernostheide, Hans-Joachim Schulze
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Patent number: 7344963Abstract: A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.Type: GrantFiled: April 20, 2006Date of Patent: March 18, 2008Assignee: United Microelectronics Corp.Inventors: Hsien-Chang Chang, Chia-Hsin Hou, Tsu-Yu Chu, Ko-Ting Chen
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Patent number: 7345355Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.Type: GrantFiled: September 15, 2004Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventors: Amitabh Jain, Stephanie W. Butler
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Publication number: 20080020541Abstract: A bonded SOI wafer is manufactured by performing bonding in a state where organics exist on a surface of an active layer wafer and/or on a surface of a supporting wafer and performing heat-treating for bonding reinforcement in a state where the organics are trapped at an interface between the active layer wafer and the supporting wafer to form crystal defects at an interface between the active layer wafer and an oxide film and/or at an interface between the supporting wafer and the oxide film. This allows a simple and inexpensive gettering source to be formed at the interface between an SOI layer and an insulating layer (oxide film). Also, the bonded SOI wafer of the present invention that is manufactured by this method can effectively remove heavy-metal impurities that may have a negative impact on the characteristics of the device and/or the withstand voltage characteristics of the oxide film.Type: ApplicationFiled: July 23, 2007Publication date: January 24, 2008Inventors: Yasunobu Ikeda, Shinichi Tomita, Hiroyuki Miyahara
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Publication number: 20080020556Abstract: Provided is a method for fabricating a semiconductor device. In the method, a poly layer on a semiconductor substrate is etched to a predetermined depth. Ions are implanted into the poly layer at a predetermined angle. The poly layer is etched again to expose a portion of the semiconductor substrate. Therefore, stress is applied to the poly gate instead of the barrier layer, so that the barrier layer is not opened during contact etching because effects of the barrier layer thickness can be solved. Also, stress is applied to a poly gate directly contacting a channel region of the semiconductor substrate to allow tensile force caused by the stress of the poly gate to directly induce tensile force to the channel region, and thus increase mobility, so that device characteristics can be remarkably enhanced.Type: ApplicationFiled: July 13, 2007Publication date: January 24, 2008Inventor: Jin Ha Park
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Publication number: 20080001258Abstract: According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.Type: ApplicationFiled: October 30, 2006Publication date: January 3, 2008Applicant: FUJITSU LIMITEDInventors: Taiji Ema, Masayoshi Asano, Toru Anezaki, Junichi Ariyoshi
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Patent number: 7301221Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.Type: GrantFiled: August 31, 2005Date of Patent: November 27, 2007Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Jerome M. Eldridge
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Patent number: 7297617Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.Type: GrantFiled: April 22, 2003Date of Patent: November 20, 2007Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Jerome M. Eldridge
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Patent number: 7297994Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.Type: GrantFiled: March 4, 2005Date of Patent: November 20, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Karsten Wieczorek, Manfred Horstmann, Rolf Stephan
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Patent number: 7294883Abstract: In a nonvolatile memory cell (110), the select gate transistor is formed as a buried channel transistor to increase the transistor current.Type: GrantFiled: June 30, 2005Date of Patent: November 13, 2007Assignee: ProMOS Technologies, Inc.Inventor: Yi Ding
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Patent number: 7221037Abstract: The present invention provides a method of manufacturing a Group III nitride substrate that has less variations in in-plane carrier concentration and includes crystals grown at a high growth rate.Type: GrantFiled: January 15, 2004Date of Patent: May 22, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi, Akihiko Ishibashi
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Patent number: 7202146Abstract: A process for producing doped semiconductor wafers from silicon, which contain an electrically active dopant, such as boron, phosphorus, arsenic or antimony, optionally are additionally doped with germanium and have a defined thermal conductivity, involves producing a single crystal from silicon and processing further to form semiconductor wafers, the thermal conductivity being established by selecting a concentration of the electrically active dopant and optionally a concentration of germanium. Semiconductor wafers produced from silicon by the process have specific properties with regard to thermal conductivity and resistivity.Type: GrantFiled: August 9, 2005Date of Patent: April 10, 2007Assignee: Siltronic AGInventors: Rupert Krautbauer, Christoph Frey, Simon Zitzelsberger, Lothar Lehmann
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Patent number: 7193294Abstract: A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond energy to oxygen is higher than that to silicon, and a semiconductor layer (an SOI layer) 3 provided on the embedded insulating film 2.Type: GrantFiled: December 3, 2004Date of Patent: March 20, 2007Assignee: Toshiba Ceramics Co., Ltd.Inventors: Reiko Yoshimura, Tsukasa Tada, Koji Izunome, Kazuhiko Kashima
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Patent number: 7187057Abstract: Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.Type: GrantFiled: August 13, 2004Date of Patent: March 6, 2007Assignee: Intel CorporationInventors: Cory E. Weber, Mark Armstrong, Harold Kennel, Tahir Ghani, Paul A. Packan, Scott Thompson
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Patent number: 7081664Abstract: The invention provides a doped semiconductor powder comprising nanocrystals of a group IV semiconductor and a rare earth element, the rare earth element being dispersed on the surface of the group IV semiconductor nanocrystals. The invention also provides processes for the preparation of the above doped semiconductor powder, and a composite material comprising a matrix in which is dispersed a doped semiconductor powder.Type: GrantFiled: January 22, 2004Date of Patent: July 25, 2006Assignee: Group IV Semiconductor Inc.Inventor: Steven E. Hill
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Patent number: 7045876Abstract: A method for fabricating a polysilicon emitter bipolar transistor employs a pair of ion implant methods. A first of the ion implant methods implants a portion of an intrinsic base region interposed between an extrinsic base region and a polysilicon emitter layer with an amorphizing non-active dopant. A second of the ion implant methods implants the polysilicon emitter layer with an active dopant to form a doped polysilicon emitter layer. The polysilicon emitter bipolar transistor is fabricated with enhanced performance.Type: GrantFiled: April 28, 2004Date of Patent: May 16, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng-Yuan An, Huan-Wen Wang
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Patent number: 7042163Abstract: An organic electroluminescence display includes a substrate and a plurality of light emitting parts formed on the substrate, each of the light emitting parts including an organic electroluminescence device and an organic thin film transistor connected to the organic electroluminescence device. The organic electroluminescence device has a pair of opposed electrodes and an organic material layer including an organic light-emitting layer laminated between the pair of electrodes. The organic thin film transistor has a source electrode and a drain electrode opposed to each other, an organic semiconductor film laminated so as to form a channel between the source electrode and the drain electrode, and a gate electrode for applying a field to the organic semiconductor film between the source electrode and the drain electrode.Type: GrantFiled: September 5, 2003Date of Patent: May 9, 2006Assignee: Pioneer CorporationInventor: Kenichi Nagayama
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Patent number: 7038297Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range ?40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.Type: GrantFiled: January 21, 2004Date of Patent: May 2, 2006Assignee: Winbond Electronics CorporationInventors: Paul Vande Voorde, Chun-Mai Liu
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Patent number: 7030464Abstract: A technology of restraining junction leakage in a semiconductor device is to be provided. There is provided a semiconductor device provided with a semiconductor substrate, a gate electrode 9 formed on the semiconductor substrate, and a source/drain region formed beside the gate electrode, wherein the source/drain region 4 comprises a first impurity diffusion region including a first P-type impurity and located in the proximity of a surface of the semiconductor substrate, and a second P-type impurity diffusion region located below the first impurity diffusion region and including a second P-type impurity having a smaller diffusion coefficient in the semiconductor substrate than the first P-type impurity.Type: GrantFiled: March 3, 2004Date of Patent: April 18, 2006Assignee: NEC Electronics CorporationInventors: Yuri Masuoka, Naohiko Kimizuka
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Patent number: 7023072Abstract: In a bipolar transistor including a base layer made of SiGe, a non-doped SiGe layer and a non-doped Si layer are provided between the base layer and an emitter layer. The composition ratio of Ge in the emitter side of SiGe base layer is decreased with increasing proximity to the emitter side, and the composition ratio of Ge in the non-doped SiGe layer is made smaller than the composition ratio of Ge at the emitter layer-side end of the SiGe base layer. In this manner, restriction is put on the diffusion of boron from the base layer to the emitter side, and the base-emitter junction capacitance CBE reduced. Furthermore, the direct-current gain ? can be improved by increasing the composition of Ge at the emitter end of the SiGe base layer to more than or equal to a predetermined value.Type: GrantFiled: March 7, 2002Date of Patent: April 4, 2006Assignee: NEC CorporationInventor: Noriaki Matsuno
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Patent number: 6995452Abstract: Provided are an SOI MOSFET device with a nanoscale channel that has a source/drain region including a shallow extension region and a deep junction region formed by solid-phase diffusion and a method of manufacturing the SOI MOSFET device. In the method of manufacturing the MOSFET device, the shallow extension region and the deep junction region that form the source/drain region are formed at the same time using first and second silicon oxide films doped with different impurities. The effective channel length of the device can be scaled down by adjusting the thickness and etching rate of the second silicon oxide film doped with the second impurity. The source/drain region is formed on the substrate before the formation of a gate electrode, thereby easily controlling impurity distribution in the channel. An impurity activation process of the source/drain region can be omitted, thereby preventing a change in a threshold voltage of the device. A solid-phase impurity is diffused.Type: GrantFiled: December 30, 2003Date of Patent: February 7, 2006Assignee: Electronics and Telecommunications Research InstituteInventors: Wonju Cho, Seong Jae Lee, Jong Heon Yang, Jihun Oh, Kiju Im
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Patent number: 6963081Abstract: In an embodiment of the invention, an electronic device includes an interfacial layer with traps. This interfacial layer is between an electrode and an organic layer, and if the electrode was adjacent to the organic layer, the energy barrier between these two layers is such that the current through the organic layer is limited by charge injection into this layer rather than the transport properties of the organic layer. The traps are used to accumulate charges of one charge type (e.g., either electrons or holes) within the interfacial layer. By accumulating charges, the bands of the interfacial layer are bent so that charges can tunnel from the electrode to the organic layer thus increasing the efficiency of the electronic device and allowing organic layers to be used within an electronic device that otherwise would be too inefficient for use in that device.Type: GrantFiled: September 30, 2003Date of Patent: November 8, 2005Assignee: Osram Otpo Semiconductors GmbHInventors: Rahul Gupta, Florian Pschenitzka, Vi-En Choong, Pierre-Marc Allemand
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Patent number: 6930362Abstract: A calcium doped polysilicon gate electrodes for PMOS containing semiconductor devices. The calcium doped PMOS gate electrodes reduce migration of the boron dopant out of the gate electrode, through the gate dielectric and into the substrate thereby reducing the boron penetration problem increasingly encountered with smaller device size regimes and their thinner gate dielectrics. Calcium doping of the gate electrode may be achieved by a variety of techniques. It is further believed that the calcium doping may improve the boron dopant activation in the gate electrode, thereby further improving performance.Type: GrantFiled: October 30, 2003Date of Patent: August 16, 2005Assignee: LSI Logic CorporationInventors: Mohammad R. Mirabedini, Grace S. Sun, Sheldon Aronowitz
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Patent number: 6911706Abstract: By providing a high dose germanium implant and then forming a P-type source/drain extension, a strained source/drain junction may be formed. The strained source/drain junction may be shallower and have lower resistivity in some embodiments.Type: GrantFiled: August 20, 2003Date of Patent: June 28, 2005Assignee: Intel CorporationInventors: Jack Hwang, Craig Andyke, Mitchell Taylor
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Patent number: 6888204Abstract: Described are preferred processes for conditioning semiconductor devices with deuterium to improve operating characteristics and decrease depassivation which occurs during the course of device operation. Also described are semiconductor devices which can be prepared by such processes.Type: GrantFiled: September 25, 1998Date of Patent: May 3, 2005Assignee: The Board of Trustees of the University of IllinoisInventors: Joseph W. Lyding, Karl Hess
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Patent number: 6878579Abstract: An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.Type: GrantFiled: August 13, 2004Date of Patent: April 12, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Ohuchi, Hironobu Fukui
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Patent number: 6815792Abstract: The present invention provides an epitaxially grown compound semiconductor film having a low density of crystal defects which are generated during the course of crystal growth of a compound semiconductor. The present invention also provides a compound semiconductor multi-layer structure including an n-type InP substrate, an n-type InP buffer layer, an undoped InGaAs light-absorbing layer, and an n-type InP cap layer, the layers being successively grown on the substrate through MOCVD. In the InGaAs layer, the compositional ratio of In/Ga is cyclically varied in a thickness direction (cyclic intervals: 80 nm) so as to fall within a range of ±2% with respect to a predetermined compositional ratio that establishes lattice matching between InGaAs and InP; specifically, within a range between 0.54/0.46 (i.e., In0.54Ga0.46As) and 0.52/0.48 (i.e., In0.52Ga0.Type: GrantFiled: March 27, 2003Date of Patent: November 9, 2004Assignee: Nippon Sheet Glass Company, LimitedInventors: Hisao Nagata, Yasunori Arima, Nobuyuki Komaba
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Patent number: 6812523Abstract: Vacancies and dopant ions are introduced near the surface of a semiconductor wafer. The dopant ions which diffuse by an interstitialcy mechanism have diffusivity greatly reduced, which leads to a very low resistivity doped region and a very shallow junction.Type: GrantFiled: September 9, 2002Date of Patent: November 2, 2004Inventors: Wei-Kan Chu, Lin Shao, Xinming Lu, Jiarui Liu, Xuemei Wang
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Publication number: 20040212046Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.Type: ApplicationFiled: April 22, 2003Publication date: October 28, 2004Applicant: Micron Technology, Inc.Inventors: Paul A. Farrar, Jerome M. Eldridge
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Patent number: 6791106Abstract: An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.Type: GrantFiled: April 23, 2003Date of Patent: September 14, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Ohuchi, Hironobu Fukui
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Publication number: 20040164379Abstract: A method that includes providing a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of masking elements. Each of the plurality of masking elements has a dimension that is equal to a first length, the first length less than twice a diffusion length of a dopant. The method further includes bombarding the semiconductor substrate and masking element with ions of the dopant. The ions form a first impurity concentration in the first region and a second impurity concentration in the second region.Type: ApplicationFiled: February 25, 2003Publication date: August 26, 2004Applicant: Xerox CorporationInventors: Alan D. Raisanen, Shelby F. Nelson
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Publication number: 20040135208Abstract: A semiconductor substrate of the present invention is a DSP wafer or Semi-DSP wafer (FIG. 2) having a flatness of an SFQR value ≦70 (nm) and containing boron at a concentration not lower than 5×1016 (atoms/cm3) nor higher than 2×1017 (atoms/cm3) within 95% or more of rectangular regions of 25×8 (mm2) arranged on a front face of the substrate. Specifically, a silicon crystal layer by an epitaxial growth is formed on a front face of a silicon substrate having the above substrate boron concentration.Type: ApplicationFiled: December 24, 2003Publication date: July 15, 2004Applicant: FUJITSU LIMITEDInventors: Katsuto Tanahashi, Hiroshi Kaneta, Tetsuo Fukuda
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Publication number: 20040124504Abstract: Compositions are provided comprising aqueous dispersions of electrically conducting organic polymers and a plurality of nanoparticles. Films cast from invention compositions are useful as buffer layers in electroluminescent devices, such as organic light emitting diodes (OLEDs) and electrodes for thin film field effect transistors. Buffer layers containing nanoparticles have a much lower conductivity than buffer layers without nanoparticles. In addition, when incorporated into an electroluminescent (EL) device, buffer layers according to the invention contribute to higher stress life of the EL device.Type: ApplicationFiled: September 24, 2003Publication date: July 1, 2004Inventor: Che-Hsiung Hsu
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Patent number: 6727147Abstract: An FET is fabricated on an SOI substrate by the following processes. Openings are formed in laminated layers of a pad oxide film of about 5-10 nm and an oxidation-resistant nitride film of about 50-150 nm at positions where device isolation regions are to be provided. The substrate is irradiated by an ion implantation apparatus with at least one of Ar ions and Si ions with an implantation energy of 40-50 keV, and a dose of 1×1014 to 5×1015 cm−2. Field oxidation is then conducted to electrically separate adjacent devices. The regions of the substrate where the openings are formed become amorphous when irradiated, and the field oxidation is consequently enhanced. Hence, a thermal oxidation film having sufficient thickness can be obtained even at device isolation regions having isolation widths of 0.2 &mgr;m or less.Type: GrantFiled: June 10, 2002Date of Patent: April 27, 2004Assignee: Oki Electric Industry Co., Ltd.Inventors: Toshiyuki Nakamura, Hideaki Matsuhashi
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Publication number: 20040063302Abstract: An N−-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N−-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N−-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N−-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N− region (1a) which is part of the N−-type silicon substrate (1). The N− region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N−-type silicon substrate (1).Type: ApplicationFiled: February 14, 2003Publication date: April 1, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hideki Takahashi, Mitsuru Kaneda
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Publication number: 20040029050Abstract: A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.Type: ApplicationFiled: August 27, 2003Publication date: February 12, 2004Inventors: Rolf Brenner, Tilo Marcus Buehler, Robert Graham Clark, Andrew Steven Dzurak, Alexander Rudolf Hamilton, Nancy Ellen Lumpkin, Rita Paytricia McKinnon
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Patent number: 6680497Abstract: A heterojunction bipolar transistor is doped in the sub-collector layer (20) with phosphorus (24). The presence of the phosphorus causes any interstitial gallium (22) to be bonded (26) to the phosphorus (24) and move to a lattice site. The result is that the interstitial gallium does not diffuse to the base layer and thus does not cause the beryllium to be displaced and diffused. Instead of doping with phosphorus, a layer including phosphorus can also be utilized.Type: GrantFiled: September 22, 2000Date of Patent: January 20, 2004Assignee: TRW Inc.Inventors: Patrick T. Chin, Augusto L. Gutierrez-Aitken, Eric N. Kaneshiro
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Patent number: 6674151Abstract: A semiconductor device having trap sites passivated with deuterium has enhanced immunity to hot carrier effects. The trap sites which are passivated with deuterium are encapsulated beneath a barrier film and are therefore resistant to having the deuterium diffuse away from the trap sites during subsequent high temperature processing operations.Type: GrantFiled: August 23, 1999Date of Patent: January 6, 2004Assignee: Agere Systems Inc.Inventors: Sundar S. Chetlur, Pradip K. Roy, Anthony S. Oates, Sidhartha Sen, Jonathan Z-N. Zhou
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Patent number: 6661061Abstract: A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon.Type: GrantFiled: December 8, 1998Date of Patent: December 9, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, Fred N. Hause
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Patent number: 6639327Abstract: In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member is manufactured by interposing the microgaps between two substrates.Type: GrantFiled: July 6, 2001Date of Patent: October 28, 2003Assignee: Canon Kabushiki KaishaInventors: Kazutaka Momoi, Takao Yonehara, Nobuhiko Sato, Masataka Ito, Noriaki Honma
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Patent number: 6635950Abstract: To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.Type: GrantFiled: September 19, 2000Date of Patent: October 21, 2003Assignee: Hitachi, Ltd.Inventors: Hidetsugu Ishida, Seiichi Isomae
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Patent number: 6627973Abstract: A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology.Type: GrantFiled: September 13, 2002Date of Patent: September 30, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Robert A. Huertas, Lu You, King Wai Kelwin Ko, Pei-Yuan Gao
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Patent number: 6621145Abstract: A metal-semiconductor junction comprises a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 1021 cm−3 or more is provided in a near-surface part of the semiconductor layer (at a distance of 10 nm or less from the metal layer. The high-carrier concentration region is composed of n- or p-type impurity layers and IV-group semiconductor layers that have been alternately deposited upon another by means of, for example, vapor-phase growth.Type: GrantFiled: May 30, 2001Date of Patent: September 16, 2003Assignee: President of Tohoku UniversityInventors: Junichi Murota, Yosuke Shimamune, Masao Sakuraba, Takashi Matsuura
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Patent number: 6621146Abstract: An integrated circuit includes a substrate and a degenerated transistor. The degenerated transistor includes a control terminal formed on the substrate, a channel formed in the substrate beneath the first control terminal, first and second heavily-doped regions embedded in the substrate on opposing sides of the channel, first and second output contacts positioned on the first and second heavily-doped regions, respectively, and a lightly-doped region extending between the first heavily-doped region and the channel. The lightly-doped region has a length that is selected such that the first output contact is spaced from a respective edge of the control terminal by a distance that is at least twice as great as a minimum distance defined for the technology in which the integrated circuit is fabricated and the lightly-doped region has a desired resistance in series with the first output contact.Type: GrantFiled: September 26, 2001Date of Patent: September 16, 2003Assignee: LSI Logic CorporationInventor: Robert J. Bowman
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Patent number: 6620708Abstract: A semiconductor device and method for fabricating a semiconductor device yields improved doping efficiency and increased capacitance. The method includes forming a silicon film on a substrate. HSG having a spherical projection forms on a surface of the silicon film. The surface of the silicon film having the HSG is washed, and a lower electrode forms by a doping process. A dielectric film and an upper electrode are sequentially formed on the silicon film without washing.Type: GrantFiled: November 28, 2000Date of Patent: September 16, 2003Assignee: Hynix SemiconductorInventor: Hong Goo Choi
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Patent number: 6555896Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, Si—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.Type: GrantFiled: December 21, 2000Date of Patent: April 29, 2003Assignee: Micron Technology, Inc.Inventors: David A. Cathey, J. Brett Rolfson, Valerie A. Ward, Karen M. Winchester
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Patent number: 6552414Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate (2) in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate (2); step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate (2) by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate (2), the dopant from said solids-based dopant source diffusing directly into said substrate (2) to form a first diffusion region (12) and, at the time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate (2) to form a second diffusion region (15) in at least some areas of said substrate (2) not covered by said pattern; and step 3) forming a metal contact pattern (20) substantially in alignment with said first diffusion region (12) withType: GrantFiled: August 27, 1999Date of Patent: April 22, 2003Assignee: IMEC vzwInventors: Jörg Horzel, Jozef Szlufcik, Mia Honoré, Johan Nijs
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Patent number: 6541821Abstract: A Silicon-on-Insulator (SOI) transistor includes an intrinsic body layer that is fully depleted when in a conductive state. The transistor includes a shallow pocket of dopants adjacent to each of its source and drain regions. The shallow pockets are of a conductivity type opposite to that of the source and drain regions and raise the threshold voltage of the transistor. The transistor also includes a deep pocket of dopants adjacent each of the source and drain regions to suppress the punch-through current.Type: GrantFiled: December 7, 2000Date of Patent: April 1, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Srinath Krishnan, Witold P. Maszara, Zoran Krivokapic
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Patent number: 6538284Abstract: A transistor on an SOI wafer has a subsurface recombination area within its body. The recombination area includes one or more doped subsurface islands, the doped islands having the same conductivity type as that of a source and a drain on opposite sides of the body, and having an opposite conductivity type from the remainder of the body. The doped subsurface island(s) may be formed by a doping implant into a surface semiconductor layer, for example through an open portion of a doping mask, the opening portion created for example by removal of a dummy gate. The doping of the islands may be performed so that the doping level of the island(s) is approximately the same as that of the body, thus enabling both Shockley-Read-Hall (SRH) and Auger recombination to take place.Type: GrantFiled: February 2, 2001Date of Patent: March 25, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Concetta E. Riccobene, Dong-Hyuk Ju
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Patent number: 6509651Abstract: A substrate-fluorescent LED having a fluorescent-impurity doped substrate and an epitaxial emission structure including an active layer and being made on the substrate. The epitaxial emission structure emits blue or green light corresponding to the band gap of the active layer. The substrate absorbs a part of the blue or green light and makes fluorescence of a longer wavelength. Neutral color light or white light is emitted from the LED. The fluorescent substrate is n-AlGaAs(Si dope), GaP(Zn+O dope), ZnSe(Cu+I, Ag+I, Al+I dope), GaN(O.C.Va(N) dope) or so.Type: GrantFiled: July 12, 1999Date of Patent: January 21, 2003Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hideki Matsubara, Toshihiko Takebe, Kensaku Motoki