With Thin Active Central Semiconductor Portion Surrounded By Thicker Inactive Shoulder (e.g., For Mechanical Support) Patents (Class 257/619)
  • Patent number: 10411140
    Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 ?m2.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 10, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Qing Liu, John H. Zhang
  • Patent number: 10280076
    Abstract: A semiconductor structure includes a first substrate including a cavity extended into the first substrate, a device disposed within the cavity, a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer, and a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer, wherein the first conductive structure is bonded with the second conductive structure and the first dielectric layer is bonded with the second dielectric layer to seal the cavity.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Hua Lin, Ping-Yin Liu, Kuan-Liang Liu, Chia-Shiung Tsai, Alexander Kalnitsky
  • Patent number: 10276419
    Abstract: A compliant electrostatic transfer head and array are described. In an embodiment a compliant electrostatic transfer head includes a base substrate, and a plurality of interdigitated spring electrodes that are deflectable together into a cavity toward the base substrate. Each spring electrode includes mesa structure, and the mesa structures of the plurality of interdigitated spring electrodes are aligned.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 30, 2019
    Assignee: Apple Inc.
    Inventors: Hyeun-Su Kim, Dariusz Golda, John A. Higginson
  • Patent number: 10185418
    Abstract: A touch panel used for a touch control electronic device is disclosed. The touch panel comprises a first board. The first board has a first surface, wherein the first surface undergoes an atomizing process to have at least one semitransparent area. The at least one semitransparent area has a first semitransparent figure which is interlaced by an atomized area and a non-atomized area for changing a light shielding rate of the first semitransparent figure by adjusting the atomized area.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: January 22, 2019
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: Hua Luo, Huilin Ye, Jing Yu, Tsung-Ke Chiu
  • Patent number: 10147645
    Abstract: A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. The top surface the semiconductor wafer undergoes grinding to leave an inner planar surface and a rim, wherein the rim extends above the inner planar surface and around a perimeter of the grinded semiconductor wafer. The first encapsulant material is formed over the inner planar surface and contained within the rim to form a composite semiconductor wafer that has a second brittleness less than the first brittleness. The composite semiconductor wafer is singulated into the plurality of die in which each die of the plurality of die is a composite structure die.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: December 4, 2018
    Assignee: NXP USA, Inc.
    Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Akhilesh K. Singh
  • Patent number: 10121690
    Abstract: Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: November 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Edward Fuergut, Joachim Mahler
  • Patent number: 9954059
    Abstract: A semiconductor wafer is provided with a thick region extending along its outer circumferential surface and being greater in thickness than its central region. A main surface of the wafer includes a slope surface located between the central region and the thick region. The slope surface has an inner circumferential edge and an outer circumferential edge, and slopes such that the thickness of the wafer increases from the inner circumferential edges to the outer circumferential edge. The slope surface includes an inner circumferential portion including the inner circumferential edge, an outer circumferential portion including the outer circumferential edge and an intermediate portion located between the inner and the outer circumferential portions. At least one of slope angles of the inner and the outer circumferential portions is smaller than a slope angle of the intermediate portion.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: April 24, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroshi Shibata, Tatsuya Ito
  • Patent number: 9905465
    Abstract: Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary structure, a substrate has a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon. A first seal ring structure is located within the dielectric layer on the seal ring region, and includes a plurality of first connection layers overlappingly disposed and separated by the dielectric layer. At least one first connection layer is formed by a plurality of discrete sub-connection layers. The first seal ring structure further includes a plurality of first conductive plugs between vertically adjacent first connection layers. A top of each first conductive plug is connected to an upper first connection layer. A bottom of each first conductive plug between at least two vertically adjacent first connection layers extends into the dielectric layer between horizontally adjacent sub-connection layers of a lower first connection layer.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 27, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Xianjie Ning
  • Patent number: 9893166
    Abstract: Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: February 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 9842929
    Abstract: A method of forming a semiconductor device that includes forming a strain relaxed buffer (SRB) layer atop a supporting substrate, and epitaxially forming a tensile semiconductor material atop a first portion of the strain relaxed buffer layer (SRB) layer. A second portion of the SRB layer is then removed, and a semiconductor material including a base material of silicon and phosphorus is formed atop a surface of the supporting substrate exposed by removing the second portion of the SRB layer. A compressive semiconductor material is epitaxially forming atop the semiconductor material including the base material of silicon and phosphorus. Compressive FinFET structures can then be formed from the compressive semiconductor material and tensile FinFET structures can then be formed from the tensile semiconductor material.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: December 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Patent number: 9799547
    Abstract: A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: October 24, 2017
    Assignee: Apple Inc.
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 9755553
    Abstract: A paper-base flexible power-generation apparatus, and a manufacturing method thereof. The flexible power-generation apparatus comprises: a first assembly (1) formed by a paper-base insulation layer (11) and a first metal conductive layer (12) deposited on the surface of the paper-base insulation layer, and a second assembly (2) formed by a paper-base insulation layer (21), a second metal conductive layer (22) deposited on the surface of the paper-base insulation layer, and an electret material layer (23) coating on the surface of the second metal conductive layer. The two edges of the two assemblies are each provided with an electrode (13, 24) and the electrodes are connected through a packaging process. The first metal conductive layer is opposite to and spaced from the electret material layer. The flexible power-generation apparatus has a low cost, is easy to manufacture, has high output power, and is especially suitable for being integrated with other flexible electronic devices.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: September 5, 2017
    Assignee: Huazhong University of Science and Technology
    Inventors: Jun Zhou, Qize Zhong, Junwen Zhong, Bin Hu, Qiyi Hu
  • Patent number: 9617147
    Abstract: Exemplary microelectromechanical system (MEMS) devices, and methods for fabricating such are disclosed. An exemplary method includes providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate includes a first silicon layer separated from a second silicon layer by an insulator layer; processing the first silicon layer to form a first structure layer of a MEMS device; bonding the first structure layer to a substrate; and processing the second silicon layer to form a second structure layer of the MEMS device.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng, Jiou-Kang Lee, Kai-Chih Liang, Chung-Hsien Lin, Te-Hao Lee
  • Patent number: 9543254
    Abstract: A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion of the crackstop disposed along the sides of the IC chip. Each corner crackstop includes a plurality of layers, formed on a top surface of a silicon layer of the IC chip, within a perimeter boundary region that comprises a triangular area, in which a right angle is disposed on a bisector of the corner, equilateral sides of the triangle are parallel to sides of the IC chip, and the right angle is proximate to the corner relative to a hypotenuse of the triangle. The plurality of layers of the corner crackstop include crackstop elements, each comprising a metal cap centered over a via bar, in which the plurality of layers of the corner crackstop is chamfered to deflect crack ingress forces by each corner crackstop.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mark C. Lamorey, David B. Stone
  • Patent number: 9508876
    Abstract: Solar cell including a substrate with first p-n-junction, separating the substrate into front portion having first doping and rear portion having second doping, being located close to front surface of substrate. A front layer having a p-n-junction, separating the front layer into front portion having first doping and rear portion having second doping. At least one first electric contact provided on front side of the solar cell electrically connected to front portion of the front layer, and second electric contact provided on rear side of solar cell electrically connected to a contact point provided on front side of the solar cell. Contact point is placed on a bottom surface of a groove open to front side of the cell and extending to rear portion of substrate, and an electrical connection between the second electric contact and the contact point is provided by the rear portion.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: November 29, 2016
    Assignee: ASTRIUM GMBH
    Inventor: Claus Zimmermann
  • Patent number: 9508812
    Abstract: A semiconductor device is provided that comprises a semiconductor substrate comprising an active area and a peripheral region adjacent the active area and structure positioned in the peripheral region for hindering the diffusion of mobile ions from the peripheral region into the active area.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: November 29, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Stephan Voss, Markus Zundel
  • Patent number: 9472483
    Abstract: A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (TCPVs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth. Each TCPV may include a barrier layer deposited within the recess and deposited upon the back side of the chip. Each TCPV may also include a thermally conductive layer deposited upon the barrier layer. The structure may also include through-silicon vias (TSVs) electrically connected to active devices, extending from the back side to an active device side of the chip to conductively remove heat from the active devices to the back side of the chip.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal, Sebastian T. Ventrone
  • Patent number: 9406541
    Abstract: A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: August 2, 2016
    Assignee: Apple Inc.
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 9217541
    Abstract: A stabilization structure includes a stabilization layer on a carrier substrate. The stabilization layer includes an array of staging cavities. An array of micro devices are within the array of staging cavities. Each micro device is laterally attached to a shear release post laterally extending from a sidewall of a staging cavity. A pressure is applied to the array of micro devices from the array of transfer heads to shear the array of micro devices off the shear release posts. The sheared off micro devices are picked up from the carrier substrate using the array of transfer heads.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: December 22, 2015
    Assignee: LuxVue Technology Corporation
    Inventors: Stephen Bathurst, Hsin-Hua Hu, Andreas Bibl
  • Patent number: 9018739
    Abstract: The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; a second semiconductor layer surrounding the first semiconductor layer; a high k dielectric layer and a gate conductor formed on the first semiconductor layer; source/drain regions formed in the second semiconductor layer, wherein the second semiconductor layer has a slant sidewall in contact with the first semiconductor layer. The semiconductor device has an increased output current, an increased operating speed, and a reduced power consumption due to the channel region of high mobility.
    Type: Grant
    Filed: September 25, 2010
    Date of Patent: April 28, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qingqing Liang, Zhijiong Luo, Haizhou Yin
  • Patent number: 9006859
    Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Gurtej S. Sandhu
  • Patent number: 9000566
    Abstract: A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: April 7, 2015
    Assignee: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 8981454
    Abstract: The present application discloses a non-volatile memory device, comprising a semiconductor fin on an insulating layer; a channel region at a central portion of the semiconductor fin; source/drain regions on both sides of the semiconductor fin; a floating gate arranged at a first side of the semiconductor fin and extending in a direction further away from the semiconductor fin; and a first control gate arranged on top of the floating gate or covering top and sidewall portions of the floating gate. The non-volatile memory device reduces a short channel effect, has an increased memory density, and is cost effective.
    Type: Grant
    Filed: September 25, 2010
    Date of Patent: March 17, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Haizhou Yin, Zhijiong Luo
  • Patent number: 8946811
    Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
  • Patent number: 8928119
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: January 6, 2015
    Inventor: Glenn J. Leedy
  • Patent number: 8928120
    Abstract: Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming Chyi Liu, Sheng-de Liu, Chi-Ming Chen, Yuan-Tai Tseng, Chung-Yen Chou, Chia-Shiung Tsai
  • Publication number: 20150001682
    Abstract: Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Ming Chyi Liu, Sheng-de Liu, Chi-Ming Chen, Yuan-Tai Tseng, Chung-Yen Chou, Chia-Shiung Tsai
  • Patent number: 8901667
    Abstract: A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Sivananda Kanakasabapathy
  • Publication number: 20140239454
    Abstract: A semiconductor device and a method for forming a device are presented. A wafer substrate having first and second regions is provided. The second region includes an inner region of the substrate while the first region includes an outer peripheral region from an edge of the substrate towards the inner region. A protection unit is provided above the substrate. The protection unit includes a region having a total width WT defined by outer and inner rings of the protection unit. The substrate is etched to form at least a trench in the second region of the substrate. The WT of the protection unit is sufficiently wide to protect the first region of the wafer substrate such that the first region is devoid of trench.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Qiaoming CAI, Wurster KAI, Chunyan XIN, Frank JAKUBOWSKI
  • Patent number: 8803290
    Abstract: The amount of signal propagation and moisture penetration and corresponding reliability problems due to moisture penetration degradation in an IC can be reduced by fabricating two seal rings with non-adjacent gaps. In one embodiment, the same effect can be achieved by fabricating a wide seal ring with a channel having offset ingress and egress portions. Either of these embodiments can also have grounded seal ring segments which further reduce signal propagation.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: August 12, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Norman Frederick, Jr., Tom Myers
  • Patent number: 8779555
    Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Po-Tao Chu
  • Patent number: 8759163
    Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chow Peng, Wen-Shen Chou, Jui-Cheng Huang
  • Patent number: 8754338
    Abstract: An electronics interconnection system is provided with reduced capacitance between a signal line and the surrounding dielectric material. By using a non-homogenous dielectric, the effective dielectric constant of the material is reduced. This reduction results in less power loss from the signal line to the dielectric material, and therefore reduces the number of buffers needed on the signal line. This increases the speed of the signal, and reduces the power consumed by the interconnection system. The fabrication techniques provided are advantageous because they can be preformed using today's standard IC fabrication techniques.
    Type: Grant
    Filed: May 28, 2011
    Date of Patent: June 17, 2014
    Assignee: Banpil Photonics, Inc.
    Inventor: Achyut Kumar Dutta
  • Patent number: 8754396
    Abstract: The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: June 17, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John A. Rogers, Dahl-Young Khang, Yugang Sun, Etienne Menard
  • Patent number: 8754504
    Abstract: A thinning method of a wafer is provided. The method includes the following steps. First, a wafer having a first surface, a second surface, and a side surface is provided, and the side surface is connected between the first surface and the second surface. At least one semiconductor device is formed on the first surface. Then, an anisotropy etching process is performed to the second surface with a mask to remove portions of the wafer while remaining the side surface thereby forming a number of grooves in the second surface and at least one reinforcing wall between the grooves. As a result, a thinned wafer is obtained.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: June 17, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chang-Sheng Hsu, Kuo-Yuh Yang, Kuo-Hsiung Huang, Yan-Da Chen, Chia-Wen Lien
  • Patent number: 8739632
    Abstract: A pressure sensor can include a diaphragm plate of an electrically conductive material, the diaphragm plate including substantially planar opposed first and second surfaces. A layer of a dielectric material can be provided at the first surface of the diaphragm plate along a periphery thereof such that a flexion region of the first surface is substantially free of the dielectric material. The dielectric layer can be configured to engage a fixed structure within a housing to support the flexion region as to enable deflection thereof relative to the fixed structure that changes an electrical characteristic of the pressure sensor in response to application of force at the second surface of the diaphragm plate.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: June 3, 2014
    Assignee: Case Western Reserve University
    Inventors: Shih-Shian Ho, Srihari Rajgopal, Mehran Mehregany
  • Patent number: 8729524
    Abstract: In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: May 20, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John A. Rogers, Matthew Meitl, Yugang Sun, Heung Cho Ko, Andrew Carlson, Won Mook Choi, Mark Stoykovich, Hanqing Jiang, Yonggang Huang, Ralph G. Nuzzo, Zhengtao Zhu, Etienne Menard, Dahl-Young Khang
  • Patent number: 8716767
    Abstract: A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: May 6, 2014
    Assignee: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 8710638
    Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a first substrate; bonding a second substrate to the first substrate, the second substrate including a microelectromechanical system (MEMS) device; and bonding a third substrate to the first substrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ting-Hua Wu
  • Patent number: 8686542
    Abstract: A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 1, 2014
    Assignee: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Publication number: 20140084424
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 27, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Xia Feng, Kang Chen, Jianmin Fang
  • Publication number: 20140084423
    Abstract: A wafer processing method including a fixing step of providing a wafer on a protective member so that a device area of the wafer faces an unevenness absorbing member provided in a recess of the protective member and providing an adhesive outside the device area to thereby fix the protective member and the wafer, a grinding step of holding the protective member on a holding table in the condition where the back side of the wafer is exposed and next grinding the back side of the wafer by using a grinding unit to thereby reduce the thickness of the wafer to a predetermined thickness, and a removing step of removing the protective member from the wafer. The adhesive is locally provided outside of the device area, so that the protective member can be easily removed from the wafer without leaving the adhesive on the front side of each device.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 27, 2014
    Applicant: Disco Corporation
    Inventor: Karl Heinz Priewasser
  • Patent number: 8679952
    Abstract: A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from <0001> face, in a reducing gas atmosphere at a first temperature T1 for a treatment time t, a second step of reducing the temperature of the substrate in the reducing gas atmosphere, and a third step of performing epitaxial growth at a second temperature T2 below the annealing temperature T1 in the first step, while supplying at least a gas including silicon atoms and a gas including carbon atoms.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: March 25, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuyuki Tomita, Kenichi Hamano, Masayoshi Tarutani, Yoichiro Mitani, Takeharu Kuroiwa, Masayuki Imaizumi, Hiroaki Sumitani, Kenichi Ohtsuka, Tomoaki Furusho, Takao Sawada, Yuji Abe
  • Patent number: 8680624
    Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: March 25, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Man Fai Ng, Bin Yang
  • Publication number: 20140048909
    Abstract: A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.
    Type: Application
    Filed: October 25, 2013
    Publication date: February 20, 2014
    Applicant: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 8642434
    Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R. Holt, Renee T. Mo, Kern Rim
  • Patent number: 8624358
    Abstract: A semiconductor substrate having a semiconductor device formable area, wherein a reinforcing part, which is thicker than the semiconductor device formable area and has a top part of which surface is flat, is formed on an outer circumference part of the semiconductor substrate, and an inner side surface connecting the top part of the reinforcing part and the semiconductor device formable area has a cross-sectional shape of which inner diameter becomes smaller as being closer to the semiconductor device formable area.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: January 7, 2014
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Mitsuharu Yamazaki
  • Patent number: 8624339
    Abstract: A vibrating device has a package having an accommodating space in the interior thereof and a gyro element and an IC chip accommodated in the accommodating space. The package has a plate-like bottom plate having an IC chip mounting area and a vibrating element mounting area. The IC chip mounting area includes an IC chip mounting surface on which the IC chip is mounted. The vibrating element mounting area is arranged in parallel with the IC chip mounting area and includes a vibrating element mounting surface on which the gyro element is mounted. The thickness of the IC chip mounting area is smaller than that of the vibrating element mounting area. The IC chip mounting surface is located closer to a bottom side than the vibrating element mounting surface.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: January 7, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Norihito Matsukawa, Atsushi Ono, Mitsuhiro Tateyama, Tsunenori Shibata
  • Patent number: 8569115
    Abstract: A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: October 29, 2013
    Assignee: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 8502350
    Abstract: According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Sugawara, Masaaki Onomura