Abstract: Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate. A through-semiconductor via is formed in the semiconductor substrate, and an interlayer dielectric layer is formed that overlies the through-semiconductor via and the plurality of semiconductor devices. A first interconnect via is embedded within the interlayer dielectric layer, and a second interconnect via is embedded within the interlayer dielectric layer. The first interconnect via and the second interconnect via are in electrical communication with the through-semiconductor via at spaced locations from each other on the through-semiconductor via.

Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch.

Abstract: A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.

Abstract: A semiconductor apparatus with a penetrating electrode having a high aspect ratio is manufactured with a low-temperature process. In one embodiment a first electrode 3 and a second electrode 6 of a semiconductor substrate 1 that are provided at the front and rear surface sides, respectively, are electrically connected by a conductive object 7 filled in a contact hole 4 and an extended portion 6a of the second electrode 6 extends to the contact hole 4. Even though the contact hole 4 has a high aspect ratio, film formation using the low-temperature process is enabled by using the conductive object 7, instead of forming the second electrode 6 on a bottom portion of the contact hole 4.

Abstract: A method of providing signal, power and ground through a through-silicon-via (TSV), and an integrated circuit chip having a TSV that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a TSV through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via. The multitude of conductive bars include at least one signal bar, at least one power bar, and at least one ground bar. The method further comprises connecting the at least one power bar to a power voltage source to apply power through the TSV; connecting the at least one ground bar to a ground voltage; and connecting the at least one signal bar to a source of an electronic signal to conduct the signal through the TSV and to form a hybrid power-ground-signal TSV in the substrate.

Abstract: A pressure sensor component includes a MEMS component having at least one pattern element that is able to be deflected perpendicular to the component plane, which is equipped with at least one electrode of a measuring capacitor device, and an ASIC component having integrated circuit elements and at least one back end stack, at least one counter-electrode of the measuring capacitor device being developed in a metallization plane of the back end stack. The MEMS component is mounted on the back end pile of the ASIC component. The MEMS component includes at least one pressure-sensitive diaphragm pattern and is mounted on the ASIC component in such a way that the pressure-sensitive diaphragm pattern spans a cavity between the MEMS component and the back end stack of the ASIC component.

Abstract: A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.

Abstract: A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC within a region of the interposer exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC.

Abstract: A semiconductor device includes a substrate including first and second surfaces, a first insulating film including third and fourth surfaces, the fourth surface being in contact with the first surface, and an electrode elongated to penetrate the substrate and the first insulating film, the electrode including a first portion and a second portion. The first portion includes first and second end parts and a center part sandwiched between the first and second end part. The first and second end parts of the first portion are smaller in diameter than at least a portion of the center part of the first portion. The second portion is located between the first portion and the third surface, and includes a third end part exposed from the third surface and a fourth end part connected to the first end part of the first portion.

Abstract: A semiconductor die including strain relief for through substrate vias (TSVs). The semiconductor die includes a semiconductor substrate having an active face. The semiconductor substrate includes conductive layers connected to the active face. The semiconductor die also includes a through substrate via extending only through the substrate. The through substrate via may include a substantially constant diameter through a length of the through substrate via. The through substrate via may be filled with a conductive filler material. The semiconductor die also includes an isolation layer surrounding the through substrate via. The isolation layer may include two portions: a recessed portion near the active face of the substrate capable of relieving stress from the conductive filler material, and a dielectric portion. A composition of the recessed portion may differ from the dielectric portion.

Abstract: A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.

Abstract: A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure.

Abstract: A semiconductor device includes: a plurality of semiconductor chips stacked on each other, each of the plurality of semiconductor chips having a semiconductor substrate and a wiring layer; a through electrode penetrating the semiconductor substrate in a thickness direction and electrically connected to each other between the semiconductor chips adjacent to each other; a conductor penetrating the semiconductor substrate in the thickness direction and not electrically connected between the other semiconductor chips; and an insulating separator penetrating the semiconductor substrate in the thickness direction and formed in a shape of a ring surrounding the conductor.

Abstract: A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor substrate through an adhesive layer. Then, there is formed a protection layer that has an opening at a location corresponding to the pad electrode and covers a side surface and a back surface of the semiconductor substrate. A conductive terminal is formed on the pad electrode at the location corresponding to the opening formed in the protection layer. No wiring layer or conductive terminal is formed on the back surface of the semiconductor substrate. A conductive terminal is formed on a periphery of the supporter outside of and next to the side surface of the semiconductor substrate.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: A semiconductor device and method for forming the same provide a through silicon via (TSV) surrounded by a dielectric liner. The TSV and dielectric liner are surrounded by a well region formed by thermal diffusion. The well region includes a dopant impurity type opposite the dopant impurity type of the substrate. The well region may be a double-diffused well with an inner portion formed of a first material and with a first concentration and an outer portion formed of a second material with a second concentration. The surrounding well region serves as an isolation well, reducing parasitic capacitance.

Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor element on a main surface of a substrate; forming a low melting glass film having a melting point of 450° C. or less on the main surface and the semiconductor element; heat treating the substrate while pressing the low melting glass film toward the main surface of the substrate with a pressurizing jig that is insulating or semi-insulating, and sintering the low melting glass film; and leaving the pressurizing jig on the low melting glass film after sintering the low melting glass film.

Abstract: A wafer stacking structure includes a first wafer and a second wafer. The first wafer includes a first through silicon via (TSV) opening and a first TSV filling portion formed in the first TSV opening and including a concave structure. The second wafer includes a second TSV opening and a second TSV filling portion formed in the second TSV opening and including a convex structure. A front surface of the first wafer faces a front surface of the second wafer, and the convex structure of the second TSV filling portion is inserted into the concave structure of the first TSV filling portion.

Abstract: A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole with a conductive filler; a deepest part of each filler includes a bump portion made of a solder material. The method further includes the step of removing a part of the substrate extending from the second surface to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding bump.

Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.

Abstract: An apparatus includes a radio-frequency die with shielding through-silicon vias and a die backside lattice lid that shield a sector in the RF die from radio- and electromagnetic interference.

Abstract: Embodiments of the present invention provide an apparatus that includes a semiconductor substrate comprising a first surface having one or more integrated circuit devices formed thereon and a second surface opposite the first surface, wherein one or more vias are formed through the semiconductor substrate to couple the first surface with the second surface. The apparatus may further include a redistribution layer coupled with the second surface of the semiconductor substrate, wherein the one or more vias couple the redistribution layer with the first surface of the semiconductor substrate. Other embodiments including, for example, associated packages and methods may be described and/or claimed.

Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.

Abstract: The present invention provides a method for forming a three-dimensional wafer stack having a single metallized stack via with a variable cross-sectional shape. The method uses at least first and silicon wafers. Each wafer has one or more integrated circuits formed thereon. One or more through-vias are formed in each silicon wafer followed by oxide formation on at least an upper and lower surface of the silicon wafer. The wafers are aligned such that each wafer through via is aligned with a corresponding through via in adjacent stacked wafers. Wafers are bonded to form a three-dimensional wafer stack having one or more stack vias formed from the alignment of individual wafer vias. Via metallization is performed by depositing a seed layer in each of the stack vias followed by copper electroplating to form a continuous and homogeneous metallization path through the three-dimensional wafer stack.

Abstract: The present disclosure relates to a dielectric solder barrier for a semiconductor die. In one embodiment, a semiconductor die includes a substrate, a semiconductor body on a first surface of the substrate, one or more first metallization layers on the semiconductor body opposite the substrate, a via that extends from a second surface of the substrate through the substrate and the semiconductor body to the one or more first metallization layers, and a second metallization layer on the second surface of the substrate and within the via. A portion of the second metallization layer within the via provides an electrical connection between the second metallization layer and the one or more first metallization layers. The semiconductor die further includes a dielectric solder barrier on the second metallization layer. Preferably, the dielectric solder barrier is on a surface of the portion of the second metallization layer within the via.

Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.

Abstract: When a silicon through electrode is to be formed from a back surface (the surface on which a semiconductor device is not formed) of a silicon substrate, a wide range of an interlayer insulating film made of a Low-k material absorbs moisture, and there is a problem that the electrical characteristics of wiring are degraded. The above-described problem can be solved by forming at least a single ring-shaped frame laid out to enclose the silicon through electrode by using metal wirings in plural layers and a connection via connecting the upper and lower metal wirings in a Low-k material layer penetrated by the silicon through electrode and by forming a moisture barrier film made up of at least a metal wiring and a connection via between the silicon through electrode and a circuit wiring formed in the vicinity of the silicon through electrode.

Abstract: A die includes a seal-ring structure below a substrate. The seal-ring structure is disposed around at least one substrate region. At least one means for substantially preventing ion diffusion into the substrate region. The at least one means is coupled with the seal-ring structure.

Abstract: An integrated circuit structure can include a silicon interposer. The silicon interposer can include a first elliptical TSV and a keep out zone (KOZ) for stress effects upon active devices surrounding the first elliptical TSV. A size of the KOZ can be determined by a transverse diameter and a conjugate diameter of the first elliptical TSV.

Abstract: A mask drawing method includes: disposing a grounding body provided with a grounding pin at a plurality of different places on a mask substrate to measure resistance values; disposing the grounding body at a position where the resistance value is lowest, among the plural positions where the resistance values are measured; and irradiating an electron beam to the mask substrate to draw a desired pattern.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming first spacers covering both sidewalls of each of the first trenches, forming a plurality of second trenches by etching a bottom of each of the first trenches, forming second spacers covering both sidewalls of each of the second trenches, forming a plurality of third trenches by etching a bottom of each of the second trenches, forming an insulation layer covering exposed surfaces of the plurality of the substrate, and forming a contact which exposes one sidewall of each of the second trenches by selectively removing the second spacers.

Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.

Abstract: A semiconductor device includes: a semiconductor substrate that includes a semiconductor; an electrode layer formed on a first surface side inside the semiconductor substrate; a frame layer laminated on the first surface of the semiconductor substrate; a conductor layer formed in an aperture portion formed by processing the semiconductor substrate and the frame layer in such a manner as to expose the electrode layer on the first surface of the semiconductor substrate; a vertical hole formed through the semiconductor substrate from a second surface of the semiconductor substrate to the conductor layer; and a wiring layer that is electrically connected to the electrode layer via the conductor layer at an end portion of the vertical hole, and that extends to the second surface of the semiconductor substrate.

Abstract: The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

Abstract: An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.

Abstract: Provided is a power voltage supply apparatus of a 3-dimensional (3D) semiconductor. The power voltage supply apparatus includes a plurality of integrated circuits (ICs) which each include a first through silicon via (TSV) and a second TSV, are stacked such that the first TSVs are connected and second TSVs are connected, and are mounted on a printed circuit board (PCB), wherein a first PCB line formed on the PCB and supplying a first voltage is connected to a bottom of a first TSV of a bottom IC from among the plurality of ICs, and a second PCB line formed on the PCB and supplying a second voltage is connected to a top of a second TSV of a top IC.

Abstract: Semiconductor packages capable of reducing a total height thereof and methods of manufacturing the semiconductor package are provided. The semiconductor package includes a semiconductor substrate having first and second surfaces opposite to each other, a semiconductor device formed on the first surface of the semiconductor substrate, pads formed on the first surface of the semiconductor substrate and electrically connected to the semiconductor device, and at least one printed circuit layer including a resin layer, via electrodes penetrating through the resin layer, and line layers formed on the first resin layer and connected to the via electrodes and attached onto the first surface of the semiconductor substrate. The via electrodes and the line layers are formed of the same type of material, and the via electrodes are electrically connected to the pads.

Abstract: A semiconductor device is disclosed allowing detection of a connection state of a Through Silicon Via (TSV) at a wafer level. The semiconductor device includes a first line formed over a Through Silicon Via (TSV), a second line formed over the first line, and a first power line and a second power line formed over the same layer as the second line. Therefore, the semiconductor device can screen not only a chip-to-chip connection state after packaging completion, but also a connection state between the TSV and the chip at a wafer level, so that unnecessary costs and time encountered in packaging of a defective chip are reduced.

Abstract: A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

Abstract: Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a bottom integrated circuit having bottom through silicon vias with a bottom via pitch; mounting outer interconnects over the bottom integrated circuit; and mounting a top integrated circuit between the outer interconnects, the top integrated circuit having top through silicon vias with a top via pitch less than the bottom via pitch.

Abstract: A through-substrate via (TSV) die includes a substrate having a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface, wherein the layers on the top side semiconductor surface exert a net tensile stress to the top side semiconductor surface. A plurality of TSVs which extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface include an inner metal core surrounded by a dielectric liner that forms an outer edge for the TSVs. A dielectric stack is on the bottom side surface lateral to the TSV tips including a compressive dielectric layer and a tensile dielectric layer on the compressive dielectric layer.

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract: A semiconductor device mounting structure includes: a substrate with an opening provided therein; a frame member with a frame body and a protruding portion that protrudes from the frame body, the frame body being formed and accommodated in a groove around the opening; a coreless substrate provided above the substrate and supported by the protruding portion of the frame member; and semiconductor elements provided on the coreless substrate.

Abstract: A semiconductor device includes a first semiconductor package including a first mold part, a second semiconductor package including a second mold part, a connecting pattern configured to electrically connect the first and second semiconductor packages to each other, and a molding pattern between the first and second semiconductor packages. The molding pattern extends to cover at least a portion of a sidewall of only the second semiconductor package.

Abstract: Using printing technologies to fill conductor materials into holes in silicon substrate, the preferred embodiments of the present improve cost efficiency of through-hole connections. Using silicon substrate as cathode terminal during electrical plating that fill holes in a silicon substrate with conductors, the preferred embodiments of the present improve alignment accuracy and cost efficiency of through-hole manufacturing processes.

Abstract: A semiconductor die has through silicon vias arranged to reduce warpage. The through silicon vias adjust the coefficient of thermal expansion of the semiconductor die, permit substrate deformation, and also relieve residual stress. The through silicon vias may be located in the edges and/or corners of the semiconductor die. The through silicon vias are stress relief vias that can be supplemented with round corner vias to reducing warpage of the semiconductor die.

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract: A stacked structure and a stacked method for a three-dimensional integrated circuit are provided. The provided stacked method includes separating a logic chip into a function chip and an I/O chip; stacking the function chip above the I/O chip; and stacking at least one memory chip between the function chip and the I/O chip.