Abstract: An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.

Abstract: A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size.

Abstract: A semiconductor wafer has an insulating layer formed over an active surface of the wafer. A conductive layer is formed over the insulating layer. A first via is formed from a back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. A conductive material is deposited in the first via to form a conductive TSV. An insulating material can be deposited in the first via to form an insulating core within the conductive via. After forming the conductive TSV, a second via is formed around the conductive TSV from the back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. An insulating material is deposited in the second via to form an insulating annular ring. The conductive via can be recessed within or extend above a surface of the semiconductor die.

Abstract: A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.

Abstract: A method of forming a contact includes forming an inter-layer dielectric layer to cover a gate formed on a semiconductor substrate; and forming a first hole which passes through the inter-layer dielectric layer to expose the gate, a second hole which exposes an active region of the semiconductor substrate, and a third hole which exposes the semiconductor substrate at a preset depth. Further, the method includes forming a shielding layer on the semiconductor substrate including the bottom and sidewalls of the first hole, the second hole, and the third hole; and removing the shielding layer at the bottom of the first hole and the second hole to expose the gate and the active region. Furthermore, the method includes filling the first hole, the second hole, and the third hole with a conductive material.

Abstract: A semiconductor package includes a substrate including a substrate body having a first face and a second face opposing the first face. A first through electrode passes through the substrate body between the first face and the second face. An insulation member is disposed over the first face; and a connection member having a first conductive unit disposed inside of the insulation member is electrically connected to the first through electrode, and a second conductive unit electrically connected to the first conductive unit is exposed at side faces of the insulation member. A semiconductor chip having third and fourth faces is disposed over the first face of the substrate body in a vertical direction. A second through electrode passes through the substrate body between the third and fourth faces and is electrically connected to the second conductive unit.

Abstract: A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized.

Abstract: A method for forming an image sensor chip package includes: providing a substrate having predetermined scribe lines defined thereon, wherein the predetermined scribe lines define device regions and each of the device regions has at least a device formed therein; disposing a support substrate on a first surface of the substrate; forming at least a spacer layer between the support substrate and the substrate, wherein the spacer layer covers the predetermined scribe lines; forming a package layer on a second surface of the substrate; forming conducting structures on the second surface of the substrate, wherein the conducting structures are electrically connected to the corresponding device in corresponding one of the device regions, respectively; and dicing along the predetermined scribe lines such that the support substrate is removed from the substrate and the substrate is separated into a plurality of individual image sensor chip packages.

Abstract: In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.

Abstract: A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process.

Abstract: The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.

Abstract: An assembly and method of making same are provided. The assembly can be formed by stacking a first semiconductor element atop a second semiconductor element and forming an electrically conductive element extending through openings of the semiconductor elements. The openings may be staged. The conductive element can conform to contours of the interior surfaces of the openings and can electrically connect conductive pads of the semiconductor elements. A dielectric region can be provided at least substantially filling the openings of the semiconductor elements, and the electrically conductive element can extend through an opening formed in the dielectric region.

Abstract: A substrate of an integrated circuit has a first surface and an opposing second surface. A functionalized region is formed at least on the first surface. At least one electrical through-plating is provided as a through-hole which is continuously filled with an electrically conductive material and which runs from the first surface to the second surface through the substrate. To ensure that the through-plating can be reliably produced and is provided in a space-saving manner, the through-hole has at least one gradation on which a transition occurs from a smaller hole cross-section on the side of the first surface to a larger hole cross-section on the side of the second surface.

Abstract: Semiconductor devices are provided including an internal circuit on a front side of a substrate, the substrate defining a through-silicon via (TSV) structure extending vertically therein; a back side insulating layer on a back side of the substrate; and a back side bonding structure on the back side insulating layer. The TSV structure includes a front side end on a front side of the substrate and contacts the internal circuit and a back side end extending toward a back side of the substrate. The back side bonding structure includes a back side bonding interconnection portion on the back side insulating layer defining a back side bonding via hole therein and a back side bonding via plug portion in the contact plug hole in the back side insulating layer connected to a back side end of the TSV structure.

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract: A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.

Abstract: Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies. The multi-memory die is created by singulating the wafer of semiconductor material into memory dies where at least one of the memory dies is a multi-memory die that includes multiple individual memory dies that are still physically connected together. The method further comprises coupling a semiconductor die to the multi-memory die.

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.

Abstract: Subject matter disclosed herein may relate to packaging for multi-chip semiconductor devices as may be used, for example, in flash memory devices. In an example embodiment, a semiconductor chip may comprise a through-silicon via and a sidewall pad.

Abstract: A structure of connecting at least two integrated circuits in a 3D arrangement by a metal-filled through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.

Abstract: A semiconductor device includes an assembly of two integrated circuits. The assembly has a layer of photoresist filling the space between the two integrated circuits, and at least one electrically conducting pillar within the resist and electrically coupling the two integrated circuits.

Abstract: An electronic device can include a substrate including a first region having a first thickness, and a second region having a second thickness different from the first thickness. The electronic device can include a via within the first region. The electronic device can include a conductive structure adjacent to the first region and connected to the via, wherein a combined thickness of the first thickness and a thickness of the conductive structure is thicker than the second thickness. In another embodiment, an interposer may have a similar structure, with laterally offset conductive structures that allow for lateral routing of electronic signals. A process of forming an electronic device can include forming a via and removing a portion of the substrate. The process can include forming a conductive structure connected to the via, wherein the conductive structure is adjacent to a region where the portion of the substrate has been removed.

Abstract: A wiring board includes a silicon substrate with a through hole communicating with first and second substrate surfaces. A capacitor includes a capacitor part mounted on an insulating film covering the substrate first surface and including a first electrode on the insulating film, a first dielectric layer on the first electrode, and a second electrode on the first dielectric layer. A multilayer structure arranged on a wall surface defining the through hole includes the insulating film on the through hole wall surface, a first metal layer on the insulating film formed from the same material as the first electrode, a second dielectric layer on the first metal layer formed from the same material as the first dielectric layer, and a second metal layer on the second dielectric layer formed from the same material as the second electrode. The multilayer structure covers a penetration electrode in the through hole.

Abstract: A semiconductor chip includes a substrate having a front surface and a back surface opposite the front surface, a conductive column part passing through the substrate from the front surface to the back surface, a cavity formed by removing a part of the back surface around an end portion of the conductive column part such that the end portion of the conductive column part protrudes from the cavity, a first insulation layer formed in the cavity such that a portion of the end portion of the conductive column part is exposed, and a back electrode electrically connected to the exposed end portion of the conductive column part.

Abstract: A method for depositing one or more polycrystalline silicon layers (230c) on a substrate (210) by a chemical vapour deposition in a reactor, includes adjusting a deposition temperature between 605° C.-800° C. in a process chamber of the reactor, and depositing the one or more polycrystalline silicon layers on the substrate by using a silicon source gas including SiH4 or SiH2Cl2, and a dopant gas including BCl3.

Abstract: A semiconductor chip includes a semiconductor substrate having one surface, the other surface which faces away from the one surface, and an integrated circuit which is formed on the one surface; and a shielding layershielding layer formed in the semiconductor substrate to correspond to the other surface.

Abstract: An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Abstract: A semiconductor device comprises: a semiconductor package having a top surface, a bottom surface, and a through hole provided from the top surface to the bottom surface; and an electrode inserted into the through hole of the semiconductor package. The semiconductor package includes: an insulating substrate; a semiconductor chip on the insulating substrate; an electrode pattern on the insulating substrate and connected to the semiconductor chip; a resin sealing the insulating substrate, the semiconductor chip, and the electrode pattern; and an electrode section on an inner wall of the through hole and connected to the electrode pattern. The through hole penetrates the insulating substrate and the resin. The electrode inserted into the through hole is connected to the electrode section inside the semiconductor package.

Abstract: Provided is a semiconductor light emitting device. The semiconductor light emitting device includes a light emitting structure disposed under an insulating layer having a plurality of holes. A first electrode is disposed on the insulating layer and a second electrode disposed is disposed under the light emitting structure. A conductive supporting member is disposed under the second electrode. The plurality of contact protrusions are disposed in the holes of the insulating layer and include filler connected to the first conductive semiconductor layer and disposed in the plurality of holes. The conductive supporting member physically contacts with the second electrode and has a thickness thicker than that of the insulating layer. The first electrode is located at a higher position than an entire region of the insulating layer and the insulating layer is located at a higher position than an entire region of the light emitting structure.

Abstract: The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: Provided is a substrate structure, including: a first substrate and a second substrate arranged correspondingly. A first surface of the first substrate faces a second surface of the second substrate, wherein the first surface is successively arranged with a conductor interconnection layer and a bonding layer, with the bonding layer connecting the first substrate and the conductor interconnection layer to the second substrate. The substrate structure and a method for manufacturing the same. The second substrate can serve as a support substrate and the first substrate as a substrate for directly manufacturing a device. However, the first substrate is formed by the growth of a crystal without the problem of thickness and stress thereof, thereby avoiding unnecessary stress and further improving the performance of the device formed in the first substrate.

Abstract: A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.

Abstract: Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.

Abstract: Stress barrier structures for semiconductor chips, and methods of fabrication thereof are described. In one embodiment, the semiconductor device includes a semiconductor substrate that includes active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure includes a layer of low-k insulating layer. A first metal bump is disposed over the semiconductor substrate and coupled to the active circuitry of the semiconductor substrate. A first stress barrier structure is disposed under the metal bump, and disposed over the low-k insulating layer, and a second substrate is disposed over the first metal bump.

Abstract: A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture.

Abstract: Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material.

Abstract: It is described a low ohmic Through Wafer Interconnection (TWI) for electronic chips formed on a semiconductor substrate (600). The TWI comprises a first connection extending between a front surface and a back surface of the substrate (600). The first connection (610) comprises a through hole filled with a low ohmic material having a specific resistivity lower than poly silicon. The TWI further comprises a second connection (615) also extending between the front surface and the back surface. The second connection (615) is spatially separated from the first connection (610) by at least a portion of the semiconductor substrate (600). The front surface is provided with a integrated circuit arrangement (620) wherein the first connection (610) is electrically coupled to at least one node of the integrated circuit arrangement (620) without penetrating the integrated circuit arrangement (620). During processing the TWI the through hole may be filled first with a non-metallic material, e.g. poly silicon.

Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

Abstract: A MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface.

Abstract: Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract: A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.

Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

Abstract: Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.

Abstract: A cavity wafer for flip chip stacking includes an electrostatic (ESC) chuck wafer with a plurality of cavities, and a bonding layer on a surface of the ESC chuck wafer. The bonding layer is configured to receive a through-silicon-via (TSV) interposer with solder bumps. The plurality of cavities are configured to receive the solder bumps at the TSV interposer. The bonding layer is configured to receive an electrostatic bias for bonding the ESC chuck wafer to the TSV interposer with the solder bumps.

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.

Abstract: A method for producing a component having a semiconductor substrate with through-hole plating is provided, the through-plating being surrounded by a recess, and the semiconductor substrate having a first layer on one side, which covers the recess on the first side. The semiconductor substrate has a second layer on a second side, which covers the recess on the second side, and the through-hole plating is surrounded by a ring structure which is produced from the semiconductor substrate. The recess surrounding the ring structure is produced in the same process step or at the same time as the recess for the through-hole plating.

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of metal terminals that are formed on a surface of the semiconductor substrate on the opposite side to a circuit-forming surface; and a resin that is formed on the surface of the semiconductor substrate on the opposite side to the circuit-forming surface, and covers at least part of side surfaces of the metal terminals, wherein upper surfaces of the metal terminals are exposed from the resin.

Abstract: A method is provided for establishing through substrate vias (TSVs) within a substrate. The method includes: forming at least one recess in a front-side of a wafer; filling, at least partially, the at least one recess with a sacrificial material from the front-side of the wafer; thinning the wafer from a back-side to reveal the at least one recess at least partially filled with the sacrificial material; removing from the back-side of the wafer the sacrificial material from the at least one recess; and filling the at least one recess from the back-side of the wafer with a conductive material to provide the at least one through substrate via.